2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
28 PRIVATE_NAMESPACE_BEGIN
30 static string
spice_id2str(IdString id
)
32 static const char *escape_chars
= "$\\[]()<>=";
33 string s
= RTLIL::unescape_id(id
);
36 if (strchr(escape_chars
, ch
) != nullptr) ch
= '_';
41 static string
spice_id2str(IdString id
, bool use_inames
, idict
<IdString
, 1> &inums
)
43 if (!use_inames
&& *id
.c_str() == '$')
44 return stringf("%d", inums(id
));
45 return spice_id2str(id
);
48 static void print_spice_net(std::ostream
&f
, RTLIL::SigBit s
, std::string
&neg
, std::string
&pos
, std::string
&ncpf
, int &nc_counter
, bool use_inames
, idict
<IdString
, 1> &inums
)
53 if (s
.wire
->width
> 1)
54 f
<< stringf(" %s.%d", spice_id2str(s
.wire
->name
, use_inames
, inums
).c_str(), s
.offset
);
56 f
<< stringf(" %s", spice_id2str(s
.wire
->name
, use_inames
, inums
).c_str());
58 if (s
== RTLIL::State::S0
)
59 f
<< stringf(" %s", neg
.c_str());
60 else if (s
== RTLIL::State::S1
)
61 f
<< stringf(" %s", pos
.c_str());
63 f
<< stringf(" %s%d", ncpf
.c_str(), nc_counter
++);
67 static void print_spice_module(std::ostream
&f
, RTLIL::Module
*module
, RTLIL::Design
*design
, std::string
&neg
, std::string
&pos
, std::string
&ncpf
, bool big_endian
, bool use_inames
)
69 SigMap
sigmap(module
);
70 idict
<IdString
, 1> inums
;
71 int cell_counter
= 0, conn_counter
= 0, nc_counter
= 0;
73 for (auto cell
: module
->cells())
75 f
<< stringf("X%d", cell_counter
++);
77 std::vector
<RTLIL::SigSpec
> port_sigs
;
79 if (design
->module(cell
->type
) == nullptr)
81 log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
82 log_id(cell
->type
), log_id(module
), log_id(cell
));
83 for (auto &conn
: cell
->connections()) {
84 RTLIL::SigSpec sig
= sigmap(conn
.second
);
85 port_sigs
.push_back(sig
);
90 RTLIL::Module
*mod
= design
->module(cell
->type
);
92 std::vector
<RTLIL::Wire
*> ports
;
93 for (auto wire
: mod
->wires()) {
94 if (wire
->port_id
== 0)
96 while (int(ports
.size()) < wire
->port_id
)
97 ports
.push_back(NULL
);
98 ports
.at(wire
->port_id
-1) = wire
;
101 for (RTLIL::Wire
*wire
: ports
) {
102 log_assert(wire
!= NULL
);
103 RTLIL::SigSpec
sig(RTLIL::State::Sz
, wire
->width
);
104 if (cell
->hasPort(wire
->name
)) {
105 sig
= sigmap(cell
->getPort(wire
->name
));
106 sig
.extend_u0(wire
->width
, false);
108 port_sigs
.push_back(sig
);
112 for (auto &sig
: port_sigs
) {
113 for (int i
= 0; i
< sig
.size(); i
++) {
114 RTLIL::SigSpec s
= sig
.extract(big_endian
? sig
.size() - 1 - i
: i
, 1);
115 print_spice_net(f
, s
, neg
, pos
, ncpf
, nc_counter
, use_inames
, inums
);
119 f
<< stringf(" %s\n", spice_id2str(cell
->type
).c_str());
122 for (auto &conn
: module
->connections())
123 for (int i
= 0; i
< conn
.first
.size(); i
++) {
124 f
<< stringf("V%d", conn_counter
++);
125 print_spice_net(f
, conn
.first
.extract(i
, 1), neg
, pos
, ncpf
, nc_counter
, use_inames
, inums
);
126 print_spice_net(f
, conn
.second
.extract(i
, 1), neg
, pos
, ncpf
, nc_counter
, use_inames
, inums
);
127 f
<< stringf(" DC 0\n");
131 struct SpiceBackend
: public Backend
{
132 SpiceBackend() : Backend("spice", "write design to SPICE netlist file") { }
133 void help() YS_OVERRIDE
135 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
137 log(" write_spice [options] [filename]\n");
139 log("Write the current design to an SPICE netlist file.\n");
141 log(" -big_endian\n");
142 log(" generate multi-bit ports in MSB first order\n");
143 log(" (default is LSB first)\n");
145 log(" -neg net_name\n");
146 log(" set the net name for constant 0 (default: Vss)\n");
148 log(" -pos net_name\n");
149 log(" set the net name for constant 1 (default: Vdd)\n");
151 log(" -nc_prefix\n");
152 log(" prefix for not-connected nets (default: _NC)\n");
155 log(" include names of internal ($-prefixed) nets in outputs\n");
156 log(" (default is to use net numbers instead)\n");
158 log(" -top top_module\n");
159 log(" set the specified module as design top module\n");
162 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
164 std::string top_module_name
;
165 RTLIL::Module
*top_module
= NULL
;
166 bool big_endian
= false, use_inames
= false;
167 std::string neg
= "Vss", pos
= "Vdd", ncpf
= "_NC";
169 log_header(design
, "Executing SPICE backend.\n");
172 for (argidx
= 1; argidx
< args
.size(); argidx
++)
174 if (args
[argidx
] == "-big_endian") {
178 if (args
[argidx
] == "-inames") {
182 if (args
[argidx
] == "-neg" && argidx
+1 < args
.size()) {
183 neg
= args
[++argidx
];
186 if (args
[argidx
] == "-pos" && argidx
+1 < args
.size()) {
187 pos
= args
[++argidx
];
190 if (args
[argidx
] == "-nc_prefix" && argidx
+1 < args
.size()) {
191 ncpf
= args
[++argidx
];
194 if (args
[argidx
] == "-top" && argidx
+1 < args
.size()) {
195 top_module_name
= args
[++argidx
];
200 extra_args(f
, filename
, args
, argidx
);
202 if (top_module_name
.empty())
203 for (auto module
: design
->modules())
204 if (module
->get_bool_attribute(ID::top
))
205 top_module_name
= module
->name
.str();
207 *f
<< stringf("* SPICE netlist generated by %s\n", yosys_version_str
);
210 for (auto module
: design
->modules())
212 if (module
->get_blackbox_attribute())
215 if (module
->processes
.size() != 0)
216 log_error("Found unmapped processes in module %s: unmapped processes are not supported in SPICE backend!\n", log_id(module
));
217 if (module
->memories
.size() != 0)
218 log_error("Found unmapped memories in module %s: unmapped memories are not supported in SPICE backend!\n", log_id(module
));
220 if (module
->name
== RTLIL::escape_id(top_module_name
)) {
225 std::vector
<RTLIL::Wire
*> ports
;
226 for (auto wire
: module
->wires()) {
227 if (wire
->port_id
== 0)
229 while (int(ports
.size()) < wire
->port_id
)
230 ports
.push_back(NULL
);
231 ports
.at(wire
->port_id
-1) = wire
;
234 *f
<< stringf(".SUBCKT %s", spice_id2str(module
->name
).c_str());
235 for (RTLIL::Wire
*wire
: ports
) {
236 log_assert(wire
!= NULL
);
237 if (wire
->width
> 1) {
238 for (int i
= 0; i
< wire
->width
; i
++)
239 *f
<< stringf(" %s.%d", spice_id2str(wire
->name
).c_str(), big_endian
? wire
->width
- 1 - i
: i
);
241 *f
<< stringf(" %s", spice_id2str(wire
->name
).c_str());
244 print_spice_module(*f
, module
, design
, neg
, pos
, ncpf
, big_endian
, use_inames
);
245 *f
<< stringf(".ENDS %s\n\n", spice_id2str(module
->name
).c_str());
248 if (!top_module_name
.empty()) {
249 if (top_module
== NULL
)
250 log_error("Can't find top module `%s'!\n", top_module_name
.c_str());
251 print_spice_module(*f
, top_module
, design
, neg
, pos
, ncpf
, big_endian
, use_inames
);
255 *f
<< stringf("************************\n");
256 *f
<< stringf("* end of SPICE netlist *\n");
257 *f
<< stringf("************************\n");
262 PRIVATE_NAMESPACE_END