backends/table/table.cc

   1 /*
   2  *  yosys -- Yosys Open SYnthesis Suite
   3  *
   4  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
   5  *
   6  *  Permission to use, copy, modify, and/or distribute this software for any
   7  *  purpose with or without fee is hereby granted, provided that the above
   8  *  copyright notice and this permission notice appear in all copies.
   9  *
  10  *  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  *  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  *  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  13  *  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  *  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  15  *  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  16  *  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  */
  19
  20 #include "kernel/rtlil.h"
  21 #include "kernel/register.h"
  22 #include "kernel/sigtools.h"
  23 #include "kernel/celltypes.h"
  24 #include "kernel/log.h"
  25 #include <string>
  26
  27 USING_YOSYS_NAMESPACE
  28 PRIVATE_NAMESPACE_BEGIN
  29
  30 struct TableBackend : public Backend {
  31         TableBackend() : Backend("table", "write design as connectivity table") { }
  32         virtual void help()
  33         {
  34                 //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
  35                 log("\n");
  36                 log("    write_table [options] [filename]\n");
  37                 log("\n");
  38                 log("Write the current design as connectivity table. The output is a tab-separated\n");
  39                 log("ASCII table with the following columns:\n");
  40                 log("\n");
  41                 log("  module name\n");
  42                 log("  cell name\n");
  43                 log("  cell type\n");
  44                 log("  cell port\n");
  45                 log("  direction\n");
  46                 log("  signal\n");
  47                 log("\n");
  48                 log("module inputs and outputs are output using cell type and port '-' and with\n");
  49                 log("'pi' (primary input) or 'po' (primary output) or 'pio' as direction.\n");
  50         }
  51         virtual void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
  52         {
  53                 log_header(design, "Executing TABLE backend.\n");
  54
  55                 size_t argidx;
  56                 for (argidx = 1; argidx < args.size(); argidx++)
  57                 {
  58                         // if (args[argidx] == "-top" && argidx+1 < args.size()) {
  59                         //      top_module_name = args[++argidx];
  60                         //      continue;
  61                         // }
  62                         break;
  63                 }
  64                 extra_args(f, filename, args, argidx);
  65
  66                 design->sort();
  67
  68                 for (auto module : design->modules())
  69                 {
  70                         if (module->get_bool_attribute("\\blackbox"))
  71                                 continue;
  72
  73                         SigMap sigmap(module);
  74
  75                         for (auto wire : module->wires())
  76                         {
  77                                 if (wire->port_id == 0)
  78                                         continue;
  79
  80                                 *f << log_id(module) << "\t";
  81                                 *f << log_id(wire) << "\t";
  82                                 *f << "-" << "\t";
  83                                 *f << "-" << "\t";
  84
  85                                 if (wire->port_input && wire->port_output)
  86                                         *f << "pio" << "\t";
  87                                 else if (wire->port_input)
  88                                         *f << "pi" << "\t";
  89                                 else if (wire->port_output)
  90                                         *f << "po" << "\t";
  91                                 else
  92                                         log_abort();
  93
  94                                 *f << log_signal(sigmap(wire)) << "\n";
  95                         }
  96
  97                         for (auto cell : module->cells())
  98                         for (auto conn : cell->connections())
  99                         {
 100                                 *f << log_id(module) << "\t";
 101                                 *f << log_id(cell) << "\t";
 102                                 *f << log_id(cell->type) << "\t";
 103                                 *f << log_id(conn.first) << "\t";
 104
 105                                 if (cell->input(conn.first) && cell->output(conn.first))
 106                                         *f << "inout" << "\t";
 107                                 else if (cell->input(conn.first))
 108                                         *f << "in" << "\t";
 109                                 else if (cell->output(conn.first))
 110                                         *f << "out" << "\t";
 111                                 else
 112                                         *f << "unkown" << "\t";
 113
 114                                 *f << log_signal(sigmap(conn.second)) << "\n";
 115                         }
 116                 }
 117         }
 118 } TableBackend;
 119
 120 PRIVATE_NAMESPACE_END