2 * yosys -- Yosys Open SYnthesis Suite
4 * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include "kernel/rtlil.h"
21 #include "kernel/register.h"
22 #include "kernel/sigtools.h"
23 #include "kernel/celltypes.h"
24 #include "kernel/log.h"
28 PRIVATE_NAMESPACE_BEGIN
30 struct TableBackend
: public Backend
{
31 TableBackend() : Backend("table", "write design as connectivity table") { }
32 void help() YS_OVERRIDE
34 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
36 log(" write_table [options] [filename]\n");
38 log("Write the current design as connectivity table. The output is a tab-separated\n");
39 log("ASCII table with the following columns:\n");
41 log(" module name\n");
48 log("module inputs and outputs are output using cell type and port '-' and with\n");
49 log("'pi' (primary input) or 'po' (primary output) or 'pio' as direction.\n");
51 void execute(std::ostream
*&f
, std::string filename
, std::vector
<std::string
> args
, RTLIL::Design
*design
) YS_OVERRIDE
53 log_header(design
, "Executing TABLE backend.\n");
56 for (argidx
= 1; argidx
< args
.size(); argidx
++)
58 // if (args[argidx] == "-top" && argidx+1 < args.size()) {
59 // top_module_name = args[++argidx];
64 extra_args(f
, filename
, args
, argidx
);
68 for (auto module
: design
->modules())
70 if (module
->get_blackbox_attribute())
73 SigMap
sigmap(module
);
75 for (auto wire
: module
->wires())
77 if (wire
->port_id
== 0)
80 *f
<< log_id(module
) << "\t";
81 *f
<< log_id(wire
) << "\t";
85 if (wire
->port_input
&& wire
->port_output
)
87 else if (wire
->port_input
)
89 else if (wire
->port_output
)
94 *f
<< log_signal(sigmap(wire
)) << "\n";
97 for (auto cell
: module
->cells())
98 for (auto conn
: cell
->connections())
100 *f
<< log_id(module
) << "\t";
101 *f
<< log_id(cell
) << "\t";
102 *f
<< log_id(cell
->type
) << "\t";
103 *f
<< log_id(conn
.first
) << "\t";
105 if (cell
->input(conn
.first
) && cell
->output(conn
.first
))
106 *f
<< "inout" << "\t";
107 else if (cell
->input(conn
.first
))
109 else if (cell
->output(conn
.first
))
112 *f
<< "unknown" << "\t";
114 *f
<< log_signal(sigmap(conn
.second
)) << "\n";
120 PRIVATE_NAMESPACE_END