1 -- Test JTAG in the following way:
2 -- * reset JTAG interface
3 -- * load samplepreload command
4 -- * shift in/out sampled inputs + wanted outputs
5 -- * load extest command
10 use ieee.std_logic_1164.ALL;
12 use work.c4m_jtag.ALL;
14 entity bench_sampleshift is
15 end bench_sampleshift;
17 architecture rtl of bench_sampleshift is
18 signal TCK: std_logic;
19 signal TMS: std_logic;
20 signal TDI: std_logic;
21 signal TDO: std_logic;
22 signal TRST_N: std_logic;
24 constant CLK_PERIOD: time := 10 ns;
27 signal CLK: out std_logic;
32 wait for CLK_PERIOD/4;
34 wait for CLK_PERIOD/2;
36 wait for CLK_PERIOD/4;
41 signal CLK: out std_logic;
46 ClkCycle(CLK, CLK_PERIOD);