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Reimplement DAP stack traces using frame filters
[binutils-gdb.git] / bfd / coff-sh.c
1 /* BFD back-end for Renesas Super-H COFF binaries.
2 Copyright (C) 1993-2023 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4 Written by Steve Chamberlain, <sac@cygnus.com>.
5 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
6
7 This file is part of BFD, the Binary File Descriptor library.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
22 MA 02110-1301, USA. */
23
24 #include "sysdep.h"
25 #include "bfd.h"
26 #include "libiberty.h"
27 #include "libbfd.h"
28 #include "bfdlink.h"
29 #include "coff/sh.h"
30 #include "coff/internal.h"
31
32 #undef bfd_pe_print_pdata
33
34 #ifdef COFF_WITH_PE
35 #include "coff/pe.h"
36
37 #ifndef COFF_IMAGE_WITH_PE
38 static bool sh_align_load_span
39 (bfd *, asection *, bfd_byte *,
40 bool (*) (bfd *, asection *, void *, bfd_byte *, bfd_vma),
41 void *, bfd_vma **, bfd_vma *, bfd_vma, bfd_vma, bool *);
42
43 #define _bfd_sh_align_load_span sh_align_load_span
44 #endif
45
46 #define bfd_pe_print_pdata _bfd_pe_print_ce_compressed_pdata
47
48 #else
49
50 #define bfd_pe_print_pdata NULL
51
52 #endif /* COFF_WITH_PE. */
53
54 #include "libcoff.h"
55
56 /* Internal functions. */
57
58 #ifdef COFF_WITH_PE
59 /* Can't build import tables with 2**4 alignment. */
60 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 2
61 #else
62 /* Default section alignment to 2**4. */
63 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER 4
64 #endif
65
66 #ifdef COFF_IMAGE_WITH_PE
67 /* Align PE executables. */
68 #define COFF_PAGE_SIZE 0x1000
69 #endif
70
71 /* Generate long file names. */
72 #define COFF_LONG_FILENAMES
73
74 #ifdef COFF_WITH_PE
75 /* Return TRUE if this relocation should
76 appear in the output .reloc section. */
77
78 static bool
79 in_reloc_p (bfd * abfd ATTRIBUTE_UNUSED,
80 reloc_howto_type * howto)
81 {
82 return ! howto->pc_relative && howto->type != R_SH_IMAGEBASE;
83 }
84 #endif
85
86 static bfd_reloc_status_type
87 sh_reloc (bfd *, arelent *, asymbol *, void *, asection *, bfd *, char **);
88 static bool
89 sh_relocate_section (bfd *, struct bfd_link_info *, bfd *, asection *,
90 bfd_byte *, struct internal_reloc *,
91 struct internal_syment *, asection **);
92 static bool
93 sh_align_loads (bfd *, asection *, struct internal_reloc *,
94 bfd_byte *, bool *);
95
96 /* The supported relocations. There are a lot of relocations defined
97 in coff/internal.h which we do not expect to ever see. */
98 static reloc_howto_type sh_coff_howtos[] =
99 {
100 EMPTY_HOWTO (0),
101 EMPTY_HOWTO (1),
102 #ifdef COFF_WITH_PE
103 /* Windows CE */
104 HOWTO (R_SH_IMM32CE, /* type */
105 0, /* rightshift */
106 4, /* size */
107 32, /* bitsize */
108 false, /* pc_relative */
109 0, /* bitpos */
110 complain_overflow_bitfield, /* complain_on_overflow */
111 sh_reloc, /* special_function */
112 "r_imm32ce", /* name */
113 true, /* partial_inplace */
114 0xffffffff, /* src_mask */
115 0xffffffff, /* dst_mask */
116 false), /* pcrel_offset */
117 #else
118 EMPTY_HOWTO (2),
119 #endif
120 EMPTY_HOWTO (3), /* R_SH_PCREL8 */
121 EMPTY_HOWTO (4), /* R_SH_PCREL16 */
122 EMPTY_HOWTO (5), /* R_SH_HIGH8 */
123 EMPTY_HOWTO (6), /* R_SH_IMM24 */
124 EMPTY_HOWTO (7), /* R_SH_LOW16 */
125 EMPTY_HOWTO (8),
126 EMPTY_HOWTO (9), /* R_SH_PCDISP8BY4 */
127
128 HOWTO (R_SH_PCDISP8BY2, /* type */
129 1, /* rightshift */
130 2, /* size */
131 8, /* bitsize */
132 true, /* pc_relative */
133 0, /* bitpos */
134 complain_overflow_signed, /* complain_on_overflow */
135 sh_reloc, /* special_function */
136 "r_pcdisp8by2", /* name */
137 true, /* partial_inplace */
138 0xff, /* src_mask */
139 0xff, /* dst_mask */
140 true), /* pcrel_offset */
141
142 EMPTY_HOWTO (11), /* R_SH_PCDISP8 */
143
144 HOWTO (R_SH_PCDISP, /* type */
145 1, /* rightshift */
146 2, /* size */
147 12, /* bitsize */
148 true, /* pc_relative */
149 0, /* bitpos */
150 complain_overflow_signed, /* complain_on_overflow */
151 sh_reloc, /* special_function */
152 "r_pcdisp12by2", /* name */
153 true, /* partial_inplace */
154 0xfff, /* src_mask */
155 0xfff, /* dst_mask */
156 true), /* pcrel_offset */
157
158 EMPTY_HOWTO (13),
159
160 HOWTO (R_SH_IMM32, /* type */
161 0, /* rightshift */
162 4, /* size */
163 32, /* bitsize */
164 false, /* pc_relative */
165 0, /* bitpos */
166 complain_overflow_bitfield, /* complain_on_overflow */
167 sh_reloc, /* special_function */
168 "r_imm32", /* name */
169 true, /* partial_inplace */
170 0xffffffff, /* src_mask */
171 0xffffffff, /* dst_mask */
172 false), /* pcrel_offset */
173
174 EMPTY_HOWTO (15),
175 #ifdef COFF_WITH_PE
176 HOWTO (R_SH_IMAGEBASE, /* type */
177 0, /* rightshift */
178 4, /* size */
179 32, /* bitsize */
180 false, /* pc_relative */
181 0, /* bitpos */
182 complain_overflow_bitfield, /* complain_on_overflow */
183 sh_reloc, /* special_function */
184 "rva32", /* name */
185 true, /* partial_inplace */
186 0xffffffff, /* src_mask */
187 0xffffffff, /* dst_mask */
188 false), /* pcrel_offset */
189 #else
190 EMPTY_HOWTO (16), /* R_SH_IMM8 */
191 #endif
192 EMPTY_HOWTO (17), /* R_SH_IMM8BY2 */
193 EMPTY_HOWTO (18), /* R_SH_IMM8BY4 */
194 EMPTY_HOWTO (19), /* R_SH_IMM4 */
195 EMPTY_HOWTO (20), /* R_SH_IMM4BY2 */
196 EMPTY_HOWTO (21), /* R_SH_IMM4BY4 */
197
198 HOWTO (R_SH_PCRELIMM8BY2, /* type */
199 1, /* rightshift */
200 2, /* size */
201 8, /* bitsize */
202 true, /* pc_relative */
203 0, /* bitpos */
204 complain_overflow_unsigned, /* complain_on_overflow */
205 sh_reloc, /* special_function */
206 "r_pcrelimm8by2", /* name */
207 true, /* partial_inplace */
208 0xff, /* src_mask */
209 0xff, /* dst_mask */
210 true), /* pcrel_offset */
211
212 HOWTO (R_SH_PCRELIMM8BY4, /* type */
213 2, /* rightshift */
214 2, /* size */
215 8, /* bitsize */
216 true, /* pc_relative */
217 0, /* bitpos */
218 complain_overflow_unsigned, /* complain_on_overflow */
219 sh_reloc, /* special_function */
220 "r_pcrelimm8by4", /* name */
221 true, /* partial_inplace */
222 0xff, /* src_mask */
223 0xff, /* dst_mask */
224 true), /* pcrel_offset */
225
226 HOWTO (R_SH_IMM16, /* type */
227 0, /* rightshift */
228 2, /* size */
229 16, /* bitsize */
230 false, /* pc_relative */
231 0, /* bitpos */
232 complain_overflow_bitfield, /* complain_on_overflow */
233 sh_reloc, /* special_function */
234 "r_imm16", /* name */
235 true, /* partial_inplace */
236 0xffff, /* src_mask */
237 0xffff, /* dst_mask */
238 false), /* pcrel_offset */
239
240 HOWTO (R_SH_SWITCH16, /* type */
241 0, /* rightshift */
242 2, /* size */
243 16, /* bitsize */
244 false, /* pc_relative */
245 0, /* bitpos */
246 complain_overflow_bitfield, /* complain_on_overflow */
247 sh_reloc, /* special_function */
248 "r_switch16", /* name */
249 true, /* partial_inplace */
250 0xffff, /* src_mask */
251 0xffff, /* dst_mask */
252 false), /* pcrel_offset */
253
254 HOWTO (R_SH_SWITCH32, /* type */
255 0, /* rightshift */
256 4, /* size */
257 32, /* bitsize */
258 false, /* pc_relative */
259 0, /* bitpos */
260 complain_overflow_bitfield, /* complain_on_overflow */
261 sh_reloc, /* special_function */
262 "r_switch32", /* name */
263 true, /* partial_inplace */
264 0xffffffff, /* src_mask */
265 0xffffffff, /* dst_mask */
266 false), /* pcrel_offset */
267
268 HOWTO (R_SH_USES, /* type */
269 0, /* rightshift */
270 2, /* size */
271 16, /* bitsize */
272 false, /* pc_relative */
273 0, /* bitpos */
274 complain_overflow_bitfield, /* complain_on_overflow */
275 sh_reloc, /* special_function */
276 "r_uses", /* name */
277 true, /* partial_inplace */
278 0xffff, /* src_mask */
279 0xffff, /* dst_mask */
280 false), /* pcrel_offset */
281
282 HOWTO (R_SH_COUNT, /* type */
283 0, /* rightshift */
284 4, /* size */
285 32, /* bitsize */
286 false, /* pc_relative */
287 0, /* bitpos */
288 complain_overflow_bitfield, /* complain_on_overflow */
289 sh_reloc, /* special_function */
290 "r_count", /* name */
291 true, /* partial_inplace */
292 0xffffffff, /* src_mask */
293 0xffffffff, /* dst_mask */
294 false), /* pcrel_offset */
295
296 HOWTO (R_SH_ALIGN, /* type */
297 0, /* rightshift */
298 4, /* size */
299 32, /* bitsize */
300 false, /* pc_relative */
301 0, /* bitpos */
302 complain_overflow_bitfield, /* complain_on_overflow */
303 sh_reloc, /* special_function */
304 "r_align", /* name */
305 true, /* partial_inplace */
306 0xffffffff, /* src_mask */
307 0xffffffff, /* dst_mask */
308 false), /* pcrel_offset */
309
310 HOWTO (R_SH_CODE, /* type */
311 0, /* rightshift */
312 4, /* size */
313 32, /* bitsize */
314 false, /* pc_relative */
315 0, /* bitpos */
316 complain_overflow_bitfield, /* complain_on_overflow */
317 sh_reloc, /* special_function */
318 "r_code", /* name */
319 true, /* partial_inplace */
320 0xffffffff, /* src_mask */
321 0xffffffff, /* dst_mask */
322 false), /* pcrel_offset */
323
324 HOWTO (R_SH_DATA, /* type */
325 0, /* rightshift */
326 4, /* size */
327 32, /* bitsize */
328 false, /* pc_relative */
329 0, /* bitpos */
330 complain_overflow_bitfield, /* complain_on_overflow */
331 sh_reloc, /* special_function */
332 "r_data", /* name */
333 true, /* partial_inplace */
334 0xffffffff, /* src_mask */
335 0xffffffff, /* dst_mask */
336 false), /* pcrel_offset */
337
338 HOWTO (R_SH_LABEL, /* type */
339 0, /* rightshift */
340 4, /* size */
341 32, /* bitsize */
342 false, /* pc_relative */
343 0, /* bitpos */
344 complain_overflow_bitfield, /* complain_on_overflow */
345 sh_reloc, /* special_function */
346 "r_label", /* name */
347 true, /* partial_inplace */
348 0xffffffff, /* src_mask */
349 0xffffffff, /* dst_mask */
350 false), /* pcrel_offset */
351
352 HOWTO (R_SH_SWITCH8, /* type */
353 0, /* rightshift */
354 1, /* size */
355 8, /* bitsize */
356 false, /* pc_relative */
357 0, /* bitpos */
358 complain_overflow_bitfield, /* complain_on_overflow */
359 sh_reloc, /* special_function */
360 "r_switch8", /* name */
361 true, /* partial_inplace */
362 0xff, /* src_mask */
363 0xff, /* dst_mask */
364 false) /* pcrel_offset */
365 };
366
367 #define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
368
369 /* Check for a bad magic number. */
370 #define BADMAG(x) SHBADMAG(x)
371
372 /* Customize coffcode.h (this is not currently used). */
373 #define SH 1
374
375 /* FIXME: This should not be set here. */
376 #define __A_MAGIC_SET__
377
378 #ifndef COFF_WITH_PE
379 /* Swap the r_offset field in and out. */
380 #define SWAP_IN_RELOC_OFFSET H_GET_32
381 #define SWAP_OUT_RELOC_OFFSET H_PUT_32
382
383 /* Swap out extra information in the reloc structure. */
384 #define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
385 do \
386 { \
387 dst->r_stuff[0] = 'S'; \
388 dst->r_stuff[1] = 'C'; \
389 } \
390 while (0)
391 #endif
392
393 /* Get the value of a symbol, when performing a relocation. */
394
395 static long
396 get_symbol_value (asymbol *symbol)
397 {
398 bfd_vma relocation;
399
400 if (bfd_is_com_section (symbol->section))
401 relocation = 0;
402 else
403 relocation = (symbol->value +
404 symbol->section->output_section->vma +
405 symbol->section->output_offset);
406
407 return relocation;
408 }
409
410 #ifdef COFF_WITH_PE
411 /* Convert an rtype to howto for the COFF backend linker.
412 Copied from coff-i386. */
413 #define coff_rtype_to_howto coff_sh_rtype_to_howto
414
415
416 static reloc_howto_type *
417 coff_sh_rtype_to_howto (bfd * abfd ATTRIBUTE_UNUSED,
418 asection * sec,
419 struct internal_reloc * rel,
420 struct coff_link_hash_entry * h,
421 struct internal_syment * sym,
422 bfd_vma * addendp)
423 {
424 reloc_howto_type * howto;
425
426 howto = sh_coff_howtos + rel->r_type;
427
428 *addendp = 0;
429
430 if (howto->pc_relative)
431 *addendp += sec->vma;
432
433 if (sym != NULL && sym->n_scnum == 0 && sym->n_value != 0)
434 {
435 /* This is a common symbol. The section contents include the
436 size (sym->n_value) as an addend. The relocate_section
437 function will be adding in the final value of the symbol. We
438 need to subtract out the current size in order to get the
439 correct result. */
440 BFD_ASSERT (h != NULL);
441 }
442
443 if (howto->pc_relative)
444 {
445 *addendp -= 4;
446
447 /* If the symbol is defined, then the generic code is going to
448 add back the symbol value in order to cancel out an
449 adjustment it made to the addend. However, we set the addend
450 to 0 at the start of this function. We need to adjust here,
451 to avoid the adjustment the generic code will make. FIXME:
452 This is getting a bit hackish. */
453 if (sym != NULL && sym->n_scnum != 0)
454 *addendp -= sym->n_value;
455 }
456
457 if (rel->r_type == R_SH_IMAGEBASE)
458 *addendp -= pe_data (sec->output_section->owner)->pe_opthdr.ImageBase;
459
460 return howto;
461 }
462
463 #endif /* COFF_WITH_PE */
464
465 /* This structure is used to map BFD reloc codes to SH PE relocs. */
466 struct shcoff_reloc_map
467 {
468 bfd_reloc_code_real_type bfd_reloc_val;
469 unsigned char shcoff_reloc_val;
470 };
471
472 #ifdef COFF_WITH_PE
473 /* An array mapping BFD reloc codes to SH PE relocs. */
474 static const struct shcoff_reloc_map sh_reloc_map[] =
475 {
476 { BFD_RELOC_32, R_SH_IMM32CE },
477 { BFD_RELOC_RVA, R_SH_IMAGEBASE },
478 { BFD_RELOC_CTOR, R_SH_IMM32CE },
479 };
480 #else
481 /* An array mapping BFD reloc codes to SH PE relocs. */
482 static const struct shcoff_reloc_map sh_reloc_map[] =
483 {
484 { BFD_RELOC_32, R_SH_IMM32 },
485 { BFD_RELOC_CTOR, R_SH_IMM32 },
486 };
487 #endif
488
489 /* Given a BFD reloc code, return the howto structure for the
490 corresponding SH PE reloc. */
491 #define coff_bfd_reloc_type_lookup sh_coff_reloc_type_lookup
492 #define coff_bfd_reloc_name_lookup sh_coff_reloc_name_lookup
493
494 static reloc_howto_type *
495 sh_coff_reloc_type_lookup (bfd *abfd,
496 bfd_reloc_code_real_type code)
497 {
498 unsigned int i;
499
500 for (i = ARRAY_SIZE (sh_reloc_map); i--;)
501 if (sh_reloc_map[i].bfd_reloc_val == code)
502 return &sh_coff_howtos[(int) sh_reloc_map[i].shcoff_reloc_val];
503
504 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
505 abfd, (unsigned int) code);
506 return NULL;
507 }
508
509 static reloc_howto_type *
510 sh_coff_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
511 const char *r_name)
512 {
513 unsigned int i;
514
515 for (i = 0; i < sizeof (sh_coff_howtos) / sizeof (sh_coff_howtos[0]); i++)
516 if (sh_coff_howtos[i].name != NULL
517 && strcasecmp (sh_coff_howtos[i].name, r_name) == 0)
518 return &sh_coff_howtos[i];
519
520 return NULL;
521 }
522
523 /* This macro is used in coffcode.h to get the howto corresponding to
524 an internal reloc. */
525
526 #define RTYPE2HOWTO(relent, internal) \
527 ((relent)->howto = \
528 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
529 ? &sh_coff_howtos[(internal)->r_type] \
530 : (reloc_howto_type *) NULL))
531
532 /* This is the same as the macro in coffcode.h, except that it copies
533 r_offset into reloc_entry->addend for some relocs. */
534 #define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
535 { \
536 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
537 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
538 coffsym = (obj_symbols (abfd) \
539 + (cache_ptr->sym_ptr_ptr - symbols)); \
540 else if (ptr) \
541 coffsym = coff_symbol_from (ptr); \
542 if (coffsym != (coff_symbol_type *) NULL \
543 && coffsym->native->u.syment.n_scnum == 0) \
544 cache_ptr->addend = 0; \
545 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
546 && ptr->section != (asection *) NULL) \
547 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
548 else \
549 cache_ptr->addend = 0; \
550 if ((reloc).r_type == R_SH_SWITCH8 \
551 || (reloc).r_type == R_SH_SWITCH16 \
552 || (reloc).r_type == R_SH_SWITCH32 \
553 || (reloc).r_type == R_SH_USES \
554 || (reloc).r_type == R_SH_COUNT \
555 || (reloc).r_type == R_SH_ALIGN) \
556 cache_ptr->addend = (reloc).r_offset; \
557 }
558
559 /* This is the howto function for the SH relocations. */
560
561 static bfd_reloc_status_type
562 sh_reloc (bfd * abfd,
563 arelent * reloc_entry,
564 asymbol * symbol_in,
565 void * data,
566 asection * input_section,
567 bfd * output_bfd,
568 char ** error_message ATTRIBUTE_UNUSED)
569 {
570 bfd_vma insn;
571 bfd_vma sym_value;
572 unsigned short r_type;
573 bfd_vma addr = reloc_entry->address;
574 bfd_byte *hit_data = addr + (bfd_byte *) data;
575
576 r_type = reloc_entry->howto->type;
577
578 if (output_bfd != NULL)
579 {
580 /* Partial linking--do nothing. */
581 reloc_entry->address += input_section->output_offset;
582 return bfd_reloc_ok;
583 }
584
585 /* Almost all relocs have to do with relaxing. If any work must be
586 done for them, it has been done in sh_relax_section. */
587 if (r_type != R_SH_IMM32
588 #ifdef COFF_WITH_PE
589 && r_type != R_SH_IMM32CE
590 && r_type != R_SH_IMAGEBASE
591 #endif
592 && (r_type != R_SH_PCDISP
593 || (symbol_in->flags & BSF_LOCAL) != 0))
594 return bfd_reloc_ok;
595
596 if (symbol_in != NULL
597 && bfd_is_und_section (symbol_in->section))
598 return bfd_reloc_undefined;
599
600 if (!bfd_reloc_offset_in_range (reloc_entry->howto, abfd, input_section,
601 addr))
602 return bfd_reloc_outofrange;
603
604 sym_value = get_symbol_value (symbol_in);
605
606 switch (r_type)
607 {
608 case R_SH_IMM32:
609 #ifdef COFF_WITH_PE
610 case R_SH_IMM32CE:
611 #endif
612 insn = bfd_get_32 (abfd, hit_data);
613 insn += sym_value + reloc_entry->addend;
614 bfd_put_32 (abfd, insn, hit_data);
615 break;
616 #ifdef COFF_WITH_PE
617 case R_SH_IMAGEBASE:
618 insn = bfd_get_32 (abfd, hit_data);
619 insn += sym_value + reloc_entry->addend;
620 insn -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
621 bfd_put_32 (abfd, insn, hit_data);
622 break;
623 #endif
624 case R_SH_PCDISP:
625 insn = bfd_get_16 (abfd, hit_data);
626 sym_value += reloc_entry->addend;
627 sym_value -= (input_section->output_section->vma
628 + input_section->output_offset
629 + addr
630 + 4);
631 sym_value += (((insn & 0xfff) ^ 0x800) - 0x800) << 1;
632 insn = (insn & 0xf000) | ((sym_value >> 1) & 0xfff);
633 bfd_put_16 (abfd, insn, hit_data);
634 if (sym_value + 0x1000 >= 0x2000 || (sym_value & 1) != 0)
635 return bfd_reloc_overflow;
636 break;
637 default:
638 abort ();
639 break;
640 }
641
642 return bfd_reloc_ok;
643 }
644
645 #define coff_bfd_merge_private_bfd_data _bfd_generic_verify_endian_match
646
647 /* We can do relaxing. */
648 #define coff_bfd_relax_section sh_relax_section
649
650 /* We use the special COFF backend linker. */
651 #define coff_relocate_section sh_relocate_section
652
653 /* When relaxing, we need to use special code to get the relocated
654 section contents. */
655 #define coff_bfd_get_relocated_section_contents \
656 sh_coff_get_relocated_section_contents
657
658 #include "coffcode.h"
659 \f
660 static bool
661 sh_relax_delete_bytes (bfd *, asection *, bfd_vma, int);
662
663 /* This function handles relaxing on the SH.
664
665 Function calls on the SH look like this:
666
667 movl L1,r0
668 ...
669 jsr @r0
670 ...
671 L1:
672 .long function
673
674 The compiler and assembler will cooperate to create R_SH_USES
675 relocs on the jsr instructions. The r_offset field of the
676 R_SH_USES reloc is the PC relative offset to the instruction which
677 loads the register (the r_offset field is computed as though it
678 were a jump instruction, so the offset value is actually from four
679 bytes past the instruction). The linker can use this reloc to
680 determine just which function is being called, and thus decide
681 whether it is possible to replace the jsr with a bsr.
682
683 If multiple function calls are all based on a single register load
684 (i.e., the same function is called multiple times), the compiler
685 guarantees that each function call will have an R_SH_USES reloc.
686 Therefore, if the linker is able to convert each R_SH_USES reloc
687 which refers to that address, it can safely eliminate the register
688 load.
689
690 When the assembler creates an R_SH_USES reloc, it examines it to
691 determine which address is being loaded (L1 in the above example).
692 It then counts the number of references to that address, and
693 creates an R_SH_COUNT reloc at that address. The r_offset field of
694 the R_SH_COUNT reloc will be the number of references. If the
695 linker is able to eliminate a register load, it can use the
696 R_SH_COUNT reloc to see whether it can also eliminate the function
697 address.
698
699 SH relaxing also handles another, unrelated, matter. On the SH, if
700 a load or store instruction is not aligned on a four byte boundary,
701 the memory cycle interferes with the 32 bit instruction fetch,
702 causing a one cycle bubble in the pipeline. Therefore, we try to
703 align load and store instructions on four byte boundaries if we
704 can, by swapping them with one of the adjacent instructions. */
705
706 static bool
707 sh_relax_section (bfd *abfd,
708 asection *sec,
709 struct bfd_link_info *link_info,
710 bool *again)
711 {
712 struct internal_reloc *internal_relocs;
713 bool have_code;
714 struct internal_reloc *irel, *irelend;
715 bfd_byte *contents = NULL;
716
717 *again = false;
718
719 if (bfd_link_relocatable (link_info)
720 || (sec->flags & SEC_HAS_CONTENTS) == 0
721 || (sec->flags & SEC_RELOC) == 0
722 || sec->reloc_count == 0)
723 return true;
724
725 if (coff_section_data (abfd, sec) == NULL)
726 {
727 size_t amt = sizeof (struct coff_section_tdata);
728 sec->used_by_bfd = bfd_zalloc (abfd, amt);
729 if (sec->used_by_bfd == NULL)
730 return false;
731 }
732
733 internal_relocs = (_bfd_coff_read_internal_relocs
734 (abfd, sec, link_info->keep_memory,
735 (bfd_byte *) NULL, false,
736 (struct internal_reloc *) NULL));
737 if (internal_relocs == NULL)
738 goto error_return;
739
740 have_code = false;
741
742 irelend = internal_relocs + sec->reloc_count;
743 for (irel = internal_relocs; irel < irelend; irel++)
744 {
745 bfd_vma laddr, paddr, symval;
746 unsigned short insn;
747 struct internal_reloc *irelfn, *irelscan, *irelcount;
748 struct internal_syment sym;
749 bfd_signed_vma foff;
750
751 if (irel->r_type == R_SH_CODE)
752 have_code = true;
753
754 if (irel->r_type != R_SH_USES)
755 continue;
756
757 /* Get the section contents. */
758 if (contents == NULL)
759 {
760 if (coff_section_data (abfd, sec)->contents != NULL)
761 contents = coff_section_data (abfd, sec)->contents;
762 else
763 {
764 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
765 goto error_return;
766 }
767 }
768
769 /* The r_offset field of the R_SH_USES reloc will point us to
770 the register load. The 4 is because the r_offset field is
771 computed as though it were a jump offset, which are based
772 from 4 bytes after the jump instruction. */
773 laddr = irel->r_vaddr - sec->vma + 4;
774 /* Careful to sign extend the 32-bit offset. */
775 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
776 if (laddr >= sec->size)
777 {
778 /* xgettext: c-format */
779 _bfd_error_handler
780 (_("%pB: %#" PRIx64 ": warning: bad R_SH_USES offset"),
781 abfd, (uint64_t) irel->r_vaddr);
782 continue;
783 }
784 insn = bfd_get_16 (abfd, contents + laddr);
785
786 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
787 if ((insn & 0xf000) != 0xd000)
788 {
789 _bfd_error_handler
790 /* xgettext: c-format */
791 (_("%pB: %#" PRIx64 ": warning: R_SH_USES points to unrecognized insn %#x"),
792 abfd, (uint64_t) irel->r_vaddr, insn);
793 continue;
794 }
795
796 /* Get the address from which the register is being loaded. The
797 displacement in the mov.l instruction is quadrupled. It is a
798 displacement from four bytes after the movl instruction, but,
799 before adding in the PC address, two least significant bits
800 of the PC are cleared. We assume that the section is aligned
801 on a four byte boundary. */
802 paddr = insn & 0xff;
803 paddr *= 4;
804 paddr += (laddr + 4) &~ (bfd_vma) 3;
805 if (paddr >= sec->size)
806 {
807 _bfd_error_handler
808 /* xgettext: c-format */
809 (_("%pB: %#" PRIx64 ": warning: bad R_SH_USES load offset"),
810 abfd, (uint64_t) irel->r_vaddr);
811 continue;
812 }
813
814 /* Get the reloc for the address from which the register is
815 being loaded. This reloc will tell us which function is
816 actually being called. */
817 paddr += sec->vma;
818 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
819 if (irelfn->r_vaddr == paddr
820 #ifdef COFF_WITH_PE
821 && (irelfn->r_type == R_SH_IMM32
822 || irelfn->r_type == R_SH_IMM32CE
823 || irelfn->r_type == R_SH_IMAGEBASE)
824
825 #else
826 && irelfn->r_type == R_SH_IMM32
827 #endif
828 )
829 break;
830 if (irelfn >= irelend)
831 {
832 _bfd_error_handler
833 /* xgettext: c-format */
834 (_("%pB: %#" PRIx64 ": warning: could not find expected reloc"),
835 abfd, (uint64_t) paddr);
836 continue;
837 }
838
839 /* Get the value of the symbol referred to by the reloc. */
840 if (! _bfd_coff_get_external_symbols (abfd))
841 goto error_return;
842 bfd_coff_swap_sym_in (abfd,
843 ((bfd_byte *) obj_coff_external_syms (abfd)
844 + (irelfn->r_symndx
845 * bfd_coff_symesz (abfd))),
846 &sym);
847 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
848 {
849 _bfd_error_handler
850 /* xgettext: c-format */
851 (_("%pB: %#" PRIx64 ": warning: symbol in unexpected section"),
852 abfd, (uint64_t) paddr);
853 continue;
854 }
855
856 if (sym.n_sclass != C_EXT)
857 {
858 symval = (sym.n_value
859 - sec->vma
860 + sec->output_section->vma
861 + sec->output_offset);
862 }
863 else
864 {
865 struct coff_link_hash_entry *h;
866
867 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
868 BFD_ASSERT (h != NULL);
869 if (h->root.type != bfd_link_hash_defined
870 && h->root.type != bfd_link_hash_defweak)
871 {
872 /* This appears to be a reference to an undefined
873 symbol. Just ignore it--it will be caught by the
874 regular reloc processing. */
875 continue;
876 }
877
878 symval = (h->root.u.def.value
879 + h->root.u.def.section->output_section->vma
880 + h->root.u.def.section->output_offset);
881 }
882
883 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
884
885 /* See if this function call can be shortened. */
886 foff = (symval
887 - (irel->r_vaddr
888 - sec->vma
889 + sec->output_section->vma
890 + sec->output_offset
891 + 4));
892 if (foff < -0x1000 || foff >= 0x1000)
893 {
894 /* After all that work, we can't shorten this function call. */
895 continue;
896 }
897
898 /* Shorten the function call. */
899
900 /* For simplicity of coding, we are going to modify the section
901 contents, the section relocs, and the BFD symbol table. We
902 must tell the rest of the code not to free up this
903 information. It would be possible to instead create a table
904 of changes which have to be made, as is done in coff-mips.c;
905 that would be more work, but would require less memory when
906 the linker is run. */
907
908 coff_section_data (abfd, sec)->relocs = internal_relocs;
909 coff_section_data (abfd, sec)->contents = contents;
910
911 /* Replace the jsr with a bsr. */
912
913 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
914 replace the jsr with a bsr. */
915 irel->r_type = R_SH_PCDISP;
916 irel->r_symndx = irelfn->r_symndx;
917 if (sym.n_sclass != C_EXT)
918 {
919 /* If this needs to be changed because of future relaxing,
920 it will be handled here like other internal PCDISP
921 relocs. */
922 bfd_put_16 (abfd,
923 (bfd_vma) 0xb000 | ((foff >> 1) & 0xfff),
924 contents + irel->r_vaddr - sec->vma);
925 }
926 else
927 {
928 /* We can't fully resolve this yet, because the external
929 symbol value may be changed by future relaxing. We let
930 the final link phase handle it. */
931 bfd_put_16 (abfd, (bfd_vma) 0xb000,
932 contents + irel->r_vaddr - sec->vma);
933 }
934
935 /* See if there is another R_SH_USES reloc referring to the same
936 register load. */
937 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
938 if (irelscan->r_type == R_SH_USES
939 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
940 break;
941 if (irelscan < irelend)
942 {
943 /* Some other function call depends upon this register load,
944 and we have not yet converted that function call.
945 Indeed, we may never be able to convert it. There is
946 nothing else we can do at this point. */
947 continue;
948 }
949
950 /* Look for a R_SH_COUNT reloc on the location where the
951 function address is stored. Do this before deleting any
952 bytes, to avoid confusion about the address. */
953 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
954 if (irelcount->r_vaddr == paddr
955 && irelcount->r_type == R_SH_COUNT)
956 break;
957
958 /* Delete the register load. */
959 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
960 goto error_return;
961
962 /* That will change things, so, just in case it permits some
963 other function call to come within range, we should relax
964 again. Note that this is not required, and it may be slow. */
965 *again = true;
966
967 /* Now check whether we got a COUNT reloc. */
968 if (irelcount >= irelend)
969 {
970 _bfd_error_handler
971 /* xgettext: c-format */
972 (_("%pB: %#" PRIx64 ": warning: could not find expected COUNT reloc"),
973 abfd, (uint64_t) paddr);
974 continue;
975 }
976
977 /* The number of uses is stored in the r_offset field. We've
978 just deleted one. */
979 if (irelcount->r_offset == 0)
980 {
981 /* xgettext: c-format */
982 _bfd_error_handler (_("%pB: %#" PRIx64 ": warning: bad count"),
983 abfd, (uint64_t) paddr);
984 continue;
985 }
986
987 --irelcount->r_offset;
988
989 /* If there are no more uses, we can delete the address. Reload
990 the address from irelfn, in case it was changed by the
991 previous call to sh_relax_delete_bytes. */
992 if (irelcount->r_offset == 0)
993 {
994 if (! sh_relax_delete_bytes (abfd, sec,
995 irelfn->r_vaddr - sec->vma, 4))
996 goto error_return;
997 }
998
999 /* We've done all we can with that function call. */
1000 }
1001
1002 /* Look for load and store instructions that we can align on four
1003 byte boundaries. */
1004 if (have_code)
1005 {
1006 bool swapped;
1007
1008 /* Get the section contents. */
1009 if (contents == NULL)
1010 {
1011 if (coff_section_data (abfd, sec)->contents != NULL)
1012 contents = coff_section_data (abfd, sec)->contents;
1013 else
1014 {
1015 if (!bfd_malloc_and_get_section (abfd, sec, &contents))
1016 goto error_return;
1017 }
1018 }
1019
1020 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
1021 goto error_return;
1022
1023 if (swapped)
1024 {
1025 coff_section_data (abfd, sec)->relocs = internal_relocs;
1026 coff_section_data (abfd, sec)->contents = contents;
1027 }
1028 }
1029
1030 if (internal_relocs != NULL
1031 && internal_relocs != coff_section_data (abfd, sec)->relocs)
1032 {
1033 if (! link_info->keep_memory)
1034 free (internal_relocs);
1035 else
1036 coff_section_data (abfd, sec)->relocs = internal_relocs;
1037 }
1038
1039 if (contents != NULL && contents != coff_section_data (abfd, sec)->contents)
1040 {
1041 if (! link_info->keep_memory)
1042 free (contents);
1043 else
1044 /* Cache the section contents for coff_link_input_bfd. */
1045 coff_section_data (abfd, sec)->contents = contents;
1046 }
1047
1048 return true;
1049
1050 error_return:
1051 if (internal_relocs != coff_section_data (abfd, sec)->relocs)
1052 free (internal_relocs);
1053 if (contents != coff_section_data (abfd, sec)->contents)
1054 free (contents);
1055 return false;
1056 }
1057
1058 /* Delete some bytes from a section while relaxing. */
1059
1060 static bool
1061 sh_relax_delete_bytes (bfd *abfd,
1062 asection *sec,
1063 bfd_vma addr,
1064 int count)
1065 {
1066 bfd_byte *contents;
1067 struct internal_reloc *irel, *irelend;
1068 struct internal_reloc *irelalign;
1069 bfd_vma toaddr;
1070 bfd_byte *esym, *esymend;
1071 bfd_size_type symesz;
1072 struct coff_link_hash_entry **sym_hash;
1073 asection *o;
1074
1075 contents = coff_section_data (abfd, sec)->contents;
1076
1077 /* The deletion must stop at the next ALIGN reloc for an alignment
1078 power larger than the number of bytes we are deleting. */
1079
1080 irelalign = NULL;
1081 toaddr = sec->size;
1082
1083 irel = coff_section_data (abfd, sec)->relocs;
1084 irelend = irel + sec->reloc_count;
1085 for (; irel < irelend; irel++)
1086 {
1087 if (irel->r_type == R_SH_ALIGN
1088 && irel->r_vaddr - sec->vma > addr
1089 && count < (1 << irel->r_offset))
1090 {
1091 irelalign = irel;
1092 toaddr = irel->r_vaddr - sec->vma;
1093 break;
1094 }
1095 }
1096
1097 /* Actually delete the bytes. */
1098 memmove (contents + addr, contents + addr + count,
1099 (size_t) (toaddr - addr - count));
1100 if (irelalign == NULL)
1101 sec->size -= count;
1102 else
1103 {
1104 int i;
1105
1106 #define NOP_OPCODE (0x0009)
1107
1108 BFD_ASSERT ((count & 1) == 0);
1109 for (i = 0; i < count; i += 2)
1110 bfd_put_16 (abfd, (bfd_vma) NOP_OPCODE, contents + toaddr - count + i);
1111 }
1112
1113 /* Adjust all the relocs. */
1114 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
1115 {
1116 bfd_vma nraddr, stop;
1117 bfd_vma start = 0;
1118 int insn = 0;
1119 struct internal_syment sym;
1120 int off, adjust, oinsn;
1121 bfd_signed_vma voff = 0;
1122 bool overflow;
1123
1124 /* Get the new reloc address. */
1125 nraddr = irel->r_vaddr - sec->vma;
1126 if ((irel->r_vaddr - sec->vma > addr
1127 && irel->r_vaddr - sec->vma < toaddr)
1128 || (irel->r_type == R_SH_ALIGN
1129 && irel->r_vaddr - sec->vma == toaddr))
1130 nraddr -= count;
1131
1132 /* See if this reloc was for the bytes we have deleted, in which
1133 case we no longer care about it. Don't delete relocs which
1134 represent addresses, though. */
1135 if (irel->r_vaddr - sec->vma >= addr
1136 && irel->r_vaddr - sec->vma < addr + count
1137 && irel->r_type != R_SH_ALIGN
1138 && irel->r_type != R_SH_CODE
1139 && irel->r_type != R_SH_DATA
1140 && irel->r_type != R_SH_LABEL)
1141 irel->r_type = R_SH_UNUSED;
1142
1143 /* If this is a PC relative reloc, see if the range it covers
1144 includes the bytes we have deleted. */
1145 switch (irel->r_type)
1146 {
1147 default:
1148 break;
1149
1150 case R_SH_PCDISP8BY2:
1151 case R_SH_PCDISP:
1152 case R_SH_PCRELIMM8BY2:
1153 case R_SH_PCRELIMM8BY4:
1154 start = irel->r_vaddr - sec->vma;
1155 insn = bfd_get_16 (abfd, contents + nraddr);
1156 break;
1157 }
1158
1159 switch (irel->r_type)
1160 {
1161 default:
1162 start = stop = addr;
1163 break;
1164
1165 case R_SH_IMM32:
1166 #ifdef COFF_WITH_PE
1167 case R_SH_IMM32CE:
1168 case R_SH_IMAGEBASE:
1169 #endif
1170 /* If this reloc is against a symbol defined in this
1171 section, and the symbol will not be adjusted below, we
1172 must check the addend to see it will put the value in
1173 range to be adjusted, and hence must be changed. */
1174 bfd_coff_swap_sym_in (abfd,
1175 ((bfd_byte *) obj_coff_external_syms (abfd)
1176 + (irel->r_symndx
1177 * bfd_coff_symesz (abfd))),
1178 &sym);
1179 if (sym.n_sclass != C_EXT
1180 && sym.n_scnum == sec->target_index
1181 && ((bfd_vma) sym.n_value <= addr
1182 || (bfd_vma) sym.n_value >= toaddr))
1183 {
1184 bfd_vma val;
1185
1186 val = bfd_get_32 (abfd, contents + nraddr);
1187 val += sym.n_value;
1188 if (val > addr && val < toaddr)
1189 bfd_put_32 (abfd, val - count, contents + nraddr);
1190 }
1191 start = stop = addr;
1192 break;
1193
1194 case R_SH_PCDISP8BY2:
1195 off = insn & 0xff;
1196 if (off & 0x80)
1197 off -= 0x100;
1198 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1199 break;
1200
1201 case R_SH_PCDISP:
1202 bfd_coff_swap_sym_in (abfd,
1203 ((bfd_byte *) obj_coff_external_syms (abfd)
1204 + (irel->r_symndx
1205 * bfd_coff_symesz (abfd))),
1206 &sym);
1207 if (sym.n_sclass == C_EXT)
1208 start = stop = addr;
1209 else
1210 {
1211 off = insn & 0xfff;
1212 if (off & 0x800)
1213 off -= 0x1000;
1214 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1215 }
1216 break;
1217
1218 case R_SH_PCRELIMM8BY2:
1219 off = insn & 0xff;
1220 stop = start + 4 + off * 2;
1221 break;
1222
1223 case R_SH_PCRELIMM8BY4:
1224 off = insn & 0xff;
1225 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1226 break;
1227
1228 case R_SH_SWITCH8:
1229 case R_SH_SWITCH16:
1230 case R_SH_SWITCH32:
1231 /* These relocs types represent
1232 .word L2-L1
1233 The r_offset field holds the difference between the reloc
1234 address and L1. That is the start of the reloc, and
1235 adding in the contents gives us the top. We must adjust
1236 both the r_offset field and the section contents. */
1237
1238 start = irel->r_vaddr - sec->vma;
1239 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1240
1241 if (start > addr
1242 && start < toaddr
1243 && (stop <= addr || stop >= toaddr))
1244 irel->r_offset += count;
1245 else if (stop > addr
1246 && stop < toaddr
1247 && (start <= addr || start >= toaddr))
1248 irel->r_offset -= count;
1249
1250 start = stop;
1251
1252 if (irel->r_type == R_SH_SWITCH16)
1253 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1254 else if (irel->r_type == R_SH_SWITCH8)
1255 voff = bfd_get_8 (abfd, contents + nraddr);
1256 else
1257 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1258 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1259
1260 break;
1261
1262 case R_SH_USES:
1263 start = irel->r_vaddr - sec->vma;
1264 stop = (bfd_vma) ((bfd_signed_vma) start
1265 + (long) irel->r_offset
1266 + 4);
1267 break;
1268 }
1269
1270 if (start > addr
1271 && start < toaddr
1272 && (stop <= addr || stop >= toaddr))
1273 adjust = count;
1274 else if (stop > addr
1275 && stop < toaddr
1276 && (start <= addr || start >= toaddr))
1277 adjust = - count;
1278 else
1279 adjust = 0;
1280
1281 if (adjust != 0)
1282 {
1283 oinsn = insn;
1284 overflow = false;
1285 switch (irel->r_type)
1286 {
1287 default:
1288 abort ();
1289 break;
1290
1291 case R_SH_PCDISP8BY2:
1292 case R_SH_PCRELIMM8BY2:
1293 insn += adjust / 2;
1294 if ((oinsn & 0xff00) != (insn & 0xff00))
1295 overflow = true;
1296 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
1297 break;
1298
1299 case R_SH_PCDISP:
1300 insn += adjust / 2;
1301 if ((oinsn & 0xf000) != (insn & 0xf000))
1302 overflow = true;
1303 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
1304 break;
1305
1306 case R_SH_PCRELIMM8BY4:
1307 BFD_ASSERT (adjust == count || count >= 4);
1308 if (count >= 4)
1309 insn += adjust / 4;
1310 else
1311 {
1312 if ((irel->r_vaddr & 3) == 0)
1313 ++insn;
1314 }
1315 if ((oinsn & 0xff00) != (insn & 0xff00))
1316 overflow = true;
1317 bfd_put_16 (abfd, (bfd_vma) insn, contents + nraddr);
1318 break;
1319
1320 case R_SH_SWITCH8:
1321 voff += adjust;
1322 if (voff < 0 || voff >= 0xff)
1323 overflow = true;
1324 bfd_put_8 (abfd, (bfd_vma) voff, contents + nraddr);
1325 break;
1326
1327 case R_SH_SWITCH16:
1328 voff += adjust;
1329 if (voff < - 0x8000 || voff >= 0x8000)
1330 overflow = true;
1331 bfd_put_signed_16 (abfd, (bfd_vma) voff, contents + nraddr);
1332 break;
1333
1334 case R_SH_SWITCH32:
1335 voff += adjust;
1336 bfd_put_signed_32 (abfd, (bfd_vma) voff, contents + nraddr);
1337 break;
1338
1339 case R_SH_USES:
1340 irel->r_offset += adjust;
1341 break;
1342 }
1343
1344 if (overflow)
1345 {
1346 _bfd_error_handler
1347 /* xgettext: c-format */
1348 (_("%pB: %#" PRIx64 ": fatal: reloc overflow while relaxing"),
1349 abfd, (uint64_t) irel->r_vaddr);
1350 bfd_set_error (bfd_error_bad_value);
1351 return false;
1352 }
1353 }
1354
1355 irel->r_vaddr = nraddr + sec->vma;
1356 }
1357
1358 /* Look through all the other sections. If there contain any IMM32
1359 relocs against internal symbols which we are not going to adjust
1360 below, we may need to adjust the addends. */
1361 for (o = abfd->sections; o != NULL; o = o->next)
1362 {
1363 struct internal_reloc *internal_relocs;
1364 struct internal_reloc *irelscan, *irelscanend;
1365 bfd_byte *ocontents;
1366
1367 if (o == sec
1368 || (o->flags & SEC_HAS_CONTENTS) == 0
1369 || (o->flags & SEC_RELOC) == 0
1370 || o->reloc_count == 0)
1371 continue;
1372
1373 /* We always cache the relocs. Perhaps, if info->keep_memory is
1374 FALSE, we should free them, if we are permitted to, when we
1375 leave sh_coff_relax_section. */
1376 internal_relocs = (_bfd_coff_read_internal_relocs
1377 (abfd, o, true, (bfd_byte *) NULL, false,
1378 (struct internal_reloc *) NULL));
1379 if (internal_relocs == NULL)
1380 return false;
1381
1382 ocontents = NULL;
1383 irelscanend = internal_relocs + o->reloc_count;
1384 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1385 {
1386 struct internal_syment sym;
1387
1388 #ifdef COFF_WITH_PE
1389 if (irelscan->r_type != R_SH_IMM32
1390 && irelscan->r_type != R_SH_IMAGEBASE
1391 && irelscan->r_type != R_SH_IMM32CE)
1392 #else
1393 if (irelscan->r_type != R_SH_IMM32)
1394 #endif
1395 continue;
1396
1397 bfd_coff_swap_sym_in (abfd,
1398 ((bfd_byte *) obj_coff_external_syms (abfd)
1399 + (irelscan->r_symndx
1400 * bfd_coff_symesz (abfd))),
1401 &sym);
1402 if (sym.n_sclass != C_EXT
1403 && sym.n_scnum == sec->target_index
1404 && ((bfd_vma) sym.n_value <= addr
1405 || (bfd_vma) sym.n_value >= toaddr))
1406 {
1407 bfd_vma val;
1408
1409 if (ocontents == NULL)
1410 {
1411 if (coff_section_data (abfd, o)->contents != NULL)
1412 ocontents = coff_section_data (abfd, o)->contents;
1413 else
1414 {
1415 if (!bfd_malloc_and_get_section (abfd, o, &ocontents))
1416 return false;
1417 /* We always cache the section contents.
1418 Perhaps, if info->keep_memory is FALSE, we
1419 should free them, if we are permitted to,
1420 when we leave sh_coff_relax_section. */
1421 coff_section_data (abfd, o)->contents = ocontents;
1422 }
1423 }
1424
1425 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1426 val += sym.n_value;
1427 if (val > addr && val < toaddr)
1428 bfd_put_32 (abfd, val - count,
1429 ocontents + irelscan->r_vaddr - o->vma);
1430 }
1431 }
1432 }
1433
1434 /* Adjusting the internal symbols will not work if something has
1435 already retrieved the generic symbols. It would be possible to
1436 make this work by adjusting the generic symbols at the same time.
1437 However, this case should not arise in normal usage. */
1438 if (obj_symbols (abfd) != NULL
1439 || obj_raw_syments (abfd) != NULL)
1440 {
1441 _bfd_error_handler
1442 (_("%pB: fatal: generic symbols retrieved before relaxing"), abfd);
1443 bfd_set_error (bfd_error_invalid_operation);
1444 return false;
1445 }
1446
1447 /* Adjust all the symbols. */
1448 sym_hash = obj_coff_sym_hashes (abfd);
1449 symesz = bfd_coff_symesz (abfd);
1450 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1451 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1452 while (esym < esymend)
1453 {
1454 struct internal_syment isym;
1455
1456 bfd_coff_swap_sym_in (abfd, esym, &isym);
1457
1458 if (isym.n_scnum == sec->target_index
1459 && (bfd_vma) isym.n_value > addr
1460 && (bfd_vma) isym.n_value < toaddr)
1461 {
1462 isym.n_value -= count;
1463
1464 bfd_coff_swap_sym_out (abfd, &isym, esym);
1465
1466 if (*sym_hash != NULL)
1467 {
1468 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1469 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1470 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1471 && (*sym_hash)->root.u.def.value < toaddr);
1472 (*sym_hash)->root.u.def.value -= count;
1473 }
1474 }
1475
1476 esym += (isym.n_numaux + 1) * symesz;
1477 sym_hash += isym.n_numaux + 1;
1478 }
1479
1480 /* See if we can move the ALIGN reloc forward. We have adjusted
1481 r_vaddr for it already. */
1482 if (irelalign != NULL)
1483 {
1484 bfd_vma alignto, alignaddr;
1485
1486 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1487 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1488 1 << irelalign->r_offset);
1489 if (alignto != alignaddr)
1490 {
1491 /* Tail recursion. */
1492 return sh_relax_delete_bytes (abfd, sec, alignaddr,
1493 (int) (alignto - alignaddr));
1494 }
1495 }
1496
1497 return true;
1498 }
1499 \f
1500 /* This is yet another version of the SH opcode table, used to rapidly
1501 get information about a particular instruction. */
1502
1503 /* The opcode map is represented by an array of these structures. The
1504 array is indexed by the high order four bits in the instruction. */
1505
1506 struct sh_major_opcode
1507 {
1508 /* A pointer to the instruction list. This is an array which
1509 contains all the instructions with this major opcode. */
1510 const struct sh_minor_opcode *minor_opcodes;
1511 /* The number of elements in minor_opcodes. */
1512 unsigned short count;
1513 };
1514
1515 /* This structure holds information for a set of SH opcodes. The
1516 instruction code is anded with the mask value, and the resulting
1517 value is used to search the order opcode list. */
1518
1519 struct sh_minor_opcode
1520 {
1521 /* The sorted opcode list. */
1522 const struct sh_opcode *opcodes;
1523 /* The number of elements in opcodes. */
1524 unsigned short count;
1525 /* The mask value to use when searching the opcode list. */
1526 unsigned short mask;
1527 };
1528
1529 /* This structure holds information for an SH instruction. An array
1530 of these structures is sorted in order by opcode. */
1531
1532 struct sh_opcode
1533 {
1534 /* The code for this instruction, after it has been anded with the
1535 mask value in the sh_major_opcode structure. */
1536 unsigned short opcode;
1537 /* Flags for this instruction. */
1538 unsigned long flags;
1539 };
1540
1541 /* Flag which appear in the sh_opcode structure. */
1542
1543 /* This instruction loads a value from memory. */
1544 #define LOAD (0x1)
1545
1546 /* This instruction stores a value to memory. */
1547 #define STORE (0x2)
1548
1549 /* This instruction is a branch. */
1550 #define BRANCH (0x4)
1551
1552 /* This instruction has a delay slot. */
1553 #define DELAY (0x8)
1554
1555 /* This instruction uses the value in the register in the field at
1556 mask 0x0f00 of the instruction. */
1557 #define USES1 (0x10)
1558 #define USES1_REG(x) ((x & 0x0f00) >> 8)
1559
1560 /* This instruction uses the value in the register in the field at
1561 mask 0x00f0 of the instruction. */
1562 #define USES2 (0x20)
1563 #define USES2_REG(x) ((x & 0x00f0) >> 4)
1564
1565 /* This instruction uses the value in register 0. */
1566 #define USESR0 (0x40)
1567
1568 /* This instruction sets the value in the register in the field at
1569 mask 0x0f00 of the instruction. */
1570 #define SETS1 (0x80)
1571 #define SETS1_REG(x) ((x & 0x0f00) >> 8)
1572
1573 /* This instruction sets the value in the register in the field at
1574 mask 0x00f0 of the instruction. */
1575 #define SETS2 (0x100)
1576 #define SETS2_REG(x) ((x & 0x00f0) >> 4)
1577
1578 /* This instruction sets register 0. */
1579 #define SETSR0 (0x200)
1580
1581 /* This instruction sets a special register. */
1582 #define SETSSP (0x400)
1583
1584 /* This instruction uses a special register. */
1585 #define USESSP (0x800)
1586
1587 /* This instruction uses the floating point register in the field at
1588 mask 0x0f00 of the instruction. */
1589 #define USESF1 (0x1000)
1590 #define USESF1_REG(x) ((x & 0x0f00) >> 8)
1591
1592 /* This instruction uses the floating point register in the field at
1593 mask 0x00f0 of the instruction. */
1594 #define USESF2 (0x2000)
1595 #define USESF2_REG(x) ((x & 0x00f0) >> 4)
1596
1597 /* This instruction uses floating point register 0. */
1598 #define USESF0 (0x4000)
1599
1600 /* This instruction sets the floating point register in the field at
1601 mask 0x0f00 of the instruction. */
1602 #define SETSF1 (0x8000)
1603 #define SETSF1_REG(x) ((x & 0x0f00) >> 8)
1604
1605 #define USESAS (0x10000)
1606 #define USESAS_REG(x) (((((x) >> 8) - 2) & 3) + 2)
1607 #define USESR8 (0x20000)
1608 #define SETSAS (0x40000)
1609 #define SETSAS_REG(x) USESAS_REG (x)
1610
1611 #define MAP(a) a, sizeof a / sizeof a[0]
1612
1613 #ifndef COFF_IMAGE_WITH_PE
1614
1615 /* The opcode maps. */
1616
1617 static const struct sh_opcode sh_opcode00[] =
1618 {
1619 { 0x0008, SETSSP }, /* clrt */
1620 { 0x0009, 0 }, /* nop */
1621 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1622 { 0x0018, SETSSP }, /* sett */
1623 { 0x0019, SETSSP }, /* div0u */
1624 { 0x001b, 0 }, /* sleep */
1625 { 0x0028, SETSSP }, /* clrmac */
1626 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1627 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1628 { 0x0048, SETSSP }, /* clrs */
1629 { 0x0058, SETSSP } /* sets */
1630 };
1631
1632 static const struct sh_opcode sh_opcode01[] =
1633 {
1634 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1635 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
1636 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
1637 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1638 { 0x0029, SETS1 | USESSP }, /* movt rn */
1639 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
1640 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1641 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn / sts dsr,rn */
1642 { 0x0083, LOAD | USES1 }, /* pref @rn */
1643 { 0x007a, SETS1 | USESSP }, /* sts a0,rn */
1644 { 0x008a, SETS1 | USESSP }, /* sts x0,rn */
1645 { 0x009a, SETS1 | USESSP }, /* sts x1,rn */
1646 { 0x00aa, SETS1 | USESSP }, /* sts y0,rn */
1647 { 0x00ba, SETS1 | USESSP } /* sts y1,rn */
1648 };
1649
1650 static const struct sh_opcode sh_opcode02[] =
1651 {
1652 { 0x0002, SETS1 | USESSP }, /* stc <special_reg>,rn */
1653 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1654 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1655 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1656 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1657 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1658 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1659 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1660 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1661 };
1662
1663 static const struct sh_minor_opcode sh_opcode0[] =
1664 {
1665 { MAP (sh_opcode00), 0xffff },
1666 { MAP (sh_opcode01), 0xf0ff },
1667 { MAP (sh_opcode02), 0xf00f }
1668 };
1669
1670 static const struct sh_opcode sh_opcode10[] =
1671 {
1672 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1673 };
1674
1675 static const struct sh_minor_opcode sh_opcode1[] =
1676 {
1677 { MAP (sh_opcode10), 0xf000 }
1678 };
1679
1680 static const struct sh_opcode sh_opcode20[] =
1681 {
1682 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1683 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1684 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1685 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1686 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1687 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1688 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1689 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1690 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1691 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1692 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1693 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1694 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1695 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1696 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1697 };
1698
1699 static const struct sh_minor_opcode sh_opcode2[] =
1700 {
1701 { MAP (sh_opcode20), 0xf00f }
1702 };
1703
1704 static const struct sh_opcode sh_opcode30[] =
1705 {
1706 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1707 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1708 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1709 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1710 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1711 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1712 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1713 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1714 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1715 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1716 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1717 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1718 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1719 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1720 };
1721
1722 static const struct sh_minor_opcode sh_opcode3[] =
1723 {
1724 { MAP (sh_opcode30), 0xf00f }
1725 };
1726
1727 static const struct sh_opcode sh_opcode40[] =
1728 {
1729 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1730 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1731 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
1732 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1733 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1734 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
1735 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1736 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1737 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1738 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
1739 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1740 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1741 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
1742 { 0x4014, SETSSP | USES1 }, /* setrc rm */
1743 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1744 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
1745 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1746 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1747 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1748 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
1749 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1750 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1751 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
1752 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1753 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1754 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
1755 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1756 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1757 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1758 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
1759 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1760 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1761 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1762 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr / dsr,@-rn */
1763 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr / dsr */
1764 { 0x406a, SETSSP | USES1 }, /* lds rm,fpscr / lds rm,dsr */
1765 { 0x4072, STORE | SETS1 | USES1 | USESSP }, /* sts.l a0,@-rn */
1766 { 0x4076, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,a0 */
1767 { 0x407a, SETSSP | USES1 }, /* lds.l rm,a0 */
1768 { 0x4082, STORE | SETS1 | USES1 | USESSP }, /* sts.l x0,@-rn */
1769 { 0x4086, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x0 */
1770 { 0x408a, SETSSP | USES1 }, /* lds.l rm,x0 */
1771 { 0x4092, STORE | SETS1 | USES1 | USESSP }, /* sts.l x1,@-rn */
1772 { 0x4096, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,x1 */
1773 { 0x409a, SETSSP | USES1 }, /* lds.l rm,x1 */
1774 { 0x40a2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y0,@-rn */
1775 { 0x40a6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y0 */
1776 { 0x40aa, SETSSP | USES1 }, /* lds.l rm,y0 */
1777 { 0x40b2, STORE | SETS1 | USES1 | USESSP }, /* sts.l y1,@-rn */
1778 { 0x40b6, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,y1 */
1779 { 0x40ba, SETSSP | USES1 } /* lds.l rm,y1 */
1780 };
1781
1782 static const struct sh_opcode sh_opcode41[] =
1783 {
1784 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l <special_reg>,@-rn */
1785 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,<special_reg> */
1786 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1787 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1788 { 0x400e, SETSSP | USES1 }, /* ldc rm,<special_reg> */
1789 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1790 };
1791
1792 static const struct sh_minor_opcode sh_opcode4[] =
1793 {
1794 { MAP (sh_opcode40), 0xf0ff },
1795 { MAP (sh_opcode41), 0xf00f }
1796 };
1797
1798 static const struct sh_opcode sh_opcode50[] =
1799 {
1800 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1801 };
1802
1803 static const struct sh_minor_opcode sh_opcode5[] =
1804 {
1805 { MAP (sh_opcode50), 0xf000 }
1806 };
1807
1808 static const struct sh_opcode sh_opcode60[] =
1809 {
1810 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1811 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1812 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1813 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1814 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1815 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1816 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1817 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1818 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1819 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1820 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1821 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1822 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1823 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1824 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1825 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1826 };
1827
1828 static const struct sh_minor_opcode sh_opcode6[] =
1829 {
1830 { MAP (sh_opcode60), 0xf00f }
1831 };
1832
1833 static const struct sh_opcode sh_opcode70[] =
1834 {
1835 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1836 };
1837
1838 static const struct sh_minor_opcode sh_opcode7[] =
1839 {
1840 { MAP (sh_opcode70), 0xf000 }
1841 };
1842
1843 static const struct sh_opcode sh_opcode80[] =
1844 {
1845 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1846 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
1847 { 0x8200, SETSSP }, /* setrc #imm */
1848 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1849 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1850 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1851 { 0x8900, BRANCH | USESSP }, /* bt label */
1852 { 0x8b00, BRANCH | USESSP }, /* bf label */
1853 { 0x8c00, SETSSP }, /* ldrs @(disp,pc) */
1854 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
1855 { 0x8e00, SETSSP }, /* ldre @(disp,pc) */
1856 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1857 };
1858
1859 static const struct sh_minor_opcode sh_opcode8[] =
1860 {
1861 { MAP (sh_opcode80), 0xff00 }
1862 };
1863
1864 static const struct sh_opcode sh_opcode90[] =
1865 {
1866 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1867 };
1868
1869 static const struct sh_minor_opcode sh_opcode9[] =
1870 {
1871 { MAP (sh_opcode90), 0xf000 }
1872 };
1873
1874 static const struct sh_opcode sh_opcodea0[] =
1875 {
1876 { 0xa000, BRANCH | DELAY } /* bra label */
1877 };
1878
1879 static const struct sh_minor_opcode sh_opcodea[] =
1880 {
1881 { MAP (sh_opcodea0), 0xf000 }
1882 };
1883
1884 static const struct sh_opcode sh_opcodeb0[] =
1885 {
1886 { 0xb000, BRANCH | DELAY } /* bsr label */
1887 };
1888
1889 static const struct sh_minor_opcode sh_opcodeb[] =
1890 {
1891 { MAP (sh_opcodeb0), 0xf000 }
1892 };
1893
1894 static const struct sh_opcode sh_opcodec0[] =
1895 {
1896 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1897 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1898 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1899 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
1900 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
1901 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
1902 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
1903 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
1904 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
1905 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
1906 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
1907 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
1908 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
1909 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1910 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1911 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1912 };
1913
1914 static const struct sh_minor_opcode sh_opcodec[] =
1915 {
1916 { MAP (sh_opcodec0), 0xff00 }
1917 };
1918
1919 static const struct sh_opcode sh_opcoded0[] =
1920 {
1921 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
1922 };
1923
1924 static const struct sh_minor_opcode sh_opcoded[] =
1925 {
1926 { MAP (sh_opcoded0), 0xf000 }
1927 };
1928
1929 static const struct sh_opcode sh_opcodee0[] =
1930 {
1931 { 0xe000, SETS1 } /* mov #imm,rn */
1932 };
1933
1934 static const struct sh_minor_opcode sh_opcodee[] =
1935 {
1936 { MAP (sh_opcodee0), 0xf000 }
1937 };
1938
1939 static const struct sh_opcode sh_opcodef0[] =
1940 {
1941 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
1942 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
1943 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
1944 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
1945 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
1946 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
1947 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
1948 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
1949 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
1950 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
1951 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
1952 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
1953 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
1954 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
1955 };
1956
1957 static const struct sh_opcode sh_opcodef1[] =
1958 {
1959 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
1960 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
1961 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
1962 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
1963 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
1964 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
1965 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
1966 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
1967 { 0xf08d, SETSF1 }, /* fldi0 fn */
1968 { 0xf09d, SETSF1 } /* fldi1 fn */
1969 };
1970
1971 static const struct sh_minor_opcode sh_opcodef[] =
1972 {
1973 { MAP (sh_opcodef0), 0xf00f },
1974 { MAP (sh_opcodef1), 0xf0ff }
1975 };
1976
1977 static struct sh_major_opcode sh_opcodes[] =
1978 {
1979 { MAP (sh_opcode0) },
1980 { MAP (sh_opcode1) },
1981 { MAP (sh_opcode2) },
1982 { MAP (sh_opcode3) },
1983 { MAP (sh_opcode4) },
1984 { MAP (sh_opcode5) },
1985 { MAP (sh_opcode6) },
1986 { MAP (sh_opcode7) },
1987 { MAP (sh_opcode8) },
1988 { MAP (sh_opcode9) },
1989 { MAP (sh_opcodea) },
1990 { MAP (sh_opcodeb) },
1991 { MAP (sh_opcodec) },
1992 { MAP (sh_opcoded) },
1993 { MAP (sh_opcodee) },
1994 { MAP (sh_opcodef) }
1995 };
1996
1997 /* The double data transfer / parallel processing insns are not
1998 described here. This will cause sh_align_load_span to leave them alone. */
1999
2000 static const struct sh_opcode sh_dsp_opcodef0[] =
2001 {
2002 { 0xf400, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @-as,ds */
2003 { 0xf401, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@-as */
2004 { 0xf404, USESAS | LOAD | SETSSP }, /* movs.x @as,ds */
2005 { 0xf405, USESAS | STORE | USESSP }, /* movs.x ds,@as */
2006 { 0xf408, USESAS | SETSAS | LOAD | SETSSP }, /* movs.x @as+,ds */
2007 { 0xf409, USESAS | SETSAS | STORE | USESSP }, /* movs.x ds,@as+ */
2008 { 0xf40c, USESAS | SETSAS | LOAD | SETSSP | USESR8 }, /* movs.x @as+r8,ds */
2009 { 0xf40d, USESAS | SETSAS | STORE | USESSP | USESR8 } /* movs.x ds,@as+r8 */
2010 };
2011
2012 static const struct sh_minor_opcode sh_dsp_opcodef[] =
2013 {
2014 { MAP (sh_dsp_opcodef0), 0xfc0d }
2015 };
2016
2017 /* Given an instruction, return a pointer to the corresponding
2018 sh_opcode structure. Return NULL if the instruction is not
2019 recognized. */
2020
2021 static const struct sh_opcode *
2022 sh_insn_info (unsigned int insn)
2023 {
2024 const struct sh_major_opcode *maj;
2025 const struct sh_minor_opcode *min, *minend;
2026
2027 maj = &sh_opcodes[(insn & 0xf000) >> 12];
2028 min = maj->minor_opcodes;
2029 minend = min + maj->count;
2030 for (; min < minend; min++)
2031 {
2032 unsigned int l;
2033 const struct sh_opcode *op, *opend;
2034
2035 l = insn & min->mask;
2036 op = min->opcodes;
2037 opend = op + min->count;
2038
2039 /* Since the opcodes tables are sorted, we could use a binary
2040 search here if the count were above some cutoff value. */
2041 for (; op < opend; op++)
2042 if (op->opcode == l)
2043 return op;
2044 }
2045
2046 return NULL;
2047 }
2048
2049 /* See whether an instruction uses a general purpose register. */
2050
2051 static bool
2052 sh_insn_uses_reg (unsigned int insn,
2053 const struct sh_opcode *op,
2054 unsigned int reg)
2055 {
2056 unsigned int f;
2057
2058 f = op->flags;
2059
2060 if ((f & USES1) != 0
2061 && USES1_REG (insn) == reg)
2062 return true;
2063 if ((f & USES2) != 0
2064 && USES2_REG (insn) == reg)
2065 return true;
2066 if ((f & USESR0) != 0
2067 && reg == 0)
2068 return true;
2069 if ((f & USESAS) && reg == USESAS_REG (insn))
2070 return true;
2071 if ((f & USESR8) && reg == 8)
2072 return true;
2073
2074 return false;
2075 }
2076
2077 /* See whether an instruction sets a general purpose register. */
2078
2079 static bool
2080 sh_insn_sets_reg (unsigned int insn,
2081 const struct sh_opcode *op,
2082 unsigned int reg)
2083 {
2084 unsigned int f;
2085
2086 f = op->flags;
2087
2088 if ((f & SETS1) != 0
2089 && SETS1_REG (insn) == reg)
2090 return true;
2091 if ((f & SETS2) != 0
2092 && SETS2_REG (insn) == reg)
2093 return true;
2094 if ((f & SETSR0) != 0
2095 && reg == 0)
2096 return true;
2097 if ((f & SETSAS) && reg == SETSAS_REG (insn))
2098 return true;
2099
2100 return false;
2101 }
2102
2103 /* See whether an instruction uses or sets a general purpose register */
2104
2105 static bool
2106 sh_insn_uses_or_sets_reg (unsigned int insn,
2107 const struct sh_opcode *op,
2108 unsigned int reg)
2109 {
2110 if (sh_insn_uses_reg (insn, op, reg))
2111 return true;
2112
2113 return sh_insn_sets_reg (insn, op, reg);
2114 }
2115
2116 /* See whether an instruction uses a floating point register. */
2117
2118 static bool
2119 sh_insn_uses_freg (unsigned int insn,
2120 const struct sh_opcode *op,
2121 unsigned int freg)
2122 {
2123 unsigned int f;
2124
2125 f = op->flags;
2126
2127 /* We can't tell if this is a double-precision insn, so just play safe
2128 and assume that it might be. So not only have we test FREG against
2129 itself, but also even FREG against FREG+1 - if the using insn uses
2130 just the low part of a double precision value - but also an odd
2131 FREG against FREG-1 - if the setting insn sets just the low part
2132 of a double precision value.
2133 So what this all boils down to is that we have to ignore the lowest
2134 bit of the register number. */
2135
2136 if ((f & USESF1) != 0
2137 && (USESF1_REG (insn) & 0xe) == (freg & 0xe))
2138 return true;
2139 if ((f & USESF2) != 0
2140 && (USESF2_REG (insn) & 0xe) == (freg & 0xe))
2141 return true;
2142 if ((f & USESF0) != 0
2143 && freg == 0)
2144 return true;
2145
2146 return false;
2147 }
2148
2149 /* See whether an instruction sets a floating point register. */
2150
2151 static bool
2152 sh_insn_sets_freg (unsigned int insn,
2153 const struct sh_opcode *op,
2154 unsigned int freg)
2155 {
2156 unsigned int f;
2157
2158 f = op->flags;
2159
2160 /* We can't tell if this is a double-precision insn, so just play safe
2161 and assume that it might be. So not only have we test FREG against
2162 itself, but also even FREG against FREG+1 - if the using insn uses
2163 just the low part of a double precision value - but also an odd
2164 FREG against FREG-1 - if the setting insn sets just the low part
2165 of a double precision value.
2166 So what this all boils down to is that we have to ignore the lowest
2167 bit of the register number. */
2168
2169 if ((f & SETSF1) != 0
2170 && (SETSF1_REG (insn) & 0xe) == (freg & 0xe))
2171 return true;
2172
2173 return false;
2174 }
2175
2176 /* See whether an instruction uses or sets a floating point register */
2177
2178 static bool
2179 sh_insn_uses_or_sets_freg (unsigned int insn,
2180 const struct sh_opcode *op,
2181 unsigned int reg)
2182 {
2183 if (sh_insn_uses_freg (insn, op, reg))
2184 return true;
2185
2186 return sh_insn_sets_freg (insn, op, reg);
2187 }
2188
2189 /* See whether instructions I1 and I2 conflict, assuming I1 comes
2190 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
2191 This should return TRUE if there is a conflict, or FALSE if the
2192 instructions can be swapped safely. */
2193
2194 static bool
2195 sh_insns_conflict (unsigned int i1,
2196 const struct sh_opcode *op1,
2197 unsigned int i2,
2198 const struct sh_opcode *op2)
2199 {
2200 unsigned int f1, f2;
2201
2202 f1 = op1->flags;
2203 f2 = op2->flags;
2204
2205 /* Load of fpscr conflicts with floating point operations.
2206 FIXME: shouldn't test raw opcodes here. */
2207 if (((i1 & 0xf0ff) == 0x4066 && (i2 & 0xf000) == 0xf000)
2208 || ((i2 & 0xf0ff) == 0x4066 && (i1 & 0xf000) == 0xf000))
2209 return true;
2210
2211 if ((f1 & (BRANCH | DELAY)) != 0
2212 || (f2 & (BRANCH | DELAY)) != 0)
2213 return true;
2214
2215 if (((f1 | f2) & SETSSP)
2216 && (f1 & (SETSSP | USESSP))
2217 && (f2 & (SETSSP | USESSP)))
2218 return true;
2219
2220 if ((f1 & SETS1) != 0
2221 && sh_insn_uses_or_sets_reg (i2, op2, SETS1_REG (i1)))
2222 return true;
2223 if ((f1 & SETS2) != 0
2224 && sh_insn_uses_or_sets_reg (i2, op2, SETS2_REG (i1)))
2225 return true;
2226 if ((f1 & SETSR0) != 0
2227 && sh_insn_uses_or_sets_reg (i2, op2, 0))
2228 return true;
2229 if ((f1 & SETSAS)
2230 && sh_insn_uses_or_sets_reg (i2, op2, SETSAS_REG (i1)))
2231 return true;
2232 if ((f1 & SETSF1) != 0
2233 && sh_insn_uses_or_sets_freg (i2, op2, SETSF1_REG (i1)))
2234 return true;
2235
2236 if ((f2 & SETS1) != 0
2237 && sh_insn_uses_or_sets_reg (i1, op1, SETS1_REG (i2)))
2238 return true;
2239 if ((f2 & SETS2) != 0
2240 && sh_insn_uses_or_sets_reg (i1, op1, SETS2_REG (i2)))
2241 return true;
2242 if ((f2 & SETSR0) != 0
2243 && sh_insn_uses_or_sets_reg (i1, op1, 0))
2244 return true;
2245 if ((f2 & SETSAS)
2246 && sh_insn_uses_or_sets_reg (i1, op1, SETSAS_REG (i2)))
2247 return true;
2248 if ((f2 & SETSF1) != 0
2249 && sh_insn_uses_or_sets_freg (i1, op1, SETSF1_REG (i2)))
2250 return true;
2251
2252 /* The instructions do not conflict. */
2253 return false;
2254 }
2255
2256 /* I1 is a load instruction, and I2 is some other instruction. Return
2257 TRUE if I1 loads a register which I2 uses. */
2258
2259 static bool
2260 sh_load_use (unsigned int i1,
2261 const struct sh_opcode *op1,
2262 unsigned int i2,
2263 const struct sh_opcode *op2)
2264 {
2265 unsigned int f1;
2266
2267 f1 = op1->flags;
2268
2269 if ((f1 & LOAD) == 0)
2270 return false;
2271
2272 /* If both SETS1 and SETSSP are set, that means a load to a special
2273 register using postincrement addressing mode, which we don't care
2274 about here. */
2275 if ((f1 & SETS1) != 0
2276 && (f1 & SETSSP) == 0
2277 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
2278 return true;
2279
2280 if ((f1 & SETSR0) != 0
2281 && sh_insn_uses_reg (i2, op2, 0))
2282 return true;
2283
2284 if ((f1 & SETSF1) != 0
2285 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
2286 return true;
2287
2288 return false;
2289 }
2290
2291 /* Try to align loads and stores within a span of memory. This is
2292 called by both the ELF and the COFF sh targets. ABFD and SEC are
2293 the BFD and section we are examining. CONTENTS is the contents of
2294 the section. SWAP is the routine to call to swap two instructions.
2295 RELOCS is a pointer to the internal relocation information, to be
2296 passed to SWAP. PLABEL is a pointer to the current label in a
2297 sorted list of labels; LABEL_END is the end of the list. START and
2298 STOP are the range of memory to examine. If a swap is made,
2299 *PSWAPPED is set to TRUE. */
2300
2301 #ifdef COFF_WITH_PE
2302 static
2303 #endif
2304 bool
2305 _bfd_sh_align_load_span (bfd *abfd,
2306 asection *sec,
2307 bfd_byte *contents,
2308 bool (*swap) (bfd *, asection *, void *, bfd_byte *, bfd_vma),
2309 void * relocs,
2310 bfd_vma **plabel,
2311 bfd_vma *label_end,
2312 bfd_vma start,
2313 bfd_vma stop,
2314 bool *pswapped)
2315 {
2316 int dsp = (abfd->arch_info->mach == bfd_mach_sh_dsp
2317 || abfd->arch_info->mach == bfd_mach_sh3_dsp);
2318 bfd_vma i;
2319
2320 /* The SH4 has a Harvard architecture, hence aligning loads is not
2321 desirable. In fact, it is counter-productive, since it interferes
2322 with the schedules generated by the compiler. */
2323 if (abfd->arch_info->mach == bfd_mach_sh4)
2324 return true;
2325
2326 /* If we are linking sh[3]-dsp code, swap the FPU instructions for DSP
2327 instructions. */
2328 if (dsp)
2329 {
2330 sh_opcodes[0xf].minor_opcodes = sh_dsp_opcodef;
2331 sh_opcodes[0xf].count = sizeof sh_dsp_opcodef / sizeof sh_dsp_opcodef [0];
2332 }
2333
2334 /* Instructions should be aligned on 2 byte boundaries. */
2335 if ((start & 1) == 1)
2336 ++start;
2337
2338 /* Now look through the unaligned addresses. */
2339 i = start;
2340 if ((i & 2) == 0)
2341 i += 2;
2342 for (; i < stop; i += 4)
2343 {
2344 unsigned int insn;
2345 const struct sh_opcode *op;
2346 unsigned int prev_insn = 0;
2347 const struct sh_opcode *prev_op = NULL;
2348
2349 insn = bfd_get_16 (abfd, contents + i);
2350 op = sh_insn_info (insn);
2351 if (op == NULL
2352 || (op->flags & (LOAD | STORE)) == 0)
2353 continue;
2354
2355 /* This is a load or store which is not on a four byte boundary. */
2356
2357 while (*plabel < label_end && **plabel < i)
2358 ++*plabel;
2359
2360 if (i > start)
2361 {
2362 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2363 /* If INSN is the field b of a parallel processing insn, it is not
2364 a load / store after all. Note that the test here might mistake
2365 the field_b of a pcopy insn for the starting code of a parallel
2366 processing insn; this might miss a swapping opportunity, but at
2367 least we're on the safe side. */
2368 if (dsp && (prev_insn & 0xfc00) == 0xf800)
2369 continue;
2370
2371 /* Check if prev_insn is actually the field b of a parallel
2372 processing insn. Again, this can give a spurious match
2373 after a pcopy. */
2374 if (dsp && i - 2 > start)
2375 {
2376 unsigned pprev_insn = bfd_get_16 (abfd, contents + i - 4);
2377
2378 if ((pprev_insn & 0xfc00) == 0xf800)
2379 prev_op = NULL;
2380 else
2381 prev_op = sh_insn_info (prev_insn);
2382 }
2383 else
2384 prev_op = sh_insn_info (prev_insn);
2385
2386 /* If the load/store instruction is in a delay slot, we
2387 can't swap. */
2388 if (prev_op == NULL
2389 || (prev_op->flags & DELAY) != 0)
2390 continue;
2391 }
2392 if (i > start
2393 && (*plabel >= label_end || **plabel != i)
2394 && prev_op != NULL
2395 && (prev_op->flags & (LOAD | STORE)) == 0
2396 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2397 {
2398 bool ok;
2399
2400 /* The load/store instruction does not have a label, and
2401 there is a previous instruction; PREV_INSN is not
2402 itself a load/store instruction, and PREV_INSN and
2403 INSN do not conflict. */
2404
2405 ok = true;
2406
2407 if (i >= start + 4)
2408 {
2409 unsigned int prev2_insn;
2410 const struct sh_opcode *prev2_op;
2411
2412 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2413 prev2_op = sh_insn_info (prev2_insn);
2414
2415 /* If the instruction before PREV_INSN has a delay
2416 slot--that is, PREV_INSN is in a delay slot--we
2417 can not swap. */
2418 if (prev2_op == NULL
2419 || (prev2_op->flags & DELAY) != 0)
2420 ok = false;
2421
2422 /* If the instruction before PREV_INSN is a load,
2423 and it sets a register which INSN uses, then
2424 putting INSN immediately after PREV_INSN will
2425 cause a pipeline bubble, so there is no point to
2426 making the swap. */
2427 if (ok
2428 && (prev2_op->flags & LOAD) != 0
2429 && sh_load_use (prev2_insn, prev2_op, insn, op))
2430 ok = false;
2431 }
2432
2433 if (ok)
2434 {
2435 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
2436 return false;
2437 *pswapped = true;
2438 continue;
2439 }
2440 }
2441
2442 while (*plabel < label_end && **plabel < i + 2)
2443 ++*plabel;
2444
2445 if (i + 2 < stop
2446 && (*plabel >= label_end || **plabel != i + 2))
2447 {
2448 unsigned int next_insn;
2449 const struct sh_opcode *next_op;
2450
2451 /* There is an instruction after the load/store
2452 instruction, and it does not have a label. */
2453 next_insn = bfd_get_16 (abfd, contents + i + 2);
2454 next_op = sh_insn_info (next_insn);
2455 if (next_op != NULL
2456 && (next_op->flags & (LOAD | STORE)) == 0
2457 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2458 {
2459 bool ok;
2460
2461 /* NEXT_INSN is not itself a load/store instruction,
2462 and it does not conflict with INSN. */
2463
2464 ok = true;
2465
2466 /* If PREV_INSN is a load, and it sets a register
2467 which NEXT_INSN uses, then putting NEXT_INSN
2468 immediately after PREV_INSN will cause a pipeline
2469 bubble, so there is no reason to make this swap. */
2470 if (prev_op != NULL
2471 && (prev_op->flags & LOAD) != 0
2472 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
2473 ok = false;
2474
2475 /* If INSN is a load, and it sets a register which
2476 the insn after NEXT_INSN uses, then doing the
2477 swap will cause a pipeline bubble, so there is no
2478 reason to make the swap. However, if the insn
2479 after NEXT_INSN is itself a load or store
2480 instruction, then it is misaligned, so
2481 optimistically hope that it will be swapped
2482 itself, and just live with the pipeline bubble if
2483 it isn't. */
2484 if (ok
2485 && i + 4 < stop
2486 && (op->flags & LOAD) != 0)
2487 {
2488 unsigned int next2_insn;
2489 const struct sh_opcode *next2_op;
2490
2491 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2492 next2_op = sh_insn_info (next2_insn);
2493 if (next2_op == NULL
2494 || ((next2_op->flags & (LOAD | STORE)) == 0
2495 && sh_load_use (insn, op, next2_insn, next2_op)))
2496 ok = false;
2497 }
2498
2499 if (ok)
2500 {
2501 if (! (*swap) (abfd, sec, relocs, contents, i))
2502 return false;
2503 *pswapped = true;
2504 continue;
2505 }
2506 }
2507 }
2508 }
2509
2510 return true;
2511 }
2512 #endif /* not COFF_IMAGE_WITH_PE */
2513
2514 /* Swap two SH instructions. */
2515
2516 static bool
2517 sh_swap_insns (bfd * abfd,
2518 asection * sec,
2519 void * relocs,
2520 bfd_byte * contents,
2521 bfd_vma addr)
2522 {
2523 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2524 unsigned short i1, i2;
2525 struct internal_reloc *irel, *irelend;
2526
2527 /* Swap the instructions themselves. */
2528 i1 = bfd_get_16 (abfd, contents + addr);
2529 i2 = bfd_get_16 (abfd, contents + addr + 2);
2530 bfd_put_16 (abfd, (bfd_vma) i2, contents + addr);
2531 bfd_put_16 (abfd, (bfd_vma) i1, contents + addr + 2);
2532
2533 /* Adjust all reloc addresses. */
2534 irelend = internal_relocs + sec->reloc_count;
2535 for (irel = internal_relocs; irel < irelend; irel++)
2536 {
2537 int type, add;
2538
2539 /* There are a few special types of relocs that we don't want to
2540 adjust. These relocs do not apply to the instruction itself,
2541 but are only associated with the address. */
2542 type = irel->r_type;
2543 if (type == R_SH_ALIGN
2544 || type == R_SH_CODE
2545 || type == R_SH_DATA
2546 || type == R_SH_LABEL)
2547 continue;
2548
2549 /* If an R_SH_USES reloc points to one of the addresses being
2550 swapped, we must adjust it. It would be incorrect to do this
2551 for a jump, though, since we want to execute both
2552 instructions after the jump. (We have avoided swapping
2553 around a label, so the jump will not wind up executing an
2554 instruction it shouldn't). */
2555 if (type == R_SH_USES)
2556 {
2557 bfd_vma off;
2558
2559 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2560 if (off == addr)
2561 irel->r_offset += 2;
2562 else if (off == addr + 2)
2563 irel->r_offset -= 2;
2564 }
2565
2566 if (irel->r_vaddr - sec->vma == addr)
2567 {
2568 irel->r_vaddr += 2;
2569 add = -2;
2570 }
2571 else if (irel->r_vaddr - sec->vma == addr + 2)
2572 {
2573 irel->r_vaddr -= 2;
2574 add = 2;
2575 }
2576 else
2577 add = 0;
2578
2579 if (add != 0)
2580 {
2581 bfd_byte *loc;
2582 unsigned short insn, oinsn;
2583 bool overflow;
2584
2585 loc = contents + irel->r_vaddr - sec->vma;
2586 overflow = false;
2587 switch (type)
2588 {
2589 default:
2590 break;
2591
2592 case R_SH_PCDISP8BY2:
2593 case R_SH_PCRELIMM8BY2:
2594 insn = bfd_get_16 (abfd, loc);
2595 oinsn = insn;
2596 insn += add / 2;
2597 if ((oinsn & 0xff00) != (insn & 0xff00))
2598 overflow = true;
2599 bfd_put_16 (abfd, (bfd_vma) insn, loc);
2600 break;
2601
2602 case R_SH_PCDISP:
2603 insn = bfd_get_16 (abfd, loc);
2604 oinsn = insn;
2605 insn += add / 2;
2606 if ((oinsn & 0xf000) != (insn & 0xf000))
2607 overflow = true;
2608 bfd_put_16 (abfd, (bfd_vma) insn, loc);
2609 break;
2610
2611 case R_SH_PCRELIMM8BY4:
2612 /* This reloc ignores the least significant 3 bits of
2613 the program counter before adding in the offset.
2614 This means that if ADDR is at an even address, the
2615 swap will not affect the offset. If ADDR is an at an
2616 odd address, then the instruction will be crossing a
2617 four byte boundary, and must be adjusted. */
2618 if ((addr & 3) != 0)
2619 {
2620 insn = bfd_get_16 (abfd, loc);
2621 oinsn = insn;
2622 insn += add / 2;
2623 if ((oinsn & 0xff00) != (insn & 0xff00))
2624 overflow = true;
2625 bfd_put_16 (abfd, (bfd_vma) insn, loc);
2626 }
2627
2628 break;
2629 }
2630
2631 if (overflow)
2632 {
2633 _bfd_error_handler
2634 /* xgettext: c-format */
2635 (_("%pB: %#" PRIx64 ": fatal: reloc overflow while relaxing"),
2636 abfd, (uint64_t) irel->r_vaddr);
2637 bfd_set_error (bfd_error_bad_value);
2638 return false;
2639 }
2640 }
2641 }
2642
2643 return true;
2644 }
2645
2646 /* Look for loads and stores which we can align to four byte
2647 boundaries. See the longer comment above sh_relax_section for why
2648 this is desirable. This sets *PSWAPPED if some instruction was
2649 swapped. */
2650
2651 static bool
2652 sh_align_loads (bfd *abfd,
2653 asection *sec,
2654 struct internal_reloc *internal_relocs,
2655 bfd_byte *contents,
2656 bool *pswapped)
2657 {
2658 struct internal_reloc *irel, *irelend;
2659 bfd_vma *labels = NULL;
2660 bfd_vma *label, *label_end;
2661 bfd_size_type amt;
2662
2663 *pswapped = false;
2664
2665 irelend = internal_relocs + sec->reloc_count;
2666
2667 /* Get all the addresses with labels on them. */
2668 amt = (bfd_size_type) sec->reloc_count * sizeof (bfd_vma);
2669 labels = (bfd_vma *) bfd_malloc (amt);
2670 if (labels == NULL)
2671 goto error_return;
2672 label_end = labels;
2673 for (irel = internal_relocs; irel < irelend; irel++)
2674 {
2675 if (irel->r_type == R_SH_LABEL)
2676 {
2677 *label_end = irel->r_vaddr - sec->vma;
2678 ++label_end;
2679 }
2680 }
2681
2682 /* Note that the assembler currently always outputs relocs in
2683 address order. If that ever changes, this code will need to sort
2684 the label values and the relocs. */
2685
2686 label = labels;
2687
2688 for (irel = internal_relocs; irel < irelend; irel++)
2689 {
2690 bfd_vma start, stop;
2691
2692 if (irel->r_type != R_SH_CODE)
2693 continue;
2694
2695 start = irel->r_vaddr - sec->vma;
2696
2697 for (irel++; irel < irelend; irel++)
2698 if (irel->r_type == R_SH_DATA)
2699 break;
2700 if (irel < irelend)
2701 stop = irel->r_vaddr - sec->vma;
2702 else
2703 stop = sec->size;
2704
2705 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2706 internal_relocs, &label,
2707 label_end, start, stop, pswapped))
2708 goto error_return;
2709 }
2710
2711 free (labels);
2712
2713 return true;
2714
2715 error_return:
2716 free (labels);
2717 return false;
2718 }
2719 \f
2720 /* This is a modification of _bfd_coff_generic_relocate_section, which
2721 will handle SH relaxing. */
2722
2723 static bool
2724 sh_relocate_section (bfd *output_bfd ATTRIBUTE_UNUSED,
2725 struct bfd_link_info *info,
2726 bfd *input_bfd,
2727 asection *input_section,
2728 bfd_byte *contents,
2729 struct internal_reloc *relocs,
2730 struct internal_syment *syms,
2731 asection **sections)
2732 {
2733 struct internal_reloc *rel;
2734 struct internal_reloc *relend;
2735
2736 rel = relocs;
2737 relend = rel + input_section->reloc_count;
2738 for (; rel < relend; rel++)
2739 {
2740 long symndx;
2741 struct coff_link_hash_entry *h;
2742 struct internal_syment *sym;
2743 bfd_vma addend;
2744 bfd_vma val;
2745 reloc_howto_type *howto;
2746 bfd_reloc_status_type rstat;
2747
2748 /* Almost all relocs have to do with relaxing. If any work must
2749 be done for them, it has been done in sh_relax_section. */
2750 if (rel->r_type != R_SH_IMM32
2751 #ifdef COFF_WITH_PE
2752 && rel->r_type != R_SH_IMM32CE
2753 && rel->r_type != R_SH_IMAGEBASE
2754 #endif
2755 && rel->r_type != R_SH_PCDISP)
2756 continue;
2757
2758 symndx = rel->r_symndx;
2759
2760 if (symndx == -1)
2761 {
2762 h = NULL;
2763 sym = NULL;
2764 }
2765 else
2766 {
2767 if (symndx < 0
2768 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2769 {
2770 _bfd_error_handler
2771 /* xgettext: c-format */
2772 (_("%pB: illegal symbol index %ld in relocs"),
2773 input_bfd, symndx);
2774 bfd_set_error (bfd_error_bad_value);
2775 return false;
2776 }
2777 h = obj_coff_sym_hashes (input_bfd)[symndx];
2778 sym = syms + symndx;
2779 }
2780
2781 if (sym != NULL && sym->n_scnum != 0)
2782 addend = - sym->n_value;
2783 else
2784 addend = 0;
2785
2786 if (rel->r_type == R_SH_PCDISP)
2787 addend -= 4;
2788
2789 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2790 howto = NULL;
2791 else
2792 howto = &sh_coff_howtos[rel->r_type];
2793
2794 if (howto == NULL)
2795 {
2796 bfd_set_error (bfd_error_bad_value);
2797 return false;
2798 }
2799
2800 #ifdef COFF_WITH_PE
2801 if (rel->r_type == R_SH_IMAGEBASE)
2802 addend -= pe_data (input_section->output_section->owner)->pe_opthdr.ImageBase;
2803 #endif
2804
2805 val = 0;
2806
2807 if (h == NULL)
2808 {
2809 asection *sec;
2810
2811 /* There is nothing to do for an internal PCDISP reloc. */
2812 if (rel->r_type == R_SH_PCDISP)
2813 continue;
2814
2815 if (symndx == -1)
2816 {
2817 sec = bfd_abs_section_ptr;
2818 val = 0;
2819 }
2820 else
2821 {
2822 sec = sections[symndx];
2823 val = (sec->output_section->vma
2824 + sec->output_offset
2825 + sym->n_value
2826 - sec->vma);
2827 }
2828 }
2829 else
2830 {
2831 if (h->root.type == bfd_link_hash_defined
2832 || h->root.type == bfd_link_hash_defweak)
2833 {
2834 asection *sec;
2835
2836 sec = h->root.u.def.section;
2837 val = (h->root.u.def.value
2838 + sec->output_section->vma
2839 + sec->output_offset);
2840 }
2841 else if (! bfd_link_relocatable (info))
2842 (*info->callbacks->undefined_symbol)
2843 (info, h->root.root.string, input_bfd, input_section,
2844 rel->r_vaddr - input_section->vma, true);
2845 }
2846
2847 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2848 contents,
2849 rel->r_vaddr - input_section->vma,
2850 val, addend);
2851
2852 switch (rstat)
2853 {
2854 default:
2855 abort ();
2856 case bfd_reloc_ok:
2857 break;
2858 case bfd_reloc_overflow:
2859 {
2860 const char *name;
2861 char buf[SYMNMLEN + 1];
2862
2863 if (symndx == -1)
2864 name = "*ABS*";
2865 else if (h != NULL)
2866 name = NULL;
2867 else if (sym->_n._n_n._n_zeroes == 0
2868 && sym->_n._n_n._n_offset != 0)
2869 {
2870 if (sym->_n._n_n._n_offset < obj_coff_strings_len (input_bfd))
2871 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2872 else
2873 name = "?";
2874 }
2875 else
2876 {
2877 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2878 buf[SYMNMLEN] = '\0';
2879 name = buf;
2880 }
2881
2882 (*info->callbacks->reloc_overflow)
2883 (info, (h ? &h->root : NULL), name, howto->name,
2884 (bfd_vma) 0, input_bfd, input_section,
2885 rel->r_vaddr - input_section->vma);
2886 }
2887 }
2888 }
2889
2890 return true;
2891 }
2892
2893 /* This is a version of bfd_generic_get_relocated_section_contents
2894 which uses sh_relocate_section. */
2895
2896 static bfd_byte *
2897 sh_coff_get_relocated_section_contents (bfd *output_bfd,
2898 struct bfd_link_info *link_info,
2899 struct bfd_link_order *link_order,
2900 bfd_byte *data,
2901 bool relocatable,
2902 asymbol **symbols)
2903 {
2904 asection *input_section = link_order->u.indirect.section;
2905 bfd *input_bfd = input_section->owner;
2906 asection **sections = NULL;
2907 struct internal_reloc *internal_relocs = NULL;
2908 struct internal_syment *internal_syms = NULL;
2909
2910 /* We only need to handle the case of relaxing, or of having a
2911 particular set of section contents, specially. */
2912 if (relocatable
2913 || coff_section_data (input_bfd, input_section) == NULL
2914 || coff_section_data (input_bfd, input_section)->contents == NULL)
2915 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
2916 link_order, data,
2917 relocatable,
2918 symbols);
2919
2920 bfd_byte *orig_data = data;
2921 if (data == NULL)
2922 {
2923 data = bfd_malloc (input_section->size);
2924 if (data == NULL)
2925 return NULL;
2926 }
2927 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
2928 (size_t) input_section->size);
2929
2930 if ((input_section->flags & SEC_RELOC) != 0
2931 && input_section->reloc_count > 0)
2932 {
2933 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
2934 bfd_byte *esym, *esymend;
2935 struct internal_syment *isymp;
2936 asection **secpp;
2937 bfd_size_type amt;
2938
2939 if (! _bfd_coff_get_external_symbols (input_bfd))
2940 goto error_return;
2941
2942 internal_relocs = (_bfd_coff_read_internal_relocs
2943 (input_bfd, input_section, false, (bfd_byte *) NULL,
2944 false, (struct internal_reloc *) NULL));
2945 if (internal_relocs == NULL)
2946 goto error_return;
2947
2948 amt = obj_raw_syment_count (input_bfd);
2949 amt *= sizeof (struct internal_syment);
2950 internal_syms = (struct internal_syment *) bfd_malloc (amt);
2951 if (internal_syms == NULL)
2952 goto error_return;
2953
2954 amt = obj_raw_syment_count (input_bfd);
2955 amt *= sizeof (asection *);
2956 sections = (asection **) bfd_malloc (amt);
2957 if (sections == NULL)
2958 goto error_return;
2959
2960 isymp = internal_syms;
2961 secpp = sections;
2962 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
2963 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
2964 while (esym < esymend)
2965 {
2966 bfd_coff_swap_sym_in (input_bfd, esym, isymp);
2967
2968 if (isymp->n_scnum != 0)
2969 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
2970 else
2971 {
2972 if (isymp->n_value == 0)
2973 *secpp = bfd_und_section_ptr;
2974 else
2975 *secpp = bfd_com_section_ptr;
2976 }
2977
2978 esym += (isymp->n_numaux + 1) * symesz;
2979 secpp += isymp->n_numaux + 1;
2980 isymp += isymp->n_numaux + 1;
2981 }
2982
2983 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
2984 input_section, data, internal_relocs,
2985 internal_syms, sections))
2986 goto error_return;
2987
2988 free (sections);
2989 sections = NULL;
2990 free (internal_syms);
2991 internal_syms = NULL;
2992 free (internal_relocs);
2993 internal_relocs = NULL;
2994 }
2995
2996 return data;
2997
2998 error_return:
2999 free (internal_relocs);
3000 free (internal_syms);
3001 free (sections);
3002 if (orig_data == NULL)
3003 free (data);
3004 return NULL;
3005 }
3006
3007 /* The target vectors. */
3008
3009 #ifndef TARGET_SHL_SYM
3010 CREATE_BIG_COFF_TARGET_VEC (sh_coff_vec, "coff-sh", BFD_IS_RELAXABLE, 0, '_', NULL, COFF_SWAP_TABLE)
3011 #endif
3012
3013 #ifdef TARGET_SHL_SYM
3014 #define TARGET_SYM TARGET_SHL_SYM
3015 #else
3016 #define TARGET_SYM sh_coff_le_vec
3017 #endif
3018
3019 #ifndef TARGET_SHL_NAME
3020 #define TARGET_SHL_NAME "coff-shl"
3021 #endif
3022
3023 #ifdef COFF_WITH_PE
3024 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3025 SEC_CODE | SEC_DATA, '_', NULL, COFF_SWAP_TABLE);
3026 #else
3027 CREATE_LITTLE_COFF_TARGET_VEC (TARGET_SYM, TARGET_SHL_NAME, BFD_IS_RELAXABLE,
3028 0, '_', NULL, COFF_SWAP_TABLE)
3029 #endif
3030
3031 #ifndef TARGET_SHL_SYM
3032
3033 /* Some people want versions of the SH COFF target which do not align
3034 to 16 byte boundaries. We implement that by adding a couple of new
3035 target vectors. These are just like the ones above, but they
3036 change the default section alignment. To generate them in the
3037 assembler, use -small. To use them in the linker, use -b
3038 coff-sh{l}-small and -oformat coff-sh{l}-small.
3039
3040 Yes, this is a horrible hack. A general solution for setting
3041 section alignment in COFF is rather complex. ELF handles this
3042 correctly. */
3043
3044 /* Only recognize the small versions if the target was not defaulted.
3045 Otherwise we won't recognize the non default endianness. */
3046
3047 static bfd_cleanup
3048 coff_small_object_p (bfd *abfd)
3049 {
3050 if (abfd->target_defaulted)
3051 {
3052 bfd_set_error (bfd_error_wrong_format);
3053 return NULL;
3054 }
3055 return coff_object_p (abfd);
3056 }
3057
3058 /* Set the section alignment for the small versions. */
3059
3060 static bool
3061 coff_small_new_section_hook (bfd *abfd, asection *section)
3062 {
3063 if (! coff_new_section_hook (abfd, section))
3064 return false;
3065
3066 /* We must align to at least a four byte boundary, because longword
3067 accesses must be on a four byte boundary. */
3068 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
3069 section->alignment_power = 2;
3070
3071 return true;
3072 }
3073
3074 /* This is copied from bfd_coff_std_swap_table so that we can change
3075 the default section alignment power. */
3076
3077 static const bfd_coff_backend_data bfd_coff_small_swap_table =
3078 {
3079 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
3080 coff_swap_aux_out, coff_swap_sym_out,
3081 coff_swap_lineno_out, coff_swap_reloc_out,
3082 coff_swap_filehdr_out, coff_swap_aouthdr_out,
3083 coff_swap_scnhdr_out,
3084 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ, FILNMLEN,
3085 #ifdef COFF_LONG_FILENAMES
3086 true,
3087 #else
3088 false,
3089 #endif
3090 COFF_DEFAULT_LONG_SECTION_NAMES,
3091 2,
3092 #ifdef COFF_FORCE_SYMBOLS_IN_STRINGS
3093 true,
3094 #else
3095 false,
3096 #endif
3097 #ifdef COFF_DEBUG_STRING_WIDE_PREFIX
3098 4,
3099 #else
3100 2,
3101 #endif
3102 32768,
3103 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
3104 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
3105 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
3106 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
3107 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
3108 coff_classify_symbol, coff_compute_section_file_positions,
3109 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
3110 coff_adjust_symndx, coff_link_add_one_symbol,
3111 coff_link_output_has_begun, coff_final_link_postscript,
3112 bfd_pe_print_pdata
3113 };
3114
3115 #define coff_small_close_and_cleanup \
3116 coff_close_and_cleanup
3117 #define coff_small_bfd_free_cached_info \
3118 coff_bfd_free_cached_info
3119 #define coff_small_get_section_contents \
3120 coff_get_section_contents
3121 #define coff_small_get_section_contents_in_window \
3122 coff_get_section_contents_in_window
3123
3124 extern const bfd_target sh_coff_small_le_vec;
3125
3126 const bfd_target sh_coff_small_vec =
3127 {
3128 "coff-sh-small", /* name */
3129 bfd_target_coff_flavour,
3130 BFD_ENDIAN_BIG, /* data byte order is big */
3131 BFD_ENDIAN_BIG, /* header byte order is big */
3132
3133 (HAS_RELOC | EXEC_P /* object flags */
3134 | HAS_LINENO | HAS_DEBUG
3135 | HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3136
3137 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3138 '_', /* leading symbol underscore */
3139 '/', /* ar_pad_char */
3140 15, /* ar_max_namelen */
3141 0, /* match priority. */
3142 TARGET_KEEP_UNUSED_SECTION_SYMBOLS, /* keep unused section symbols. */
3143 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3144 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3145 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
3146 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
3147 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
3148 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
3149
3150 { /* bfd_check_format */
3151 _bfd_dummy_target,
3152 coff_small_object_p,
3153 bfd_generic_archive_p,
3154 _bfd_dummy_target
3155 },
3156 { /* bfd_set_format */
3157 _bfd_bool_bfd_false_error,
3158 coff_mkobject,
3159 _bfd_generic_mkarchive,
3160 _bfd_bool_bfd_false_error
3161 },
3162 { /* bfd_write_contents */
3163 _bfd_bool_bfd_false_error,
3164 coff_write_object_contents,
3165 _bfd_write_archive_contents,
3166 _bfd_bool_bfd_false_error
3167 },
3168
3169 BFD_JUMP_TABLE_GENERIC (coff_small),
3170 BFD_JUMP_TABLE_COPY (coff),
3171 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3172 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3173 BFD_JUMP_TABLE_SYMBOLS (coff),
3174 BFD_JUMP_TABLE_RELOCS (coff),
3175 BFD_JUMP_TABLE_WRITE (coff),
3176 BFD_JUMP_TABLE_LINK (coff),
3177 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3178
3179 &sh_coff_small_le_vec,
3180
3181 &bfd_coff_small_swap_table
3182 };
3183
3184 const bfd_target sh_coff_small_le_vec =
3185 {
3186 "coff-shl-small", /* name */
3187 bfd_target_coff_flavour,
3188 BFD_ENDIAN_LITTLE, /* data byte order is little */
3189 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
3190
3191 (HAS_RELOC | EXEC_P /* object flags */
3192 | HAS_LINENO | HAS_DEBUG
3193 | HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
3194
3195 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
3196 '_', /* leading symbol underscore */
3197 '/', /* ar_pad_char */
3198 15, /* ar_max_namelen */
3199 0, /* match priority. */
3200 TARGET_KEEP_UNUSED_SECTION_SYMBOLS, /* keep unused section symbols. */
3201 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3202 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3203 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
3204 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
3205 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
3206 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
3207
3208 { /* bfd_check_format */
3209 _bfd_dummy_target,
3210 coff_small_object_p,
3211 bfd_generic_archive_p,
3212 _bfd_dummy_target
3213 },
3214 { /* bfd_set_format */
3215 _bfd_bool_bfd_false_error,
3216 coff_mkobject,
3217 _bfd_generic_mkarchive,
3218 _bfd_bool_bfd_false_error
3219 },
3220 { /* bfd_write_contents */
3221 _bfd_bool_bfd_false_error,
3222 coff_write_object_contents,
3223 _bfd_write_archive_contents,
3224 _bfd_bool_bfd_false_error
3225 },
3226
3227 BFD_JUMP_TABLE_GENERIC (coff_small),
3228 BFD_JUMP_TABLE_COPY (coff),
3229 BFD_JUMP_TABLE_CORE (_bfd_nocore),
3230 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
3231 BFD_JUMP_TABLE_SYMBOLS (coff),
3232 BFD_JUMP_TABLE_RELOCS (coff),
3233 BFD_JUMP_TABLE_WRITE (coff),
3234 BFD_JUMP_TABLE_LINK (coff),
3235 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
3236
3237 &sh_coff_small_vec,
3238
3239 &bfd_coff_small_swap_table
3240 };
3241 #endif