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[binutils-gdb.git] / bfd / coff-sh.c
1 /* BFD back-end for Hitachi Super-H COFF binaries.
2 Copyright 1993, 94, 95, 96, 97, 1998 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4 Written by Steve Chamberlain, <sac@cygnus.com>.
5 Relaxing code written by Ian Lance Taylor, <ian@cygnus.com>.
6
7 This file is part of BFD, the Binary File Descriptor library.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
22
23 #include "bfd.h"
24 #include "sysdep.h"
25 #include "libbfd.h"
26 #include "bfdlink.h"
27 #include "coff/sh.h"
28 #include "coff/internal.h"
29 #include "libcoff.h"
30
31 /* Internal functions. */
32 static bfd_reloc_status_type sh_reloc
33 PARAMS ((bfd *, arelent *, asymbol *, PTR, asection *, bfd *, char **));
34 static long get_symbol_value PARAMS ((asymbol *));
35 static boolean sh_merge_private_data PARAMS ((bfd *, bfd *));
36 static boolean sh_relax_section
37 PARAMS ((bfd *, asection *, struct bfd_link_info *, boolean *));
38 static boolean sh_relax_delete_bytes
39 PARAMS ((bfd *, asection *, bfd_vma, int));
40 static const struct sh_opcode *sh_insn_info PARAMS ((unsigned int));
41 static boolean sh_align_loads
42 PARAMS ((bfd *, asection *, struct internal_reloc *, bfd_byte *, boolean *));
43 static boolean sh_swap_insns
44 PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
45 static boolean sh_relocate_section
46 PARAMS ((bfd *, struct bfd_link_info *, bfd *, asection *, bfd_byte *,
47 struct internal_reloc *, struct internal_syment *, asection **));
48 static bfd_byte *sh_coff_get_relocated_section_contents
49 PARAMS ((bfd *, struct bfd_link_info *, struct bfd_link_order *,
50 bfd_byte *, boolean, asymbol **));
51
52 /* Default section alignment to 2**4. */
53 #define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (4)
54
55 /* Generate long file names. */
56 #define COFF_LONG_FILENAMES
57
58 /* The supported relocations. There are a lot of relocations defined
59 in coff/internal.h which we do not expect to ever see. */
60 static reloc_howto_type sh_coff_howtos[] =
61 {
62 { 0 },
63 { 1 },
64 { 2 },
65 { 3 }, /* R_SH_PCREL8 */
66 { 4 }, /* R_SH_PCREL16 */
67 { 5 }, /* R_SH_HIGH8 */
68 { 6 }, /* R_SH_IMM24 */
69 { 7 }, /* R_SH_LOW16 */
70 { 8 },
71 { 9 }, /* R_SH_PCDISP8BY4 */
72
73 HOWTO (R_SH_PCDISP8BY2, /* type */
74 1, /* rightshift */
75 1, /* size (0 = byte, 1 = short, 2 = long) */
76 8, /* bitsize */
77 true, /* pc_relative */
78 0, /* bitpos */
79 complain_overflow_signed, /* complain_on_overflow */
80 sh_reloc, /* special_function */
81 "r_pcdisp8by2", /* name */
82 true, /* partial_inplace */
83 0xff, /* src_mask */
84 0xff, /* dst_mask */
85 true), /* pcrel_offset */
86
87 { 11 }, /* R_SH_PCDISP8 */
88
89 HOWTO (R_SH_PCDISP, /* type */
90 1, /* rightshift */
91 1, /* size (0 = byte, 1 = short, 2 = long) */
92 12, /* bitsize */
93 true, /* pc_relative */
94 0, /* bitpos */
95 complain_overflow_signed, /* complain_on_overflow */
96 sh_reloc, /* special_function */
97 "r_pcdisp12by2", /* name */
98 true, /* partial_inplace */
99 0xfff, /* src_mask */
100 0xfff, /* dst_mask */
101 true), /* pcrel_offset */
102
103 { 13 },
104
105 HOWTO (R_SH_IMM32, /* type */
106 0, /* rightshift */
107 2, /* size (0 = byte, 1 = short, 2 = long) */
108 32, /* bitsize */
109 false, /* pc_relative */
110 0, /* bitpos */
111 complain_overflow_bitfield, /* complain_on_overflow */
112 sh_reloc, /* special_function */
113 "r_imm32", /* name */
114 true, /* partial_inplace */
115 0xffffffff, /* src_mask */
116 0xffffffff, /* dst_mask */
117 false), /* pcrel_offset */
118
119 { 15 },
120 { 16 }, /* R_SH_IMM8 */
121 { 17 }, /* R_SH_IMM8BY2 */
122 { 18 }, /* R_SH_IMM8BY4 */
123 { 19 }, /* R_SH_IMM4 */
124 { 20 }, /* R_SH_IMM4BY2 */
125 { 21 }, /* R_SH_IMM4BY4 */
126
127 HOWTO (R_SH_PCRELIMM8BY2, /* type */
128 1, /* rightshift */
129 1, /* size (0 = byte, 1 = short, 2 = long) */
130 8, /* bitsize */
131 true, /* pc_relative */
132 0, /* bitpos */
133 complain_overflow_unsigned, /* complain_on_overflow */
134 sh_reloc, /* special_function */
135 "r_pcrelimm8by2", /* name */
136 true, /* partial_inplace */
137 0xff, /* src_mask */
138 0xff, /* dst_mask */
139 true), /* pcrel_offset */
140
141 HOWTO (R_SH_PCRELIMM8BY4, /* type */
142 2, /* rightshift */
143 1, /* size (0 = byte, 1 = short, 2 = long) */
144 8, /* bitsize */
145 true, /* pc_relative */
146 0, /* bitpos */
147 complain_overflow_unsigned, /* complain_on_overflow */
148 sh_reloc, /* special_function */
149 "r_pcrelimm8by4", /* name */
150 true, /* partial_inplace */
151 0xff, /* src_mask */
152 0xff, /* dst_mask */
153 true), /* pcrel_offset */
154
155 HOWTO (R_SH_IMM16, /* type */
156 0, /* rightshift */
157 1, /* size (0 = byte, 1 = short, 2 = long) */
158 16, /* bitsize */
159 false, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield, /* complain_on_overflow */
162 sh_reloc, /* special_function */
163 "r_imm16", /* name */
164 true, /* partial_inplace */
165 0xffff, /* src_mask */
166 0xffff, /* dst_mask */
167 false), /* pcrel_offset */
168
169 HOWTO (R_SH_SWITCH16, /* type */
170 0, /* rightshift */
171 1, /* size (0 = byte, 1 = short, 2 = long) */
172 16, /* bitsize */
173 false, /* pc_relative */
174 0, /* bitpos */
175 complain_overflow_bitfield, /* complain_on_overflow */
176 sh_reloc, /* special_function */
177 "r_switch16", /* name */
178 true, /* partial_inplace */
179 0xffff, /* src_mask */
180 0xffff, /* dst_mask */
181 false), /* pcrel_offset */
182
183 HOWTO (R_SH_SWITCH32, /* type */
184 0, /* rightshift */
185 2, /* size (0 = byte, 1 = short, 2 = long) */
186 32, /* bitsize */
187 false, /* pc_relative */
188 0, /* bitpos */
189 complain_overflow_bitfield, /* complain_on_overflow */
190 sh_reloc, /* special_function */
191 "r_switch32", /* name */
192 true, /* partial_inplace */
193 0xffffffff, /* src_mask */
194 0xffffffff, /* dst_mask */
195 false), /* pcrel_offset */
196
197 HOWTO (R_SH_USES, /* type */
198 0, /* rightshift */
199 1, /* size (0 = byte, 1 = short, 2 = long) */
200 16, /* bitsize */
201 false, /* pc_relative */
202 0, /* bitpos */
203 complain_overflow_bitfield, /* complain_on_overflow */
204 sh_reloc, /* special_function */
205 "r_uses", /* name */
206 true, /* partial_inplace */
207 0xffff, /* src_mask */
208 0xffff, /* dst_mask */
209 false), /* pcrel_offset */
210
211 HOWTO (R_SH_COUNT, /* type */
212 0, /* rightshift */
213 2, /* size (0 = byte, 1 = short, 2 = long) */
214 32, /* bitsize */
215 false, /* pc_relative */
216 0, /* bitpos */
217 complain_overflow_bitfield, /* complain_on_overflow */
218 sh_reloc, /* special_function */
219 "r_count", /* name */
220 true, /* partial_inplace */
221 0xffffffff, /* src_mask */
222 0xffffffff, /* dst_mask */
223 false), /* pcrel_offset */
224
225 HOWTO (R_SH_ALIGN, /* type */
226 0, /* rightshift */
227 2, /* size (0 = byte, 1 = short, 2 = long) */
228 32, /* bitsize */
229 false, /* pc_relative */
230 0, /* bitpos */
231 complain_overflow_bitfield, /* complain_on_overflow */
232 sh_reloc, /* special_function */
233 "r_align", /* name */
234 true, /* partial_inplace */
235 0xffffffff, /* src_mask */
236 0xffffffff, /* dst_mask */
237 false), /* pcrel_offset */
238
239 HOWTO (R_SH_CODE, /* type */
240 0, /* rightshift */
241 2, /* size (0 = byte, 1 = short, 2 = long) */
242 32, /* bitsize */
243 false, /* pc_relative */
244 0, /* bitpos */
245 complain_overflow_bitfield, /* complain_on_overflow */
246 sh_reloc, /* special_function */
247 "r_code", /* name */
248 true, /* partial_inplace */
249 0xffffffff, /* src_mask */
250 0xffffffff, /* dst_mask */
251 false), /* pcrel_offset */
252
253 HOWTO (R_SH_DATA, /* type */
254 0, /* rightshift */
255 2, /* size (0 = byte, 1 = short, 2 = long) */
256 32, /* bitsize */
257 false, /* pc_relative */
258 0, /* bitpos */
259 complain_overflow_bitfield, /* complain_on_overflow */
260 sh_reloc, /* special_function */
261 "r_data", /* name */
262 true, /* partial_inplace */
263 0xffffffff, /* src_mask */
264 0xffffffff, /* dst_mask */
265 false), /* pcrel_offset */
266
267 HOWTO (R_SH_LABEL, /* type */
268 0, /* rightshift */
269 2, /* size (0 = byte, 1 = short, 2 = long) */
270 32, /* bitsize */
271 false, /* pc_relative */
272 0, /* bitpos */
273 complain_overflow_bitfield, /* complain_on_overflow */
274 sh_reloc, /* special_function */
275 "r_label", /* name */
276 true, /* partial_inplace */
277 0xffffffff, /* src_mask */
278 0xffffffff, /* dst_mask */
279 false), /* pcrel_offset */
280
281 HOWTO (R_SH_SWITCH8, /* type */
282 0, /* rightshift */
283 0, /* size (0 = byte, 1 = short, 2 = long) */
284 8, /* bitsize */
285 false, /* pc_relative */
286 0, /* bitpos */
287 complain_overflow_bitfield, /* complain_on_overflow */
288 sh_reloc, /* special_function */
289 "r_switch8", /* name */
290 true, /* partial_inplace */
291 0xff, /* src_mask */
292 0xff, /* dst_mask */
293 false) /* pcrel_offset */
294 };
295
296 #define SH_COFF_HOWTO_COUNT (sizeof sh_coff_howtos / sizeof sh_coff_howtos[0])
297
298 /* Check for a bad magic number. */
299 #define BADMAG(x) SHBADMAG(x)
300
301 /* Customize coffcode.h (this is not currently used). */
302 #define SH 1
303
304 /* FIXME: This should not be set here. */
305 #define __A_MAGIC_SET__
306
307 /* Swap the r_offset field in and out. */
308 #define SWAP_IN_RELOC_OFFSET bfd_h_get_32
309 #define SWAP_OUT_RELOC_OFFSET bfd_h_put_32
310
311 /* Swap out extra information in the reloc structure. */
312 #define SWAP_OUT_RELOC_EXTRA(abfd, src, dst) \
313 do \
314 { \
315 dst->r_stuff[0] = 'S'; \
316 dst->r_stuff[1] = 'C'; \
317 } \
318 while (0)
319
320 /* Get the value of a symbol, when performing a relocation. */
321
322 static long
323 get_symbol_value (symbol)
324 asymbol *symbol;
325 {
326 bfd_vma relocation;
327
328 if (bfd_is_com_section (symbol->section))
329 relocation = 0;
330 else
331 relocation = (symbol->value +
332 symbol->section->output_section->vma +
333 symbol->section->output_offset);
334
335 return relocation;
336 }
337
338 /* This macro is used in coffcode.h to get the howto corresponding to
339 an internal reloc. */
340
341 #define RTYPE2HOWTO(relent, internal) \
342 ((relent)->howto = \
343 ((internal)->r_type < SH_COFF_HOWTO_COUNT \
344 ? &sh_coff_howtos[(internal)->r_type] \
345 : (reloc_howto_type *) NULL))
346
347 /* This is the same as the macro in coffcode.h, except that it copies
348 r_offset into reloc_entry->addend for some relocs. */
349 #define CALC_ADDEND(abfd, ptr, reloc, cache_ptr) \
350 { \
351 coff_symbol_type *coffsym = (coff_symbol_type *) NULL; \
352 if (ptr && bfd_asymbol_bfd (ptr) != abfd) \
353 coffsym = (obj_symbols (abfd) \
354 + (cache_ptr->sym_ptr_ptr - symbols)); \
355 else if (ptr) \
356 coffsym = coff_symbol_from (abfd, ptr); \
357 if (coffsym != (coff_symbol_type *) NULL \
358 && coffsym->native->u.syment.n_scnum == 0) \
359 cache_ptr->addend = 0; \
360 else if (ptr && bfd_asymbol_bfd (ptr) == abfd \
361 && ptr->section != (asection *) NULL) \
362 cache_ptr->addend = - (ptr->section->vma + ptr->value); \
363 else \
364 cache_ptr->addend = 0; \
365 if ((reloc).r_type == R_SH_SWITCH8 \
366 || (reloc).r_type == R_SH_SWITCH16 \
367 || (reloc).r_type == R_SH_SWITCH32 \
368 || (reloc).r_type == R_SH_USES \
369 || (reloc).r_type == R_SH_COUNT \
370 || (reloc).r_type == R_SH_ALIGN) \
371 cache_ptr->addend = (reloc).r_offset; \
372 }
373
374 /* This is the howto function for the SH relocations. */
375
376 static bfd_reloc_status_type
377 sh_reloc (abfd, reloc_entry, symbol_in, data, input_section, output_bfd,
378 error_message)
379 bfd *abfd;
380 arelent *reloc_entry;
381 asymbol *symbol_in;
382 PTR data;
383 asection *input_section;
384 bfd *output_bfd;
385 char **error_message;
386 {
387 unsigned long insn;
388 bfd_vma sym_value;
389 unsigned short r_type;
390 bfd_vma addr = reloc_entry->address;
391 bfd_byte *hit_data = addr + (bfd_byte *) data;
392
393 r_type = reloc_entry->howto->type;
394
395 if (output_bfd != NULL)
396 {
397 /* Partial linking--do nothing. */
398 reloc_entry->address += input_section->output_offset;
399 return bfd_reloc_ok;
400 }
401
402 /* Almost all relocs have to do with relaxing. If any work must be
403 done for them, it has been done in sh_relax_section. */
404 if (r_type != R_SH_IMM32
405 && (r_type != R_SH_PCDISP
406 || (symbol_in->flags & BSF_LOCAL) != 0))
407 return bfd_reloc_ok;
408
409 if (symbol_in != NULL
410 && bfd_is_und_section (symbol_in->section))
411 return bfd_reloc_undefined;
412
413 sym_value = get_symbol_value (symbol_in);
414
415 switch (r_type)
416 {
417 case R_SH_IMM32:
418 insn = bfd_get_32 (abfd, hit_data);
419 insn += sym_value + reloc_entry->addend;
420 bfd_put_32 (abfd, insn, hit_data);
421 break;
422 case R_SH_PCDISP:
423 insn = bfd_get_16 (abfd, hit_data);
424 sym_value += reloc_entry->addend;
425 sym_value -= (input_section->output_section->vma
426 + input_section->output_offset
427 + addr
428 + 4);
429 sym_value += (insn & 0xfff) << 1;
430 if (insn & 0x800)
431 sym_value -= 0x1000;
432 insn = (insn & 0xf000) | (sym_value & 0xfff);
433 bfd_put_16 (abfd, insn, hit_data);
434 if (sym_value < (bfd_vma) -0x1000 || sym_value >= 0x1000)
435 return bfd_reloc_overflow;
436 break;
437 default:
438 abort ();
439 break;
440 }
441
442 return bfd_reloc_ok;
443 }
444
445 /* This routine checks for linking big and little endian objects
446 together. */
447
448 static boolean
449 sh_merge_private_data (ibfd, obfd)
450 bfd *ibfd;
451 bfd *obfd;
452 {
453 if (ibfd->xvec->byteorder != obfd->xvec->byteorder
454 && obfd->xvec->byteorder != BFD_ENDIAN_UNKNOWN)
455 {
456 (*_bfd_error_handler)
457 ("%s: compiled for a %s endian system and target is %s endian",
458 bfd_get_filename (ibfd),
459 bfd_big_endian (ibfd) ? "big" : "little",
460 bfd_big_endian (obfd) ? "big" : "little");
461
462 bfd_set_error (bfd_error_wrong_format);
463 return false;
464 }
465
466 return true;
467 }
468
469 #define coff_bfd_merge_private_bfd_data sh_merge_private_data
470
471 /* We can do relaxing. */
472 #define coff_bfd_relax_section sh_relax_section
473
474 /* We use the special COFF backend linker. */
475 #define coff_relocate_section sh_relocate_section
476
477 /* When relaxing, we need to use special code to get the relocated
478 section contents. */
479 #define coff_bfd_get_relocated_section_contents \
480 sh_coff_get_relocated_section_contents
481
482 #include "coffcode.h"
483 \f
484 /* This function handles relaxing on the SH.
485
486 Function calls on the SH look like this:
487
488 movl L1,r0
489 ...
490 jsr @r0
491 ...
492 L1:
493 .long function
494
495 The compiler and assembler will cooperate to create R_SH_USES
496 relocs on the jsr instructions. The r_offset field of the
497 R_SH_USES reloc is the PC relative offset to the instruction which
498 loads the register (the r_offset field is computed as though it
499 were a jump instruction, so the offset value is actually from four
500 bytes past the instruction). The linker can use this reloc to
501 determine just which function is being called, and thus decide
502 whether it is possible to replace the jsr with a bsr.
503
504 If multiple function calls are all based on a single register load
505 (i.e., the same function is called multiple times), the compiler
506 guarantees that each function call will have an R_SH_USES reloc.
507 Therefore, if the linker is able to convert each R_SH_USES reloc
508 which refers to that address, it can safely eliminate the register
509 load.
510
511 When the assembler creates an R_SH_USES reloc, it examines it to
512 determine which address is being loaded (L1 in the above example).
513 It then counts the number of references to that address, and
514 creates an R_SH_COUNT reloc at that address. The r_offset field of
515 the R_SH_COUNT reloc will be the number of references. If the
516 linker is able to eliminate a register load, it can use the
517 R_SH_COUNT reloc to see whether it can also eliminate the function
518 address.
519
520 SH relaxing also handles another, unrelated, matter. On the SH, if
521 a load or store instruction is not aligned on a four byte boundary,
522 the memory cycle interferes with the 32 bit instruction fetch,
523 causing a one cycle bubble in the pipeline. Therefore, we try to
524 align load and store instructions on four byte boundaries if we
525 can, by swapping them with one of the adjacent instructions. */
526
527 static boolean
528 sh_relax_section (abfd, sec, link_info, again)
529 bfd *abfd;
530 asection *sec;
531 struct bfd_link_info *link_info;
532 boolean *again;
533 {
534 struct internal_reloc *internal_relocs;
535 struct internal_reloc *free_relocs = NULL;
536 boolean have_code;
537 struct internal_reloc *irel, *irelend;
538 bfd_byte *contents = NULL;
539 bfd_byte *free_contents = NULL;
540
541 *again = false;
542
543 if (link_info->relocateable
544 || (sec->flags & SEC_RELOC) == 0
545 || sec->reloc_count == 0)
546 return true;
547
548 /* If this is the first time we have been called for this section,
549 initialize the cooked size. */
550 if (sec->_cooked_size == 0)
551 sec->_cooked_size = sec->_raw_size;
552
553 internal_relocs = (_bfd_coff_read_internal_relocs
554 (abfd, sec, link_info->keep_memory,
555 (bfd_byte *) NULL, false,
556 (struct internal_reloc *) NULL));
557 if (internal_relocs == NULL)
558 goto error_return;
559 if (! link_info->keep_memory)
560 free_relocs = internal_relocs;
561
562 have_code = false;
563
564 irelend = internal_relocs + sec->reloc_count;
565 for (irel = internal_relocs; irel < irelend; irel++)
566 {
567 bfd_vma laddr, paddr, symval;
568 unsigned short insn;
569 struct internal_reloc *irelfn, *irelscan, *irelcount;
570 struct internal_syment sym;
571 bfd_signed_vma foff;
572
573 if (irel->r_type == R_SH_CODE)
574 have_code = true;
575
576 if (irel->r_type != R_SH_USES)
577 continue;
578
579 /* Get the section contents. */
580 if (contents == NULL)
581 {
582 if (coff_section_data (abfd, sec) != NULL
583 && coff_section_data (abfd, sec)->contents != NULL)
584 contents = coff_section_data (abfd, sec)->contents;
585 else
586 {
587 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
588 if (contents == NULL)
589 goto error_return;
590 free_contents = contents;
591
592 if (! bfd_get_section_contents (abfd, sec, contents,
593 (file_ptr) 0, sec->_raw_size))
594 goto error_return;
595 }
596 }
597
598 /* The r_offset field of the R_SH_USES reloc will point us to
599 the register load. The 4 is because the r_offset field is
600 computed as though it were a jump offset, which are based
601 from 4 bytes after the jump instruction. */
602 laddr = irel->r_vaddr - sec->vma + 4;
603 /* Careful to sign extend the 32-bit offset. */
604 laddr += ((irel->r_offset & 0xffffffff) ^ 0x80000000) - 0x80000000;
605 if (laddr >= sec->_raw_size)
606 {
607 (*_bfd_error_handler) ("%s: 0x%lx: warning: bad R_SH_USES offset",
608 bfd_get_filename (abfd),
609 (unsigned long) irel->r_vaddr);
610 continue;
611 }
612 insn = bfd_get_16 (abfd, contents + laddr);
613
614 /* If the instruction is not mov.l NN,rN, we don't know what to do. */
615 if ((insn & 0xf000) != 0xd000)
616 {
617 ((*_bfd_error_handler)
618 ("%s: 0x%lx: warning: R_SH_USES points to unrecognized insn 0x%x",
619 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr, insn));
620 continue;
621 }
622
623 /* Get the address from which the register is being loaded. The
624 displacement in the mov.l instruction is quadrupled. It is a
625 displacement from four bytes after the movl instruction, but,
626 before adding in the PC address, two least significant bits
627 of the PC are cleared. We assume that the section is aligned
628 on a four byte boundary. */
629 paddr = insn & 0xff;
630 paddr *= 4;
631 paddr += (laddr + 4) &~ 3;
632 if (paddr >= sec->_raw_size)
633 {
634 ((*_bfd_error_handler)
635 ("%s: 0x%lx: warning: bad R_SH_USES load offset",
636 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
637 continue;
638 }
639
640 /* Get the reloc for the address from which the register is
641 being loaded. This reloc will tell us which function is
642 actually being called. */
643 paddr += sec->vma;
644 for (irelfn = internal_relocs; irelfn < irelend; irelfn++)
645 if (irelfn->r_vaddr == paddr
646 && irelfn->r_type == R_SH_IMM32)
647 break;
648 if (irelfn >= irelend)
649 {
650 ((*_bfd_error_handler)
651 ("%s: 0x%lx: warning: could not find expected reloc",
652 bfd_get_filename (abfd), (unsigned long) paddr));
653 continue;
654 }
655
656 /* Get the value of the symbol referred to by the reloc. */
657 if (! _bfd_coff_get_external_symbols (abfd))
658 goto error_return;
659 bfd_coff_swap_sym_in (abfd,
660 ((bfd_byte *) obj_coff_external_syms (abfd)
661 + (irelfn->r_symndx
662 * bfd_coff_symesz (abfd))),
663 &sym);
664 if (sym.n_scnum != 0 && sym.n_scnum != sec->target_index)
665 {
666 ((*_bfd_error_handler)
667 ("%s: 0x%lx: warning: symbol in unexpected section",
668 bfd_get_filename (abfd), (unsigned long) paddr));
669 continue;
670 }
671
672 if (sym.n_sclass != C_EXT)
673 {
674 symval = (sym.n_value
675 - sec->vma
676 + sec->output_section->vma
677 + sec->output_offset);
678 }
679 else
680 {
681 struct coff_link_hash_entry *h;
682
683 h = obj_coff_sym_hashes (abfd)[irelfn->r_symndx];
684 BFD_ASSERT (h != NULL);
685 if (h->root.type != bfd_link_hash_defined
686 && h->root.type != bfd_link_hash_defweak)
687 {
688 /* This appears to be a reference to an undefined
689 symbol. Just ignore it--it will be caught by the
690 regular reloc processing. */
691 continue;
692 }
693
694 symval = (h->root.u.def.value
695 + h->root.u.def.section->output_section->vma
696 + h->root.u.def.section->output_offset);
697 }
698
699 symval += bfd_get_32 (abfd, contents + paddr - sec->vma);
700
701 /* See if this function call can be shortened. */
702 foff = (symval
703 - (irel->r_vaddr
704 - sec->vma
705 + sec->output_section->vma
706 + sec->output_offset
707 + 4));
708 if (foff < -0x1000 || foff >= 0x1000)
709 {
710 /* After all that work, we can't shorten this function call. */
711 continue;
712 }
713
714 /* Shorten the function call. */
715
716 /* For simplicity of coding, we are going to modify the section
717 contents, the section relocs, and the BFD symbol table. We
718 must tell the rest of the code not to free up this
719 information. It would be possible to instead create a table
720 of changes which have to be made, as is done in coff-mips.c;
721 that would be more work, but would require less memory when
722 the linker is run. */
723
724 if (coff_section_data (abfd, sec) == NULL)
725 {
726 sec->used_by_bfd =
727 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
728 if (sec->used_by_bfd == NULL)
729 goto error_return;
730 }
731
732 coff_section_data (abfd, sec)->relocs = internal_relocs;
733 coff_section_data (abfd, sec)->keep_relocs = true;
734 free_relocs = NULL;
735
736 coff_section_data (abfd, sec)->contents = contents;
737 coff_section_data (abfd, sec)->keep_contents = true;
738 free_contents = NULL;
739
740 obj_coff_keep_syms (abfd) = true;
741
742 /* Replace the jsr with a bsr. */
743
744 /* Change the R_SH_USES reloc into an R_SH_PCDISP reloc, and
745 replace the jsr with a bsr. */
746 irel->r_type = R_SH_PCDISP;
747 irel->r_symndx = irelfn->r_symndx;
748 if (sym.n_sclass != C_EXT)
749 {
750 /* If this needs to be changed because of future relaxing,
751 it will be handled here like other internal PCDISP
752 relocs. */
753 bfd_put_16 (abfd,
754 0xb000 | ((foff >> 1) & 0xfff),
755 contents + irel->r_vaddr - sec->vma);
756 }
757 else
758 {
759 /* We can't fully resolve this yet, because the external
760 symbol value may be changed by future relaxing. We let
761 the final link phase handle it. */
762 bfd_put_16 (abfd, 0xb000, contents + irel->r_vaddr - sec->vma);
763 }
764
765 /* See if there is another R_SH_USES reloc referring to the same
766 register load. */
767 for (irelscan = internal_relocs; irelscan < irelend; irelscan++)
768 if (irelscan->r_type == R_SH_USES
769 && laddr == irelscan->r_vaddr - sec->vma + 4 + irelscan->r_offset)
770 break;
771 if (irelscan < irelend)
772 {
773 /* Some other function call depends upon this register load,
774 and we have not yet converted that function call.
775 Indeed, we may never be able to convert it. There is
776 nothing else we can do at this point. */
777 continue;
778 }
779
780 /* Look for a R_SH_COUNT reloc on the location where the
781 function address is stored. Do this before deleting any
782 bytes, to avoid confusion about the address. */
783 for (irelcount = internal_relocs; irelcount < irelend; irelcount++)
784 if (irelcount->r_vaddr == paddr
785 && irelcount->r_type == R_SH_COUNT)
786 break;
787
788 /* Delete the register load. */
789 if (! sh_relax_delete_bytes (abfd, sec, laddr, 2))
790 goto error_return;
791
792 /* That will change things, so, just in case it permits some
793 other function call to come within range, we should relax
794 again. Note that this is not required, and it may be slow. */
795 *again = true;
796
797 /* Now check whether we got a COUNT reloc. */
798 if (irelcount >= irelend)
799 {
800 ((*_bfd_error_handler)
801 ("%s: 0x%lx: warning: could not find expected COUNT reloc",
802 bfd_get_filename (abfd), (unsigned long) paddr));
803 continue;
804 }
805
806 /* The number of uses is stored in the r_offset field. We've
807 just deleted one. */
808 if (irelcount->r_offset == 0)
809 {
810 ((*_bfd_error_handler) ("%s: 0x%lx: warning: bad count",
811 bfd_get_filename (abfd),
812 (unsigned long) paddr));
813 continue;
814 }
815
816 --irelcount->r_offset;
817
818 /* If there are no more uses, we can delete the address. Reload
819 the address from irelfn, in case it was changed by the
820 previous call to sh_relax_delete_bytes. */
821 if (irelcount->r_offset == 0)
822 {
823 if (! sh_relax_delete_bytes (abfd, sec,
824 irelfn->r_vaddr - sec->vma, 4))
825 goto error_return;
826 }
827
828 /* We've done all we can with that function call. */
829 }
830
831 /* Look for load and store instructions that we can align on four
832 byte boundaries. */
833 if (have_code)
834 {
835 boolean swapped;
836
837 /* Get the section contents. */
838 if (contents == NULL)
839 {
840 if (coff_section_data (abfd, sec) != NULL
841 && coff_section_data (abfd, sec)->contents != NULL)
842 contents = coff_section_data (abfd, sec)->contents;
843 else
844 {
845 contents = (bfd_byte *) bfd_malloc (sec->_raw_size);
846 if (contents == NULL)
847 goto error_return;
848 free_contents = contents;
849
850 if (! bfd_get_section_contents (abfd, sec, contents,
851 (file_ptr) 0, sec->_raw_size))
852 goto error_return;
853 }
854 }
855
856 if (! sh_align_loads (abfd, sec, internal_relocs, contents, &swapped))
857 goto error_return;
858
859 if (swapped)
860 {
861 if (coff_section_data (abfd, sec) == NULL)
862 {
863 sec->used_by_bfd =
864 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
865 if (sec->used_by_bfd == NULL)
866 goto error_return;
867 }
868
869 coff_section_data (abfd, sec)->relocs = internal_relocs;
870 coff_section_data (abfd, sec)->keep_relocs = true;
871 free_relocs = NULL;
872
873 coff_section_data (abfd, sec)->contents = contents;
874 coff_section_data (abfd, sec)->keep_contents = true;
875 free_contents = NULL;
876
877 obj_coff_keep_syms (abfd) = true;
878 }
879 }
880
881 if (free_relocs != NULL)
882 {
883 free (free_relocs);
884 free_relocs = NULL;
885 }
886
887 if (free_contents != NULL)
888 {
889 if (! link_info->keep_memory)
890 free (free_contents);
891 else
892 {
893 /* Cache the section contents for coff_link_input_bfd. */
894 if (coff_section_data (abfd, sec) == NULL)
895 {
896 sec->used_by_bfd =
897 ((PTR) bfd_zalloc (abfd, sizeof (struct coff_section_tdata)));
898 if (sec->used_by_bfd == NULL)
899 goto error_return;
900 coff_section_data (abfd, sec)->relocs = NULL;
901 }
902 coff_section_data (abfd, sec)->contents = contents;
903 }
904 }
905
906 return true;
907
908 error_return:
909 if (free_relocs != NULL)
910 free (free_relocs);
911 if (free_contents != NULL)
912 free (free_contents);
913 return false;
914 }
915
916 /* Delete some bytes from a section while relaxing. */
917
918 static boolean
919 sh_relax_delete_bytes (abfd, sec, addr, count)
920 bfd *abfd;
921 asection *sec;
922 bfd_vma addr;
923 int count;
924 {
925 bfd_byte *contents;
926 struct internal_reloc *irel, *irelend;
927 struct internal_reloc *irelalign;
928 bfd_vma toaddr;
929 bfd_byte *esym, *esymend;
930 bfd_size_type symesz;
931 struct coff_link_hash_entry **sym_hash;
932 asection *o;
933
934 contents = coff_section_data (abfd, sec)->contents;
935
936 /* The deletion must stop at the next ALIGN reloc for an aligment
937 power larger than the number of bytes we are deleting. */
938
939 irelalign = NULL;
940 toaddr = sec->_cooked_size;
941
942 irel = coff_section_data (abfd, sec)->relocs;
943 irelend = irel + sec->reloc_count;
944 for (; irel < irelend; irel++)
945 {
946 if (irel->r_type == R_SH_ALIGN
947 && irel->r_vaddr - sec->vma > addr
948 && count < (1 << irel->r_offset))
949 {
950 irelalign = irel;
951 toaddr = irel->r_vaddr - sec->vma;
952 break;
953 }
954 }
955
956 /* Actually delete the bytes. */
957 memmove (contents + addr, contents + addr + count, toaddr - addr - count);
958 if (irelalign == NULL)
959 sec->_cooked_size -= count;
960 else
961 {
962 int i;
963
964 #define NOP_OPCODE (0x0009)
965
966 BFD_ASSERT ((count & 1) == 0);
967 for (i = 0; i < count; i += 2)
968 bfd_put_16 (abfd, NOP_OPCODE, contents + toaddr - count + i);
969 }
970
971 /* Adjust all the relocs. */
972 for (irel = coff_section_data (abfd, sec)->relocs; irel < irelend; irel++)
973 {
974 bfd_vma nraddr, stop;
975 bfd_vma start = 0;
976 int insn = 0;
977 struct internal_syment sym;
978 int off, adjust, oinsn;
979 bfd_signed_vma voff = 0;
980 boolean overflow;
981
982 /* Get the new reloc address. */
983 nraddr = irel->r_vaddr - sec->vma;
984 if ((irel->r_vaddr - sec->vma > addr
985 && irel->r_vaddr - sec->vma < toaddr)
986 || (irel->r_type == R_SH_ALIGN
987 && irel->r_vaddr - sec->vma == toaddr))
988 nraddr -= count;
989
990 /* See if this reloc was for the bytes we have deleted, in which
991 case we no longer care about it. Don't delete relocs which
992 represent addresses, though. */
993 if (irel->r_vaddr - sec->vma >= addr
994 && irel->r_vaddr - sec->vma < addr + count
995 && irel->r_type != R_SH_ALIGN
996 && irel->r_type != R_SH_CODE
997 && irel->r_type != R_SH_DATA
998 && irel->r_type != R_SH_LABEL)
999 irel->r_type = R_SH_UNUSED;
1000
1001 /* If this is a PC relative reloc, see if the range it covers
1002 includes the bytes we have deleted. */
1003 switch (irel->r_type)
1004 {
1005 default:
1006 break;
1007
1008 case R_SH_PCDISP8BY2:
1009 case R_SH_PCDISP:
1010 case R_SH_PCRELIMM8BY2:
1011 case R_SH_PCRELIMM8BY4:
1012 start = irel->r_vaddr - sec->vma;
1013 insn = bfd_get_16 (abfd, contents + nraddr);
1014 break;
1015 }
1016
1017 switch (irel->r_type)
1018 {
1019 default:
1020 start = stop = addr;
1021 break;
1022
1023 case R_SH_IMM32:
1024 /* If this reloc is against a symbol defined in this
1025 section, and the symbol will not be adjusted below, we
1026 must check the addend to see it will put the value in
1027 range to be adjusted, and hence must be changed. */
1028 bfd_coff_swap_sym_in (abfd,
1029 ((bfd_byte *) obj_coff_external_syms (abfd)
1030 + (irel->r_symndx
1031 * bfd_coff_symesz (abfd))),
1032 &sym);
1033 if (sym.n_sclass != C_EXT
1034 && sym.n_scnum == sec->target_index
1035 && ((bfd_vma) sym.n_value <= addr
1036 || (bfd_vma) sym.n_value >= toaddr))
1037 {
1038 bfd_vma val;
1039
1040 val = bfd_get_32 (abfd, contents + nraddr);
1041 val += sym.n_value;
1042 if (val > addr && val < toaddr)
1043 bfd_put_32 (abfd, val - count, contents + nraddr);
1044 }
1045 start = stop = addr;
1046 break;
1047
1048 case R_SH_PCDISP8BY2:
1049 off = insn & 0xff;
1050 if (off & 0x80)
1051 off -= 0x100;
1052 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1053 break;
1054
1055 case R_SH_PCDISP:
1056 bfd_coff_swap_sym_in (abfd,
1057 ((bfd_byte *) obj_coff_external_syms (abfd)
1058 + (irel->r_symndx
1059 * bfd_coff_symesz (abfd))),
1060 &sym);
1061 if (sym.n_sclass == C_EXT)
1062 start = stop = addr;
1063 else
1064 {
1065 off = insn & 0xfff;
1066 if (off & 0x800)
1067 off -= 0x1000;
1068 stop = (bfd_vma) ((bfd_signed_vma) start + 4 + off * 2);
1069 }
1070 break;
1071
1072 case R_SH_PCRELIMM8BY2:
1073 off = insn & 0xff;
1074 stop = start + 4 + off * 2;
1075 break;
1076
1077 case R_SH_PCRELIMM8BY4:
1078 off = insn & 0xff;
1079 stop = (start &~ (bfd_vma) 3) + 4 + off * 4;
1080 break;
1081
1082 case R_SH_SWITCH8:
1083 case R_SH_SWITCH16:
1084 case R_SH_SWITCH32:
1085 /* These relocs types represent
1086 .word L2-L1
1087 The r_offset field holds the difference between the reloc
1088 address and L1. That is the start of the reloc, and
1089 adding in the contents gives us the top. We must adjust
1090 both the r_offset field and the section contents. */
1091
1092 start = irel->r_vaddr - sec->vma;
1093 stop = (bfd_vma) ((bfd_signed_vma) start - (long) irel->r_offset);
1094
1095 if (start > addr
1096 && start < toaddr
1097 && (stop <= addr || stop >= toaddr))
1098 irel->r_offset += count;
1099 else if (stop > addr
1100 && stop < toaddr
1101 && (start <= addr || start >= toaddr))
1102 irel->r_offset -= count;
1103
1104 start = stop;
1105
1106 if (irel->r_type == R_SH_SWITCH16)
1107 voff = bfd_get_signed_16 (abfd, contents + nraddr);
1108 else if (irel->r_type == R_SH_SWITCH8)
1109 voff = bfd_get_8 (abfd, contents + nraddr);
1110 else
1111 voff = bfd_get_signed_32 (abfd, contents + nraddr);
1112 stop = (bfd_vma) ((bfd_signed_vma) start + voff);
1113
1114 break;
1115
1116 case R_SH_USES:
1117 start = irel->r_vaddr - sec->vma;
1118 stop = (bfd_vma) ((bfd_signed_vma) start
1119 + (long) irel->r_offset
1120 + 4);
1121 break;
1122 }
1123
1124 if (start > addr
1125 && start < toaddr
1126 && (stop <= addr || stop >= toaddr))
1127 adjust = count;
1128 else if (stop > addr
1129 && stop < toaddr
1130 && (start <= addr || start >= toaddr))
1131 adjust = - count;
1132 else
1133 adjust = 0;
1134
1135 if (adjust != 0)
1136 {
1137 oinsn = insn;
1138 overflow = false;
1139 switch (irel->r_type)
1140 {
1141 default:
1142 abort ();
1143 break;
1144
1145 case R_SH_PCDISP8BY2:
1146 case R_SH_PCRELIMM8BY2:
1147 insn += adjust / 2;
1148 if ((oinsn & 0xff00) != (insn & 0xff00))
1149 overflow = true;
1150 bfd_put_16 (abfd, insn, contents + nraddr);
1151 break;
1152
1153 case R_SH_PCDISP:
1154 insn += adjust / 2;
1155 if ((oinsn & 0xf000) != (insn & 0xf000))
1156 overflow = true;
1157 bfd_put_16 (abfd, insn, contents + nraddr);
1158 break;
1159
1160 case R_SH_PCRELIMM8BY4:
1161 BFD_ASSERT (adjust == count || count >= 4);
1162 if (count >= 4)
1163 insn += adjust / 4;
1164 else
1165 {
1166 if ((irel->r_vaddr & 3) == 0)
1167 ++insn;
1168 }
1169 if ((oinsn & 0xff00) != (insn & 0xff00))
1170 overflow = true;
1171 bfd_put_16 (abfd, insn, contents + nraddr);
1172 break;
1173
1174 case R_SH_SWITCH8:
1175 voff += adjust;
1176 if (voff < 0 || voff >= 0xff)
1177 overflow = true;
1178 bfd_put_8 (abfd, voff, contents + nraddr);
1179 break;
1180
1181 case R_SH_SWITCH16:
1182 voff += adjust;
1183 if (voff < - 0x8000 || voff >= 0x8000)
1184 overflow = true;
1185 bfd_put_signed_16 (abfd, voff, contents + nraddr);
1186 break;
1187
1188 case R_SH_SWITCH32:
1189 voff += adjust;
1190 bfd_put_signed_32 (abfd, voff, contents + nraddr);
1191 break;
1192
1193 case R_SH_USES:
1194 irel->r_offset += adjust;
1195 break;
1196 }
1197
1198 if (overflow)
1199 {
1200 ((*_bfd_error_handler)
1201 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
1202 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
1203 bfd_set_error (bfd_error_bad_value);
1204 return false;
1205 }
1206 }
1207
1208 irel->r_vaddr = nraddr + sec->vma;
1209 }
1210
1211 /* Look through all the other sections. If there contain any IMM32
1212 relocs against internal symbols which we are not going to adjust
1213 below, we may need to adjust the addends. */
1214 for (o = abfd->sections; o != NULL; o = o->next)
1215 {
1216 struct internal_reloc *internal_relocs;
1217 struct internal_reloc *irelscan, *irelscanend;
1218 bfd_byte *ocontents;
1219
1220 if (o == sec
1221 || (o->flags & SEC_RELOC) == 0
1222 || o->reloc_count == 0)
1223 continue;
1224
1225 /* We always cache the relocs. Perhaps, if info->keep_memory is
1226 false, we should free them, if we are permitted to, when we
1227 leave sh_coff_relax_section. */
1228 internal_relocs = (_bfd_coff_read_internal_relocs
1229 (abfd, o, true, (bfd_byte *) NULL, false,
1230 (struct internal_reloc *) NULL));
1231 if (internal_relocs == NULL)
1232 return false;
1233
1234 ocontents = NULL;
1235 irelscanend = internal_relocs + o->reloc_count;
1236 for (irelscan = internal_relocs; irelscan < irelscanend; irelscan++)
1237 {
1238 struct internal_syment sym;
1239
1240 if (irelscan->r_type != R_SH_IMM32)
1241 continue;
1242
1243 bfd_coff_swap_sym_in (abfd,
1244 ((bfd_byte *) obj_coff_external_syms (abfd)
1245 + (irelscan->r_symndx
1246 * bfd_coff_symesz (abfd))),
1247 &sym);
1248 if (sym.n_sclass != C_EXT
1249 && sym.n_scnum == sec->target_index
1250 && ((bfd_vma) sym.n_value <= addr
1251 || (bfd_vma) sym.n_value >= toaddr))
1252 {
1253 bfd_vma val;
1254
1255 if (ocontents == NULL)
1256 {
1257 if (coff_section_data (abfd, o)->contents != NULL)
1258 ocontents = coff_section_data (abfd, o)->contents;
1259 else
1260 {
1261 /* We always cache the section contents.
1262 Perhaps, if info->keep_memory is false, we
1263 should free them, if we are permitted to,
1264 when we leave sh_coff_relax_section. */
1265 ocontents = (bfd_byte *) bfd_malloc (o->_raw_size);
1266 if (ocontents == NULL)
1267 return false;
1268 if (! bfd_get_section_contents (abfd, o, ocontents,
1269 (file_ptr) 0,
1270 o->_raw_size))
1271 return false;
1272 coff_section_data (abfd, o)->contents = ocontents;
1273 }
1274 }
1275
1276 val = bfd_get_32 (abfd, ocontents + irelscan->r_vaddr - o->vma);
1277 val += sym.n_value;
1278 if (val > addr && val < toaddr)
1279 bfd_put_32 (abfd, val - count,
1280 ocontents + irelscan->r_vaddr - o->vma);
1281
1282 coff_section_data (abfd, o)->keep_contents = true;
1283 }
1284 }
1285 }
1286
1287 /* Adjusting the internal symbols will not work if something has
1288 already retrieved the generic symbols. It would be possible to
1289 make this work by adjusting the generic symbols at the same time.
1290 However, this case should not arise in normal usage. */
1291 if (obj_symbols (abfd) != NULL
1292 || obj_raw_syments (abfd) != NULL)
1293 {
1294 ((*_bfd_error_handler)
1295 ("%s: fatal: generic symbols retrieved before relaxing",
1296 bfd_get_filename (abfd)));
1297 bfd_set_error (bfd_error_invalid_operation);
1298 return false;
1299 }
1300
1301 /* Adjust all the symbols. */
1302 sym_hash = obj_coff_sym_hashes (abfd);
1303 symesz = bfd_coff_symesz (abfd);
1304 esym = (bfd_byte *) obj_coff_external_syms (abfd);
1305 esymend = esym + obj_raw_syment_count (abfd) * symesz;
1306 while (esym < esymend)
1307 {
1308 struct internal_syment isym;
1309
1310 bfd_coff_swap_sym_in (abfd, (PTR) esym, (PTR) &isym);
1311
1312 if (isym.n_scnum == sec->target_index
1313 && (bfd_vma) isym.n_value > addr
1314 && (bfd_vma) isym.n_value < toaddr)
1315 {
1316 isym.n_value -= count;
1317
1318 bfd_coff_swap_sym_out (abfd, (PTR) &isym, (PTR) esym);
1319
1320 if (*sym_hash != NULL)
1321 {
1322 BFD_ASSERT ((*sym_hash)->root.type == bfd_link_hash_defined
1323 || (*sym_hash)->root.type == bfd_link_hash_defweak);
1324 BFD_ASSERT ((*sym_hash)->root.u.def.value >= addr
1325 && (*sym_hash)->root.u.def.value < toaddr);
1326 (*sym_hash)->root.u.def.value -= count;
1327 }
1328 }
1329
1330 esym += (isym.n_numaux + 1) * symesz;
1331 sym_hash += isym.n_numaux + 1;
1332 }
1333
1334 /* See if we can move the ALIGN reloc forward. We have adjusted
1335 r_vaddr for it already. */
1336 if (irelalign != NULL)
1337 {
1338 bfd_vma alignto, alignaddr;
1339
1340 alignto = BFD_ALIGN (toaddr, 1 << irelalign->r_offset);
1341 alignaddr = BFD_ALIGN (irelalign->r_vaddr - sec->vma,
1342 1 << irelalign->r_offset);
1343 if (alignto != alignaddr)
1344 {
1345 /* Tail recursion. */
1346 return sh_relax_delete_bytes (abfd, sec, alignaddr,
1347 alignto - alignaddr);
1348 }
1349 }
1350
1351 return true;
1352 }
1353 \f
1354 /* This is yet another version of the SH opcode table, used to rapidly
1355 get information about a particular instruction. */
1356
1357 /* The opcode map is represented by an array of these structures. The
1358 array is indexed by the high order four bits in the instruction. */
1359
1360 struct sh_major_opcode
1361 {
1362 /* A pointer to the instruction list. This is an array which
1363 contains all the instructions with this major opcode. */
1364 const struct sh_minor_opcode *minor_opcodes;
1365 /* The number of elements in minor_opcodes. */
1366 unsigned short count;
1367 };
1368
1369 /* This structure holds information for a set of SH opcodes. The
1370 instruction code is anded with the mask value, and the resulting
1371 value is used to search the order opcode list. */
1372
1373 struct sh_minor_opcode
1374 {
1375 /* The sorted opcode list. */
1376 const struct sh_opcode *opcodes;
1377 /* The number of elements in opcodes. */
1378 unsigned short count;
1379 /* The mask value to use when searching the opcode list. */
1380 unsigned short mask;
1381 };
1382
1383 /* This structure holds information for an SH instruction. An array
1384 of these structures is sorted in order by opcode. */
1385
1386 struct sh_opcode
1387 {
1388 /* The code for this instruction, after it has been anded with the
1389 mask value in the sh_major_opcode structure. */
1390 unsigned short opcode;
1391 /* Flags for this instruction. */
1392 unsigned short flags;
1393 };
1394
1395 /* Flag which appear in the sh_opcode structure. */
1396
1397 /* This instruction loads a value from memory. */
1398 #define LOAD (0x1)
1399
1400 /* This instruction stores a value to memory. */
1401 #define STORE (0x2)
1402
1403 /* This instruction is a branch. */
1404 #define BRANCH (0x4)
1405
1406 /* This instruction has a delay slot. */
1407 #define DELAY (0x8)
1408
1409 /* This instruction uses the value in the register in the field at
1410 mask 0x0f00 of the instruction. */
1411 #define USES1 (0x10)
1412
1413 /* This instruction uses the value in the register in the field at
1414 mask 0x00f0 of the instruction. */
1415 #define USES2 (0x20)
1416
1417 /* This instruction uses the value in register 0. */
1418 #define USESR0 (0x40)
1419
1420 /* This instruction sets the value in the register in the field at
1421 mask 0x0f00 of the instruction. */
1422 #define SETS1 (0x80)
1423
1424 /* This instruction sets the value in the register in the field at
1425 mask 0x00f0 of the instruction. */
1426 #define SETS2 (0x100)
1427
1428 /* This instruction sets register 0. */
1429 #define SETSR0 (0x200)
1430
1431 /* This instruction sets a special register. */
1432 #define SETSSP (0x400)
1433
1434 /* This instruction uses a special register. */
1435 #define USESSP (0x800)
1436
1437 /* This instruction uses the floating point register in the field at
1438 mask 0x0f00 of the instruction. */
1439 #define USESF1 (0x1000)
1440
1441 /* This instruction uses the floating point register in the field at
1442 mask 0x00f0 of the instruction. */
1443 #define USESF2 (0x2000)
1444
1445 /* This instruction uses floating point register 0. */
1446 #define USESF0 (0x4000)
1447
1448 /* This instruction sets the floating point register in the field at
1449 mask 0x0f00 of the instruction. */
1450 #define SETSF1 (0x8000)
1451
1452 static boolean sh_insn_uses_reg
1453 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1454 static boolean sh_insn_uses_freg
1455 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int));
1456 static boolean sh_insns_conflict
1457 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1458 const struct sh_opcode *));
1459 static boolean sh_load_use
1460 PARAMS ((unsigned int, const struct sh_opcode *, unsigned int,
1461 const struct sh_opcode *));
1462
1463 /* The opcode maps. */
1464
1465 #define MAP(a) a, sizeof a / sizeof a[0]
1466
1467 static const struct sh_opcode sh_opcode00[] =
1468 {
1469 { 0x0008, SETSSP }, /* clrt */
1470 { 0x0009, 0 }, /* nop */
1471 { 0x000b, BRANCH | DELAY | USESSP }, /* rts */
1472 { 0x0018, SETSSP }, /* sett */
1473 { 0x0019, SETSSP }, /* div0u */
1474 { 0x001b, 0 }, /* sleep */
1475 { 0x0028, SETSSP }, /* clrmac */
1476 { 0x002b, BRANCH | DELAY | SETSSP }, /* rte */
1477 { 0x0038, USESSP | SETSSP }, /* ldtlb */
1478 { 0x0048, SETSSP }, /* clrs */
1479 { 0x0058, SETSSP } /* sets */
1480 };
1481
1482 static const struct sh_opcode sh_opcode01[] =
1483 {
1484 { 0x0002, SETS1 | USESSP }, /* stc sr,rn */
1485 { 0x0003, BRANCH | DELAY | USES1 | SETSSP }, /* bsrf rn */
1486 { 0x000a, SETS1 | USESSP }, /* sts mach,rn */
1487 { 0x0012, SETS1 | USESSP }, /* stc gbr,rn */
1488 { 0x001a, SETS1 | USESSP }, /* sts macl,rn */
1489 { 0x0022, SETS1 | USESSP }, /* stc vbr,rn */
1490 { 0x0023, BRANCH | DELAY | USES1 }, /* braf rn */
1491 { 0x0029, SETS1 | USESSP }, /* movt rn */
1492 { 0x002a, SETS1 | USESSP }, /* sts pr,rn */
1493 { 0x0032, SETS1 | USESSP }, /* stc ssr,rn */
1494 { 0x0042, SETS1 | USESSP }, /* stc spc,rn */
1495 { 0x005a, SETS1 | USESSP }, /* sts fpul,rn */
1496 { 0x006a, SETS1 | USESSP }, /* sts fpscr,rn */
1497 { 0x0082, SETS1 | USESSP }, /* stc r0_bank,rn */
1498 { 0x0083, LOAD | USES1 }, /* pref @rn */
1499 { 0x0092, SETS1 | USESSP }, /* stc r1_bank,rn */
1500 { 0x00a2, SETS1 | USESSP }, /* stc r2_bank,rn */
1501 { 0x00b2, SETS1 | USESSP }, /* stc r3_bank,rn */
1502 { 0x00c2, SETS1 | USESSP }, /* stc r4_bank,rn */
1503 { 0x00d2, SETS1 | USESSP }, /* stc r5_bank,rn */
1504 { 0x00e2, SETS1 | USESSP }, /* stc r6_bank,rn */
1505 { 0x00f2, SETS1 | USESSP } /* stc r7_bank,rn */
1506 };
1507
1508 static const struct sh_opcode sh_opcode02[] =
1509 {
1510 { 0x0004, STORE | USES1 | USES2 | USESR0 }, /* mov.b rm,@(r0,rn) */
1511 { 0x0005, STORE | USES1 | USES2 | USESR0 }, /* mov.w rm,@(r0,rn) */
1512 { 0x0006, STORE | USES1 | USES2 | USESR0 }, /* mov.l rm,@(r0,rn) */
1513 { 0x0007, SETSSP | USES1 | USES2 }, /* mul.l rm,rn */
1514 { 0x000c, LOAD | SETS1 | USES2 | USESR0 }, /* mov.b @(r0,rm),rn */
1515 { 0x000d, LOAD | SETS1 | USES2 | USESR0 }, /* mov.w @(r0,rm),rn */
1516 { 0x000e, LOAD | SETS1 | USES2 | USESR0 }, /* mov.l @(r0,rm),rn */
1517 { 0x000f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.l @rm+,@rn+ */
1518 };
1519
1520 static const struct sh_minor_opcode sh_opcode0[] =
1521 {
1522 { MAP (sh_opcode00), 0xffff },
1523 { MAP (sh_opcode01), 0xf0ff },
1524 { MAP (sh_opcode02), 0xf00f }
1525 };
1526
1527 static const struct sh_opcode sh_opcode10[] =
1528 {
1529 { 0x1000, STORE | USES1 | USES2 } /* mov.l rm,@(disp,rn) */
1530 };
1531
1532 static const struct sh_minor_opcode sh_opcode1[] =
1533 {
1534 { MAP (sh_opcode10), 0xf000 }
1535 };
1536
1537 static const struct sh_opcode sh_opcode20[] =
1538 {
1539 { 0x2000, STORE | USES1 | USES2 }, /* mov.b rm,@rn */
1540 { 0x2001, STORE | USES1 | USES2 }, /* mov.w rm,@rn */
1541 { 0x2002, STORE | USES1 | USES2 }, /* mov.l rm,@rn */
1542 { 0x2004, STORE | SETS1 | USES1 | USES2 }, /* mov.b rm,@-rn */
1543 { 0x2005, STORE | SETS1 | USES1 | USES2 }, /* mov.w rm,@-rn */
1544 { 0x2006, STORE | SETS1 | USES1 | USES2 }, /* mov.l rm,@-rn */
1545 { 0x2007, SETSSP | USES1 | USES2 | USESSP }, /* div0s */
1546 { 0x2008, SETSSP | USES1 | USES2 }, /* tst rm,rn */
1547 { 0x2009, SETS1 | USES1 | USES2 }, /* and rm,rn */
1548 { 0x200a, SETS1 | USES1 | USES2 }, /* xor rm,rn */
1549 { 0x200b, SETS1 | USES1 | USES2 }, /* or rm,rn */
1550 { 0x200c, SETSSP | USES1 | USES2 }, /* cmp/str rm,rn */
1551 { 0x200d, SETS1 | USES1 | USES2 }, /* xtrct rm,rn */
1552 { 0x200e, SETSSP | USES1 | USES2 }, /* mulu.w rm,rn */
1553 { 0x200f, SETSSP | USES1 | USES2 } /* muls.w rm,rn */
1554 };
1555
1556 static const struct sh_minor_opcode sh_opcode2[] =
1557 {
1558 { MAP (sh_opcode20), 0xf00f }
1559 };
1560
1561 static const struct sh_opcode sh_opcode30[] =
1562 {
1563 { 0x3000, SETSSP | USES1 | USES2 }, /* cmp/eq rm,rn */
1564 { 0x3002, SETSSP | USES1 | USES2 }, /* cmp/hs rm,rn */
1565 { 0x3003, SETSSP | USES1 | USES2 }, /* cmp/ge rm,rn */
1566 { 0x3004, SETSSP | USESSP | USES1 | USES2 }, /* div1 rm,rn */
1567 { 0x3005, SETSSP | USES1 | USES2 }, /* dmulu.l rm,rn */
1568 { 0x3006, SETSSP | USES1 | USES2 }, /* cmp/hi rm,rn */
1569 { 0x3007, SETSSP | USES1 | USES2 }, /* cmp/gt rm,rn */
1570 { 0x3008, SETS1 | USES1 | USES2 }, /* sub rm,rn */
1571 { 0x300a, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* subc rm,rn */
1572 { 0x300b, SETS1 | SETSSP | USES1 | USES2 }, /* subv rm,rn */
1573 { 0x300c, SETS1 | USES1 | USES2 }, /* add rm,rn */
1574 { 0x300d, SETSSP | USES1 | USES2 }, /* dmuls.l rm,rn */
1575 { 0x300e, SETS1 | SETSSP | USES1 | USES2 | USESSP }, /* addc rm,rn */
1576 { 0x300f, SETS1 | SETSSP | USES1 | USES2 } /* addv rm,rn */
1577 };
1578
1579 static const struct sh_minor_opcode sh_opcode3[] =
1580 {
1581 { MAP (sh_opcode30), 0xf00f }
1582 };
1583
1584 static const struct sh_opcode sh_opcode40[] =
1585 {
1586 { 0x4000, SETS1 | SETSSP | USES1 }, /* shll rn */
1587 { 0x4001, SETS1 | SETSSP | USES1 }, /* shlr rn */
1588 { 0x4002, STORE | SETS1 | USES1 | USESSP }, /* sts.l mach,@-rn */
1589 { 0x4003, STORE | SETS1 | USES1 | USESSP }, /* stc.l sr,@-rn */
1590 { 0x4004, SETS1 | SETSSP | USES1 }, /* rotl rn */
1591 { 0x4005, SETS1 | SETSSP | USES1 }, /* rotr rn */
1592 { 0x4006, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,mach */
1593 { 0x4007, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,sr */
1594 { 0x4008, SETS1 | USES1 }, /* shll2 rn */
1595 { 0x4009, SETS1 | USES1 }, /* shlr2 rn */
1596 { 0x400a, SETSSP | USES1 }, /* lds rm,mach */
1597 { 0x400b, BRANCH | DELAY | USES1 }, /* jsr @rn */
1598 { 0x400e, SETSSP | USES1 }, /* ldc rm,sr */
1599 { 0x4010, SETS1 | SETSSP | USES1 }, /* dt rn */
1600 { 0x4011, SETSSP | USES1 }, /* cmp/pz rn */
1601 { 0x4012, STORE | SETS1 | USES1 | USESSP }, /* sts.l macl,@-rn */
1602 { 0x4013, STORE | SETS1 | USES1 | USESSP }, /* stc.l gbr,@-rn */
1603 { 0x4015, SETSSP | USES1 }, /* cmp/pl rn */
1604 { 0x4016, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,macl */
1605 { 0x4017, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,gbr */
1606 { 0x4018, SETS1 | USES1 }, /* shll8 rn */
1607 { 0x4019, SETS1 | USES1 }, /* shlr8 rn */
1608 { 0x401a, SETSSP | USES1 }, /* lds rm,macl */
1609 { 0x401b, LOAD | SETSSP | USES1 }, /* tas.b @rn */
1610 { 0x401e, SETSSP | USES1 }, /* ldc rm,gbr */
1611 { 0x4020, SETS1 | SETSSP | USES1 }, /* shal rn */
1612 { 0x4021, SETS1 | SETSSP | USES1 }, /* shar rn */
1613 { 0x4022, STORE | SETS1 | USES1 | USESSP }, /* sts.l pr,@-rn */
1614 { 0x4023, STORE | SETS1 | USES1 | USESSP }, /* stc.l vbr,@-rn */
1615 { 0x4024, SETS1 | SETSSP | USES1 | USESSP }, /* rotcl rn */
1616 { 0x4025, SETS1 | SETSSP | USES1 | USESSP }, /* rotcr rn */
1617 { 0x4026, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,pr */
1618 { 0x4027, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,vbr */
1619 { 0x4028, SETS1 | USES1 }, /* shll16 rn */
1620 { 0x4029, SETS1 | USES1 }, /* shlr16 rn */
1621 { 0x402a, SETSSP | USES1 }, /* lds rm,pr */
1622 { 0x402b, BRANCH | DELAY | USES1 }, /* jmp @rn */
1623 { 0x402e, SETSSP | USES1 }, /* ldc rm,vbr */
1624 { 0x4033, STORE | SETS1 | USES1 | USESSP }, /* stc.l ssr,@-rn */
1625 { 0x4037, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,ssr */
1626 { 0x403e, SETSSP | USES1 }, /* ldc rm,ssr */
1627 { 0x4043, STORE | SETS1 | USES1 | USESSP }, /* stc.l spc,@-rn */
1628 { 0x4047, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,spc */
1629 { 0x404e, SETSSP | USES1 }, /* ldc rm,spc */
1630 { 0x4052, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpul,@-rn */
1631 { 0x4056, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpul */
1632 { 0x405a, SETSSP | USES1 }, /* lds.l rm,fpul */
1633 { 0x4062, STORE | SETS1 | USES1 | USESSP }, /* sts.l fpscr,@-rn */
1634 { 0x4066, LOAD | SETS1 | SETSSP | USES1 }, /* lds.l @rm+,fpscr */
1635 { 0x406a, SETSSP | USES1 } /* lds rm,fpscr */
1636 };
1637
1638 static const struct sh_opcode sh_opcode41[] =
1639 {
1640 { 0x4083, STORE | SETS1 | USES1 | USESSP }, /* stc.l rx_bank,@-rn */
1641 { 0x4087, LOAD | SETS1 | SETSSP | USES1 }, /* ldc.l @rm+,rx_bank */
1642 { 0x408e, SETSSP | USES1 } /* ldc rm,rx_bank */
1643 };
1644
1645 static const struct sh_opcode sh_opcode42[] =
1646 {
1647 { 0x400c, SETS1 | USES1 | USES2 }, /* shad rm,rn */
1648 { 0x400d, SETS1 | USES1 | USES2 }, /* shld rm,rn */
1649 { 0x400f, LOAD|SETS1|SETS2|SETSSP|USES1|USES2|USESSP }, /* mac.w @rm+,@rn+ */
1650 };
1651
1652 static const struct sh_minor_opcode sh_opcode4[] =
1653 {
1654 { MAP (sh_opcode40), 0xf0ff },
1655 { MAP (sh_opcode41), 0xf08f },
1656 { MAP (sh_opcode42), 0xf00f }
1657 };
1658
1659 static const struct sh_opcode sh_opcode50[] =
1660 {
1661 { 0x5000, LOAD | SETS1 | USES2 } /* mov.l @(disp,rm),rn */
1662 };
1663
1664 static const struct sh_minor_opcode sh_opcode5[] =
1665 {
1666 { MAP (sh_opcode50), 0xf000 }
1667 };
1668
1669 static const struct sh_opcode sh_opcode60[] =
1670 {
1671 { 0x6000, LOAD | SETS1 | USES2 }, /* mov.b @rm,rn */
1672 { 0x6001, LOAD | SETS1 | USES2 }, /* mov.w @rm,rn */
1673 { 0x6002, LOAD | SETS1 | USES2 }, /* mov.l @rm,rn */
1674 { 0x6003, SETS1 | USES2 }, /* mov rm,rn */
1675 { 0x6004, LOAD | SETS1 | SETS2 | USES2 }, /* mov.b @rm+,rn */
1676 { 0x6005, LOAD | SETS1 | SETS2 | USES2 }, /* mov.w @rm+,rn */
1677 { 0x6006, LOAD | SETS1 | SETS2 | USES2 }, /* mov.l @rm+,rn */
1678 { 0x6007, SETS1 | USES2 }, /* not rm,rn */
1679 { 0x6008, SETS1 | USES2 }, /* swap.b rm,rn */
1680 { 0x6009, SETS1 | USES2 }, /* swap.w rm,rn */
1681 { 0x600a, SETS1 | SETSSP | USES2 | USESSP }, /* negc rm,rn */
1682 { 0x600b, SETS1 | USES2 }, /* neg rm,rn */
1683 { 0x600c, SETS1 | USES2 }, /* extu.b rm,rn */
1684 { 0x600d, SETS1 | USES2 }, /* extu.w rm,rn */
1685 { 0x600e, SETS1 | USES2 }, /* exts.b rm,rn */
1686 { 0x600f, SETS1 | USES2 } /* exts.w rm,rn */
1687 };
1688
1689 static const struct sh_minor_opcode sh_opcode6[] =
1690 {
1691 { MAP (sh_opcode60), 0xf00f }
1692 };
1693
1694 static const struct sh_opcode sh_opcode70[] =
1695 {
1696 { 0x7000, SETS1 | USES1 } /* add #imm,rn */
1697 };
1698
1699 static const struct sh_minor_opcode sh_opcode7[] =
1700 {
1701 { MAP (sh_opcode70), 0xf000 }
1702 };
1703
1704 static const struct sh_opcode sh_opcode80[] =
1705 {
1706 { 0x8000, STORE | USES2 | USESR0 }, /* mov.b r0,@(disp,rn) */
1707 { 0x8100, STORE | USES2 | USESR0 }, /* mov.w r0,@(disp,rn) */
1708 { 0x8400, LOAD | SETSR0 | USES2 }, /* mov.b @(disp,rm),r0 */
1709 { 0x8500, LOAD | SETSR0 | USES2 }, /* mov.w @(disp,rn),r0 */
1710 { 0x8800, SETSSP | USESR0 }, /* cmp/eq #imm,r0 */
1711 { 0x8900, BRANCH | USESSP }, /* bt label */
1712 { 0x8b00, BRANCH | USESSP }, /* bf label */
1713 { 0x8d00, BRANCH | DELAY | USESSP }, /* bt/s label */
1714 { 0x8f00, BRANCH | DELAY | USESSP } /* bf/s label */
1715 };
1716
1717 static const struct sh_minor_opcode sh_opcode8[] =
1718 {
1719 { MAP (sh_opcode80), 0xff00 }
1720 };
1721
1722 static const struct sh_opcode sh_opcode90[] =
1723 {
1724 { 0x9000, LOAD | SETS1 } /* mov.w @(disp,pc),rn */
1725 };
1726
1727 static const struct sh_minor_opcode sh_opcode9[] =
1728 {
1729 { MAP (sh_opcode90), 0xf000 }
1730 };
1731
1732 static const struct sh_opcode sh_opcodea0[] =
1733 {
1734 { 0xa000, BRANCH | DELAY } /* bra label */
1735 };
1736
1737 static const struct sh_minor_opcode sh_opcodea[] =
1738 {
1739 { MAP (sh_opcodea0), 0xf000 }
1740 };
1741
1742 static const struct sh_opcode sh_opcodeb0[] =
1743 {
1744 { 0xb000, BRANCH | DELAY } /* bsr label */
1745 };
1746
1747 static const struct sh_minor_opcode sh_opcodeb[] =
1748 {
1749 { MAP (sh_opcodeb0), 0xf000 }
1750 };
1751
1752 static const struct sh_opcode sh_opcodec0[] =
1753 {
1754 { 0xc000, STORE | USESR0 | USESSP }, /* mov.b r0,@(disp,gbr) */
1755 { 0xc100, STORE | USESR0 | USESSP }, /* mov.w r0,@(disp,gbr) */
1756 { 0xc200, STORE | USESR0 | USESSP }, /* mov.l r0,@(disp,gbr) */
1757 { 0xc300, BRANCH | USESSP }, /* trapa #imm */
1758 { 0xc400, LOAD | SETSR0 | USESSP }, /* mov.b @(disp,gbr),r0 */
1759 { 0xc500, LOAD | SETSR0 | USESSP }, /* mov.w @(disp,gbr),r0 */
1760 { 0xc600, LOAD | SETSR0 | USESSP }, /* mov.l @(disp,gbr),r0 */
1761 { 0xc700, SETSR0 }, /* mova @(disp,pc),r0 */
1762 { 0xc800, SETSSP | USESR0 }, /* tst #imm,r0 */
1763 { 0xc900, SETSR0 | USESR0 }, /* and #imm,r0 */
1764 { 0xca00, SETSR0 | USESR0 }, /* xor #imm,r0 */
1765 { 0xcb00, SETSR0 | USESR0 }, /* or #imm,r0 */
1766 { 0xcc00, LOAD | SETSSP | USESR0 | USESSP }, /* tst.b #imm,@(r0,gbr) */
1767 { 0xcd00, LOAD | STORE | USESR0 | USESSP }, /* and.b #imm,@(r0,gbr) */
1768 { 0xce00, LOAD | STORE | USESR0 | USESSP }, /* xor.b #imm,@(r0,gbr) */
1769 { 0xcf00, LOAD | STORE | USESR0 | USESSP } /* or.b #imm,@(r0,gbr) */
1770 };
1771
1772 static const struct sh_minor_opcode sh_opcodec[] =
1773 {
1774 { MAP (sh_opcodec0), 0xff00 }
1775 };
1776
1777 static const struct sh_opcode sh_opcoded0[] =
1778 {
1779 { 0xd000, LOAD | SETS1 } /* mov.l @(disp,pc),rn */
1780 };
1781
1782 static const struct sh_minor_opcode sh_opcoded[] =
1783 {
1784 { MAP (sh_opcoded0), 0xf000 }
1785 };
1786
1787 static const struct sh_opcode sh_opcodee0[] =
1788 {
1789 { 0xe000, SETS1 } /* mov #imm,rn */
1790 };
1791
1792 static const struct sh_minor_opcode sh_opcodee[] =
1793 {
1794 { MAP (sh_opcodee0), 0xf000 }
1795 };
1796
1797 static const struct sh_opcode sh_opcodef0[] =
1798 {
1799 { 0xf000, SETSF1 | USESF1 | USESF2 }, /* fadd fm,fn */
1800 { 0xf001, SETSF1 | USESF1 | USESF2 }, /* fsub fm,fn */
1801 { 0xf002, SETSF1 | USESF1 | USESF2 }, /* fmul fm,fn */
1802 { 0xf003, SETSF1 | USESF1 | USESF2 }, /* fdiv fm,fn */
1803 { 0xf004, SETSSP | USESF1 | USESF2 }, /* fcmp/eq fm,fn */
1804 { 0xf005, SETSSP | USESF1 | USESF2 }, /* fcmp/gt fm,fn */
1805 { 0xf006, LOAD | SETSF1 | USES2 | USESR0 }, /* fmov.s @(r0,rm),fn */
1806 { 0xf007, STORE | USES1 | USESF2 | USESR0 }, /* fmov.s fm,@(r0,rn) */
1807 { 0xf008, LOAD | SETSF1 | USES2 }, /* fmov.s @rm,fn */
1808 { 0xf009, LOAD | SETS2 | SETSF1 | USES2 }, /* fmov.s @rm+,fn */
1809 { 0xf00a, STORE | USES1 | USESF2 }, /* fmov.s fm,@rn */
1810 { 0xf00b, STORE | SETS1 | USES1 | USESF2 }, /* fmov.s fm,@-rn */
1811 { 0xf00c, SETSF1 | USESF2 }, /* fmov fm,fn */
1812 { 0xf00e, SETSF1 | USESF1 | USESF2 | USESF0 } /* fmac f0,fm,fn */
1813 };
1814
1815 static const struct sh_opcode sh_opcodef1[] =
1816 {
1817 { 0xf00d, SETSF1 | USESSP }, /* fsts fpul,fn */
1818 { 0xf01d, SETSSP | USESF1 }, /* flds fn,fpul */
1819 { 0xf02d, SETSF1 | USESSP }, /* float fpul,fn */
1820 { 0xf03d, SETSSP | USESF1 }, /* ftrc fn,fpul */
1821 { 0xf04d, SETSF1 | USESF1 }, /* fneg fn */
1822 { 0xf05d, SETSF1 | USESF1 }, /* fabs fn */
1823 { 0xf06d, SETSF1 | USESF1 }, /* fsqrt fn */
1824 { 0xf07d, SETSSP | USESF1 }, /* ftst/nan fn */
1825 { 0xf08d, SETSF1 }, /* fldi0 fn */
1826 { 0xf09d, SETSF1 } /* fldi1 fn */
1827 };
1828
1829 static const struct sh_minor_opcode sh_opcodef[] =
1830 {
1831 { MAP (sh_opcodef0), 0xf00f },
1832 { MAP (sh_opcodef1), 0xf0ff }
1833 };
1834
1835 static const struct sh_major_opcode sh_opcodes[] =
1836 {
1837 { MAP (sh_opcode0) },
1838 { MAP (sh_opcode1) },
1839 { MAP (sh_opcode2) },
1840 { MAP (sh_opcode3) },
1841 { MAP (sh_opcode4) },
1842 { MAP (sh_opcode5) },
1843 { MAP (sh_opcode6) },
1844 { MAP (sh_opcode7) },
1845 { MAP (sh_opcode8) },
1846 { MAP (sh_opcode9) },
1847 { MAP (sh_opcodea) },
1848 { MAP (sh_opcodeb) },
1849 { MAP (sh_opcodec) },
1850 { MAP (sh_opcoded) },
1851 { MAP (sh_opcodee) },
1852 { MAP (sh_opcodef) }
1853 };
1854
1855 /* Given an instruction, return a pointer to the corresponding
1856 sh_opcode structure. Return NULL if the instruction is not
1857 recognized. */
1858
1859 static const struct sh_opcode *
1860 sh_insn_info (insn)
1861 unsigned int insn;
1862 {
1863 const struct sh_major_opcode *maj;
1864 const struct sh_minor_opcode *min, *minend;
1865
1866 maj = &sh_opcodes[(insn & 0xf000) >> 12];
1867 min = maj->minor_opcodes;
1868 minend = min + maj->count;
1869 for (; min < minend; min++)
1870 {
1871 unsigned int l;
1872 const struct sh_opcode *op, *opend;
1873
1874 l = insn & min->mask;
1875 op = min->opcodes;
1876 opend = op + min->count;
1877
1878 /* Since the opcodes tables are sorted, we could use a binary
1879 search here if the count were above some cutoff value. */
1880 for (; op < opend; op++)
1881 if (op->opcode == l)
1882 return op;
1883 }
1884
1885 return NULL;
1886 }
1887
1888 /* See whether an instruction uses a general purpose register. */
1889
1890 static boolean
1891 sh_insn_uses_reg (insn, op, reg)
1892 unsigned int insn;
1893 const struct sh_opcode *op;
1894 unsigned int reg;
1895 {
1896 unsigned int f;
1897
1898 f = op->flags;
1899
1900 if ((f & USES1) != 0
1901 && ((insn & 0x0f00) >> 8) == reg)
1902 return true;
1903 if ((f & USES2) != 0
1904 && ((insn & 0x00f0) >> 4) == reg)
1905 return true;
1906 if ((f & USESR0) != 0
1907 && reg == 0)
1908 return true;
1909
1910 return false;
1911 }
1912
1913 /* See whether an instruction uses a floating point register. */
1914
1915 static boolean
1916 sh_insn_uses_freg (insn, op, freg)
1917 unsigned int insn;
1918 const struct sh_opcode *op;
1919 unsigned int freg;
1920 {
1921 unsigned int f;
1922
1923 f = op->flags;
1924
1925 if ((f & USESF1) != 0
1926 && ((insn & 0x0f00) >> 8) == freg)
1927 return true;
1928 if ((f & USESF2) != 0
1929 && ((insn & 0x00f0) >> 4) == freg)
1930 return true;
1931 if ((f & USESF0) != 0
1932 && freg == 0)
1933 return true;
1934
1935 return false;
1936 }
1937
1938 /* See whether instructions I1 and I2 conflict, assuming I1 comes
1939 before I2. OP1 and OP2 are the corresponding sh_opcode structures.
1940 This should return true if there is a conflict, or false if the
1941 instructions can be swapped safely. */
1942
1943 static boolean
1944 sh_insns_conflict (i1, op1, i2, op2)
1945 unsigned int i1;
1946 const struct sh_opcode *op1;
1947 unsigned int i2;
1948 const struct sh_opcode *op2;
1949 {
1950 unsigned int f1, f2;
1951
1952 f1 = op1->flags;
1953 f2 = op2->flags;
1954
1955 if ((f1 & (BRANCH | DELAY)) != 0
1956 || (f2 & (BRANCH | DELAY)) != 0)
1957 return true;
1958
1959 if ((f1 & SETSSP) != 0 && (f2 & USESSP) != 0)
1960 return true;
1961 if ((f2 & SETSSP) != 0 && (f1 & USESSP) != 0)
1962 return true;
1963
1964 if ((f1 & SETS1) != 0
1965 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
1966 return true;
1967 if ((f1 & SETS2) != 0
1968 && sh_insn_uses_reg (i2, op2, (i1 & 0x00f0) >> 4))
1969 return true;
1970 if ((f1 & SETSR0) != 0
1971 && sh_insn_uses_reg (i2, op2, 0))
1972 return true;
1973 if ((f1 & SETSF1) != 0
1974 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
1975 return true;
1976
1977 if ((f2 & SETS1) != 0
1978 && sh_insn_uses_reg (i1, op1, (i2 & 0x0f00) >> 8))
1979 return true;
1980 if ((f2 & SETS2) != 0
1981 && sh_insn_uses_reg (i1, op1, (i2 & 0x00f0) >> 4))
1982 return true;
1983 if ((f2 & SETSR0) != 0
1984 && sh_insn_uses_reg (i1, op1, 0))
1985 return true;
1986 if ((f2 & SETSF1) != 0
1987 && sh_insn_uses_freg (i1, op1, (i2 & 0x0f00) >> 8))
1988 return true;
1989
1990 /* The instructions do not conflict. */
1991 return false;
1992 }
1993
1994 /* I1 is a load instruction, and I2 is some other instruction. Return
1995 true if I1 loads a register which I2 uses. */
1996
1997 static boolean
1998 sh_load_use (i1, op1, i2, op2)
1999 unsigned int i1;
2000 const struct sh_opcode *op1;
2001 unsigned int i2;
2002 const struct sh_opcode *op2;
2003 {
2004 unsigned int f1;
2005
2006 f1 = op1->flags;
2007
2008 if ((f1 & LOAD) == 0)
2009 return false;
2010
2011 /* If both SETS1 and SETSSP are set, that means a load to a special
2012 register using postincrement addressing mode, which we don't care
2013 about here. */
2014 if ((f1 & SETS1) != 0
2015 && (f1 & SETSSP) == 0
2016 && sh_insn_uses_reg (i2, op2, (i1 & 0x0f00) >> 8))
2017 return true;
2018
2019 if ((f1 & SETSR0) != 0
2020 && sh_insn_uses_reg (i2, op2, 0))
2021 return true;
2022
2023 if ((f1 & SETSF1) != 0
2024 && sh_insn_uses_freg (i2, op2, (i1 & 0x0f00) >> 8))
2025 return true;
2026
2027 return false;
2028 }
2029
2030 /* Try to align loads and stores within a span of memory. This is
2031 called by both the ELF and the COFF sh targets. ABFD and SEC are
2032 the BFD and section we are examining. CONTENTS is the contents of
2033 the section. SWAP is the routine to call to swap two instructions.
2034 RELOCS is a pointer to the internal relocation information, to be
2035 passed to SWAP. PLABEL is a pointer to the current label in a
2036 sorted list of labels; LABEL_END is the end of the list. START and
2037 STOP are the range of memory to examine. If a swap is made,
2038 *PSWAPPED is set to true. */
2039
2040 boolean
2041 _bfd_sh_align_load_span (abfd, sec, contents, swap, relocs,
2042 plabel, label_end, start, stop, pswapped)
2043 bfd *abfd;
2044 asection *sec;
2045 bfd_byte *contents;
2046 boolean (*swap) PARAMS ((bfd *, asection *, PTR, bfd_byte *, bfd_vma));
2047 PTR relocs;
2048 bfd_vma **plabel;
2049 bfd_vma *label_end;
2050 bfd_vma start;
2051 bfd_vma stop;
2052 boolean *pswapped;
2053 {
2054 bfd_vma i;
2055
2056 /* Instructions should be aligned on 2 byte boundaries. */
2057 if ((start & 1) == 1)
2058 ++start;
2059
2060 /* Now look through the unaligned addresses. */
2061 i = start;
2062 if ((i & 2) == 0)
2063 i += 2;
2064 for (; i < stop; i += 4)
2065 {
2066 unsigned int insn;
2067 const struct sh_opcode *op;
2068 unsigned int prev_insn = 0;
2069 const struct sh_opcode *prev_op = NULL;
2070
2071 insn = bfd_get_16 (abfd, contents + i);
2072 op = sh_insn_info (insn);
2073 if (op == NULL
2074 || (op->flags & (LOAD | STORE)) == 0)
2075 continue;
2076
2077 /* This is a load or store which is not on a four byte boundary. */
2078
2079 while (*plabel < label_end && **plabel < i)
2080 ++*plabel;
2081
2082 if (i > start)
2083 {
2084 prev_insn = bfd_get_16 (abfd, contents + i - 2);
2085 prev_op = sh_insn_info (prev_insn);
2086
2087 /* If the load/store instruction is in a delay slot, we
2088 can't swap. */
2089 if (prev_op == NULL
2090 || (prev_op->flags & DELAY) != 0)
2091 continue;
2092 }
2093 if (i > start
2094 && (*plabel >= label_end || **plabel != i)
2095 && prev_op != NULL
2096 && (prev_op->flags & (LOAD | STORE)) == 0
2097 && ! sh_insns_conflict (prev_insn, prev_op, insn, op))
2098 {
2099 boolean ok;
2100
2101 /* The load/store instruction does not have a label, and
2102 there is a previous instruction; PREV_INSN is not
2103 itself a load/store instruction, and PREV_INSN and
2104 INSN do not conflict. */
2105
2106 ok = true;
2107
2108 if (i >= start + 4)
2109 {
2110 unsigned int prev2_insn;
2111 const struct sh_opcode *prev2_op;
2112
2113 prev2_insn = bfd_get_16 (abfd, contents + i - 4);
2114 prev2_op = sh_insn_info (prev2_insn);
2115
2116 /* If the instruction before PREV_INSN has a delay
2117 slot--that is, PREV_INSN is in a delay slot--we
2118 can not swap. */
2119 if (prev2_op == NULL
2120 || (prev2_op->flags & DELAY) != 0)
2121 ok = false;
2122
2123 /* If the instruction before PREV_INSN is a load,
2124 and it sets a register which INSN uses, then
2125 putting INSN immediately after PREV_INSN will
2126 cause a pipeline bubble, so there is no point to
2127 making the swap. */
2128 if (ok
2129 && (prev2_op->flags & LOAD) != 0
2130 && sh_load_use (prev2_insn, prev2_op, insn, op))
2131 ok = false;
2132 }
2133
2134 if (ok)
2135 {
2136 if (! (*swap) (abfd, sec, relocs, contents, i - 2))
2137 return false;
2138 *pswapped = true;
2139 continue;
2140 }
2141 }
2142
2143 while (*plabel < label_end && **plabel < i + 2)
2144 ++*plabel;
2145
2146 if (i + 2 < stop
2147 && (*plabel >= label_end || **plabel != i + 2))
2148 {
2149 unsigned int next_insn;
2150 const struct sh_opcode *next_op;
2151
2152 /* There is an instruction after the load/store
2153 instruction, and it does not have a label. */
2154 next_insn = bfd_get_16 (abfd, contents + i + 2);
2155 next_op = sh_insn_info (next_insn);
2156 if (next_op != NULL
2157 && (next_op->flags & (LOAD | STORE)) == 0
2158 && ! sh_insns_conflict (insn, op, next_insn, next_op))
2159 {
2160 boolean ok;
2161
2162 /* NEXT_INSN is not itself a load/store instruction,
2163 and it does not conflict with INSN. */
2164
2165 ok = true;
2166
2167 /* If PREV_INSN is a load, and it sets a register
2168 which NEXT_INSN uses, then putting NEXT_INSN
2169 immediately after PREV_INSN will cause a pipeline
2170 bubble, so there is no reason to make this swap. */
2171 if (prev_op != NULL
2172 && (prev_op->flags & LOAD) != 0
2173 && sh_load_use (prev_insn, prev_op, next_insn, next_op))
2174 ok = false;
2175
2176 /* If INSN is a load, and it sets a register which
2177 the insn after NEXT_INSN uses, then doing the
2178 swap will cause a pipeline bubble, so there is no
2179 reason to make the swap. However, if the insn
2180 after NEXT_INSN is itself a load or store
2181 instruction, then it is misaligned, so
2182 optimistically hope that it will be swapped
2183 itself, and just live with the pipeline bubble if
2184 it isn't. */
2185 if (ok
2186 && i + 4 < stop
2187 && (op->flags & LOAD) != 0)
2188 {
2189 unsigned int next2_insn;
2190 const struct sh_opcode *next2_op;
2191
2192 next2_insn = bfd_get_16 (abfd, contents + i + 4);
2193 next2_op = sh_insn_info (next2_insn);
2194 if ((next2_op->flags & (LOAD | STORE)) == 0
2195 && sh_load_use (insn, op, next2_insn, next2_op))
2196 ok = false;
2197 }
2198
2199 if (ok)
2200 {
2201 if (! (*swap) (abfd, sec, relocs, contents, i))
2202 return false;
2203 *pswapped = true;
2204 continue;
2205 }
2206 }
2207 }
2208 }
2209
2210 return true;
2211 }
2212
2213 /* Look for loads and stores which we can align to four byte
2214 boundaries. See the longer comment above sh_relax_section for why
2215 this is desirable. This sets *PSWAPPED if some instruction was
2216 swapped. */
2217
2218 static boolean
2219 sh_align_loads (abfd, sec, internal_relocs, contents, pswapped)
2220 bfd *abfd;
2221 asection *sec;
2222 struct internal_reloc *internal_relocs;
2223 bfd_byte *contents;
2224 boolean *pswapped;
2225 {
2226 struct internal_reloc *irel, *irelend;
2227 bfd_vma *labels = NULL;
2228 bfd_vma *label, *label_end;
2229
2230 *pswapped = false;
2231
2232 irelend = internal_relocs + sec->reloc_count;
2233
2234 /* Get all the addresses with labels on them. */
2235 labels = (bfd_vma *) bfd_malloc (sec->reloc_count * sizeof (bfd_vma));
2236 if (labels == NULL)
2237 goto error_return;
2238 label_end = labels;
2239 for (irel = internal_relocs; irel < irelend; irel++)
2240 {
2241 if (irel->r_type == R_SH_LABEL)
2242 {
2243 *label_end = irel->r_vaddr - sec->vma;
2244 ++label_end;
2245 }
2246 }
2247
2248 /* Note that the assembler currently always outputs relocs in
2249 address order. If that ever changes, this code will need to sort
2250 the label values and the relocs. */
2251
2252 label = labels;
2253
2254 for (irel = internal_relocs; irel < irelend; irel++)
2255 {
2256 bfd_vma start, stop;
2257
2258 if (irel->r_type != R_SH_CODE)
2259 continue;
2260
2261 start = irel->r_vaddr - sec->vma;
2262
2263 for (irel++; irel < irelend; irel++)
2264 if (irel->r_type == R_SH_DATA)
2265 break;
2266 if (irel < irelend)
2267 stop = irel->r_vaddr - sec->vma;
2268 else
2269 stop = sec->_cooked_size;
2270
2271 if (! _bfd_sh_align_load_span (abfd, sec, contents, sh_swap_insns,
2272 (PTR) internal_relocs, &label,
2273 label_end, start, stop, pswapped))
2274 goto error_return;
2275 }
2276
2277 free (labels);
2278
2279 return true;
2280
2281 error_return:
2282 if (labels != NULL)
2283 free (labels);
2284 return false;
2285 }
2286
2287 /* Swap two SH instructions. */
2288
2289 static boolean
2290 sh_swap_insns (abfd, sec, relocs, contents, addr)
2291 bfd *abfd;
2292 asection *sec;
2293 PTR relocs;
2294 bfd_byte *contents;
2295 bfd_vma addr;
2296 {
2297 struct internal_reloc *internal_relocs = (struct internal_reloc *) relocs;
2298 unsigned short i1, i2;
2299 struct internal_reloc *irel, *irelend;
2300
2301 /* Swap the instructions themselves. */
2302 i1 = bfd_get_16 (abfd, contents + addr);
2303 i2 = bfd_get_16 (abfd, contents + addr + 2);
2304 bfd_put_16 (abfd, i2, contents + addr);
2305 bfd_put_16 (abfd, i1, contents + addr + 2);
2306
2307 /* Adjust all reloc addresses. */
2308 irelend = internal_relocs + sec->reloc_count;
2309 for (irel = internal_relocs; irel < irelend; irel++)
2310 {
2311 int type, add;
2312
2313 /* There are a few special types of relocs that we don't want to
2314 adjust. These relocs do not apply to the instruction itself,
2315 but are only associated with the address. */
2316 type = irel->r_type;
2317 if (type == R_SH_ALIGN
2318 || type == R_SH_CODE
2319 || type == R_SH_DATA
2320 || type == R_SH_LABEL)
2321 continue;
2322
2323 /* If an R_SH_USES reloc points to one of the addresses being
2324 swapped, we must adjust it. It would be incorrect to do this
2325 for a jump, though, since we want to execute both
2326 instructions after the jump. (We have avoided swapping
2327 around a label, so the jump will not wind up executing an
2328 instruction it shouldn't). */
2329 if (type == R_SH_USES)
2330 {
2331 bfd_vma off;
2332
2333 off = irel->r_vaddr - sec->vma + 4 + irel->r_offset;
2334 if (off == addr)
2335 irel->r_offset += 2;
2336 else if (off == addr + 2)
2337 irel->r_offset -= 2;
2338 }
2339
2340 if (irel->r_vaddr - sec->vma == addr)
2341 {
2342 irel->r_vaddr += 2;
2343 add = -2;
2344 }
2345 else if (irel->r_vaddr - sec->vma == addr + 2)
2346 {
2347 irel->r_vaddr -= 2;
2348 add = 2;
2349 }
2350 else
2351 add = 0;
2352
2353 if (add != 0)
2354 {
2355 bfd_byte *loc;
2356 unsigned short insn, oinsn;
2357 boolean overflow;
2358
2359 loc = contents + irel->r_vaddr - sec->vma;
2360 overflow = false;
2361 switch (type)
2362 {
2363 default:
2364 break;
2365
2366 case R_SH_PCDISP8BY2:
2367 case R_SH_PCRELIMM8BY2:
2368 insn = bfd_get_16 (abfd, loc);
2369 oinsn = insn;
2370 insn += add / 2;
2371 if ((oinsn & 0xff00) != (insn & 0xff00))
2372 overflow = true;
2373 bfd_put_16 (abfd, insn, loc);
2374 break;
2375
2376 case R_SH_PCDISP:
2377 insn = bfd_get_16 (abfd, loc);
2378 oinsn = insn;
2379 insn += add / 2;
2380 if ((oinsn & 0xf000) != (insn & 0xf000))
2381 overflow = true;
2382 bfd_put_16 (abfd, insn, loc);
2383 break;
2384
2385 case R_SH_PCRELIMM8BY4:
2386 /* This reloc ignores the least significant 3 bits of
2387 the program counter before adding in the offset.
2388 This means that if ADDR is at an even address, the
2389 swap will not affect the offset. If ADDR is an at an
2390 odd address, then the instruction will be crossing a
2391 four byte boundary, and must be adjusted. */
2392 if ((addr & 3) != 0)
2393 {
2394 insn = bfd_get_16 (abfd, loc);
2395 oinsn = insn;
2396 insn += add / 2;
2397 if ((oinsn & 0xff00) != (insn & 0xff00))
2398 overflow = true;
2399 bfd_put_16 (abfd, insn, loc);
2400 }
2401
2402 break;
2403 }
2404
2405 if (overflow)
2406 {
2407 ((*_bfd_error_handler)
2408 ("%s: 0x%lx: fatal: reloc overflow while relaxing",
2409 bfd_get_filename (abfd), (unsigned long) irel->r_vaddr));
2410 bfd_set_error (bfd_error_bad_value);
2411 return false;
2412 }
2413 }
2414 }
2415
2416 return true;
2417 }
2418 \f
2419 /* This is a modification of _bfd_coff_generic_relocate_section, which
2420 will handle SH relaxing. */
2421
2422 static boolean
2423 sh_relocate_section (output_bfd, info, input_bfd, input_section, contents,
2424 relocs, syms, sections)
2425 bfd *output_bfd;
2426 struct bfd_link_info *info;
2427 bfd *input_bfd;
2428 asection *input_section;
2429 bfd_byte *contents;
2430 struct internal_reloc *relocs;
2431 struct internal_syment *syms;
2432 asection **sections;
2433 {
2434 struct internal_reloc *rel;
2435 struct internal_reloc *relend;
2436
2437 rel = relocs;
2438 relend = rel + input_section->reloc_count;
2439 for (; rel < relend; rel++)
2440 {
2441 long symndx;
2442 struct coff_link_hash_entry *h;
2443 struct internal_syment *sym;
2444 bfd_vma addend;
2445 bfd_vma val;
2446 reloc_howto_type *howto;
2447 bfd_reloc_status_type rstat;
2448
2449 /* Almost all relocs have to do with relaxing. If any work must
2450 be done for them, it has been done in sh_relax_section. */
2451 if (rel->r_type != R_SH_IMM32
2452 && rel->r_type != R_SH_PCDISP)
2453 continue;
2454
2455 symndx = rel->r_symndx;
2456
2457 if (symndx == -1)
2458 {
2459 h = NULL;
2460 sym = NULL;
2461 }
2462 else
2463 {
2464 if (symndx < 0
2465 || (unsigned long) symndx >= obj_raw_syment_count (input_bfd))
2466 {
2467 (*_bfd_error_handler)
2468 ("%s: illegal symbol index %ld in relocs",
2469 bfd_get_filename (input_bfd), symndx);
2470 bfd_set_error (bfd_error_bad_value);
2471 return false;
2472 }
2473 h = obj_coff_sym_hashes (input_bfd)[symndx];
2474 sym = syms + symndx;
2475 }
2476
2477 if (sym != NULL && sym->n_scnum != 0)
2478 addend = - sym->n_value;
2479 else
2480 addend = 0;
2481
2482 if (rel->r_type == R_SH_PCDISP)
2483 addend -= 4;
2484
2485 if (rel->r_type >= SH_COFF_HOWTO_COUNT)
2486 howto = NULL;
2487 else
2488 howto = &sh_coff_howtos[rel->r_type];
2489
2490 if (howto == NULL)
2491 {
2492 bfd_set_error (bfd_error_bad_value);
2493 return false;
2494 }
2495
2496 val = 0;
2497
2498 if (h == NULL)
2499 {
2500 asection *sec;
2501
2502 /* There is nothing to do for an internal PCDISP reloc. */
2503 if (rel->r_type == R_SH_PCDISP)
2504 continue;
2505
2506 if (symndx == -1)
2507 {
2508 sec = bfd_abs_section_ptr;
2509 val = 0;
2510 }
2511 else
2512 {
2513 sec = sections[symndx];
2514 val = (sec->output_section->vma
2515 + sec->output_offset
2516 + sym->n_value
2517 - sec->vma);
2518 }
2519 }
2520 else
2521 {
2522 if (h->root.type == bfd_link_hash_defined
2523 || h->root.type == bfd_link_hash_defweak)
2524 {
2525 asection *sec;
2526
2527 sec = h->root.u.def.section;
2528 val = (h->root.u.def.value
2529 + sec->output_section->vma
2530 + sec->output_offset);
2531 }
2532 else if (! info->relocateable)
2533 {
2534 if (! ((*info->callbacks->undefined_symbol)
2535 (info, h->root.root.string, input_bfd, input_section,
2536 rel->r_vaddr - input_section->vma)))
2537 return false;
2538 }
2539 }
2540
2541 rstat = _bfd_final_link_relocate (howto, input_bfd, input_section,
2542 contents,
2543 rel->r_vaddr - input_section->vma,
2544 val, addend);
2545
2546 switch (rstat)
2547 {
2548 default:
2549 abort ();
2550 case bfd_reloc_ok:
2551 break;
2552 case bfd_reloc_overflow:
2553 {
2554 const char *name;
2555 char buf[SYMNMLEN + 1];
2556
2557 if (symndx == -1)
2558 name = "*ABS*";
2559 else if (h != NULL)
2560 name = h->root.root.string;
2561 else if (sym->_n._n_n._n_zeroes == 0
2562 && sym->_n._n_n._n_offset != 0)
2563 name = obj_coff_strings (input_bfd) + sym->_n._n_n._n_offset;
2564 else
2565 {
2566 strncpy (buf, sym->_n._n_name, SYMNMLEN);
2567 buf[SYMNMLEN] = '\0';
2568 name = buf;
2569 }
2570
2571 if (! ((*info->callbacks->reloc_overflow)
2572 (info, name, howto->name, (bfd_vma) 0, input_bfd,
2573 input_section, rel->r_vaddr - input_section->vma)))
2574 return false;
2575 }
2576 }
2577 }
2578
2579 return true;
2580 }
2581
2582 /* This is a version of bfd_generic_get_relocated_section_contents
2583 which uses sh_relocate_section. */
2584
2585 static bfd_byte *
2586 sh_coff_get_relocated_section_contents (output_bfd, link_info, link_order,
2587 data, relocateable, symbols)
2588 bfd *output_bfd;
2589 struct bfd_link_info *link_info;
2590 struct bfd_link_order *link_order;
2591 bfd_byte *data;
2592 boolean relocateable;
2593 asymbol **symbols;
2594 {
2595 asection *input_section = link_order->u.indirect.section;
2596 bfd *input_bfd = input_section->owner;
2597 asection **sections = NULL;
2598 struct internal_reloc *internal_relocs = NULL;
2599 struct internal_syment *internal_syms = NULL;
2600
2601 /* We only need to handle the case of relaxing, or of having a
2602 particular set of section contents, specially. */
2603 if (relocateable
2604 || coff_section_data (input_bfd, input_section) == NULL
2605 || coff_section_data (input_bfd, input_section)->contents == NULL)
2606 return bfd_generic_get_relocated_section_contents (output_bfd, link_info,
2607 link_order, data,
2608 relocateable,
2609 symbols);
2610
2611 memcpy (data, coff_section_data (input_bfd, input_section)->contents,
2612 input_section->_raw_size);
2613
2614 if ((input_section->flags & SEC_RELOC) != 0
2615 && input_section->reloc_count > 0)
2616 {
2617 bfd_size_type symesz = bfd_coff_symesz (input_bfd);
2618 bfd_byte *esym, *esymend;
2619 struct internal_syment *isymp;
2620 asection **secpp;
2621
2622 if (! _bfd_coff_get_external_symbols (input_bfd))
2623 goto error_return;
2624
2625 internal_relocs = (_bfd_coff_read_internal_relocs
2626 (input_bfd, input_section, false, (bfd_byte *) NULL,
2627 false, (struct internal_reloc *) NULL));
2628 if (internal_relocs == NULL)
2629 goto error_return;
2630
2631 internal_syms = ((struct internal_syment *)
2632 bfd_malloc (obj_raw_syment_count (input_bfd)
2633 * sizeof (struct internal_syment)));
2634 if (internal_syms == NULL)
2635 goto error_return;
2636
2637 sections = (asection **) bfd_malloc (obj_raw_syment_count (input_bfd)
2638 * sizeof (asection *));
2639 if (sections == NULL)
2640 goto error_return;
2641
2642 isymp = internal_syms;
2643 secpp = sections;
2644 esym = (bfd_byte *) obj_coff_external_syms (input_bfd);
2645 esymend = esym + obj_raw_syment_count (input_bfd) * symesz;
2646 while (esym < esymend)
2647 {
2648 bfd_coff_swap_sym_in (input_bfd, (PTR) esym, (PTR) isymp);
2649
2650 if (isymp->n_scnum != 0)
2651 *secpp = coff_section_from_bfd_index (input_bfd, isymp->n_scnum);
2652 else
2653 {
2654 if (isymp->n_value == 0)
2655 *secpp = bfd_und_section_ptr;
2656 else
2657 *secpp = bfd_com_section_ptr;
2658 }
2659
2660 esym += (isymp->n_numaux + 1) * symesz;
2661 secpp += isymp->n_numaux + 1;
2662 isymp += isymp->n_numaux + 1;
2663 }
2664
2665 if (! sh_relocate_section (output_bfd, link_info, input_bfd,
2666 input_section, data, internal_relocs,
2667 internal_syms, sections))
2668 goto error_return;
2669
2670 free (sections);
2671 sections = NULL;
2672 free (internal_syms);
2673 internal_syms = NULL;
2674 free (internal_relocs);
2675 internal_relocs = NULL;
2676 }
2677
2678 return data;
2679
2680 error_return:
2681 if (internal_relocs != NULL)
2682 free (internal_relocs);
2683 if (internal_syms != NULL)
2684 free (internal_syms);
2685 if (sections != NULL)
2686 free (sections);
2687 return NULL;
2688 }
2689
2690 /* The target vectors. */
2691
2692 const bfd_target shcoff_vec =
2693 {
2694 "coff-sh", /* name */
2695 bfd_target_coff_flavour,
2696 BFD_ENDIAN_BIG, /* data byte order is big */
2697 BFD_ENDIAN_BIG, /* header byte order is big */
2698
2699 (HAS_RELOC | EXEC_P | /* object flags */
2700 HAS_LINENO | HAS_DEBUG |
2701 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
2702
2703 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
2704 '_', /* leading symbol underscore */
2705 '/', /* ar_pad_char */
2706 15, /* ar_max_namelen */
2707 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
2708 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
2709 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
2710 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
2711 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
2712 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
2713
2714 {_bfd_dummy_target, coff_object_p, /* bfd_check_format */
2715 bfd_generic_archive_p, _bfd_dummy_target},
2716 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
2717 bfd_false},
2718 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
2719 _bfd_write_archive_contents, bfd_false},
2720
2721 BFD_JUMP_TABLE_GENERIC (coff),
2722 BFD_JUMP_TABLE_COPY (coff),
2723 BFD_JUMP_TABLE_CORE (_bfd_nocore),
2724 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
2725 BFD_JUMP_TABLE_SYMBOLS (coff),
2726 BFD_JUMP_TABLE_RELOCS (coff),
2727 BFD_JUMP_TABLE_WRITE (coff),
2728 BFD_JUMP_TABLE_LINK (coff),
2729 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
2730
2731 COFF_SWAP_TABLE,
2732 };
2733
2734 const bfd_target shlcoff_vec =
2735 {
2736 "coff-shl", /* name */
2737 bfd_target_coff_flavour,
2738 BFD_ENDIAN_LITTLE, /* data byte order is little */
2739 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
2740
2741 (HAS_RELOC | EXEC_P | /* object flags */
2742 HAS_LINENO | HAS_DEBUG |
2743 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
2744
2745 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
2746 '_', /* leading symbol underscore */
2747 '/', /* ar_pad_char */
2748 15, /* ar_max_namelen */
2749 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
2750 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
2751 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
2752 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
2753 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
2754 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
2755
2756 {_bfd_dummy_target, coff_object_p, /* bfd_check_format */
2757 bfd_generic_archive_p, _bfd_dummy_target},
2758 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
2759 bfd_false},
2760 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
2761 _bfd_write_archive_contents, bfd_false},
2762
2763 BFD_JUMP_TABLE_GENERIC (coff),
2764 BFD_JUMP_TABLE_COPY (coff),
2765 BFD_JUMP_TABLE_CORE (_bfd_nocore),
2766 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
2767 BFD_JUMP_TABLE_SYMBOLS (coff),
2768 BFD_JUMP_TABLE_RELOCS (coff),
2769 BFD_JUMP_TABLE_WRITE (coff),
2770 BFD_JUMP_TABLE_LINK (coff),
2771 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
2772
2773 COFF_SWAP_TABLE,
2774 };
2775
2776 /* Some people want versions of the SH COFF target which do not align
2777 to 16 byte boundaries. We implement that by adding a couple of new
2778 target vectors. These are just like the ones above, but they
2779 change the default section alignment. To generate them in the
2780 assembler, use -small. To use them in the linker, use -b
2781 coff-sh{l}-small and -oformat coff-sh{l}-small.
2782
2783 Yes, this is a horrible hack. A general solution for setting
2784 section alignment in COFF is rather complex. ELF handles this
2785 correctly. */
2786
2787 /* Only recognize the small versions if the target was not defaulted.
2788 Otherwise we won't recognize the non default endianness. */
2789
2790 static const bfd_target *
2791 coff_small_object_p (abfd)
2792 bfd *abfd;
2793 {
2794 if (abfd->target_defaulted)
2795 {
2796 bfd_set_error (bfd_error_wrong_format);
2797 return NULL;
2798 }
2799 return coff_object_p (abfd);
2800 }
2801
2802 /* Set the section alignment for the small versions. */
2803
2804 static boolean
2805 coff_small_new_section_hook (abfd, section)
2806 bfd *abfd;
2807 asection *section;
2808 {
2809 if (! coff_new_section_hook (abfd, section))
2810 return false;
2811
2812 /* We must align to at least a four byte boundary, because longword
2813 accesses must be on a four byte boundary. */
2814 if (section->alignment_power == COFF_DEFAULT_SECTION_ALIGNMENT_POWER)
2815 section->alignment_power = 2;
2816
2817 return true;
2818 }
2819
2820 /* This is copied from bfd_coff_std_swap_table so that we can change
2821 the default section alignment power. */
2822
2823 static const bfd_coff_backend_data bfd_coff_small_swap_table =
2824 {
2825 coff_swap_aux_in, coff_swap_sym_in, coff_swap_lineno_in,
2826 coff_swap_aux_out, coff_swap_sym_out,
2827 coff_swap_lineno_out, coff_swap_reloc_out,
2828 coff_swap_filehdr_out, coff_swap_aouthdr_out,
2829 coff_swap_scnhdr_out,
2830 FILHSZ, AOUTSZ, SCNHSZ, SYMESZ, AUXESZ, RELSZ, LINESZ,
2831 #ifdef COFF_LONG_FILENAMES
2832 true,
2833 #else
2834 false,
2835 #endif
2836 #ifdef COFF_LONG_SECTION_NAMES
2837 true,
2838 #else
2839 false,
2840 #endif
2841 2,
2842 coff_swap_filehdr_in, coff_swap_aouthdr_in, coff_swap_scnhdr_in,
2843 coff_swap_reloc_in, coff_bad_format_hook, coff_set_arch_mach_hook,
2844 coff_mkobject_hook, styp_to_sec_flags, coff_set_alignment_hook,
2845 coff_slurp_symbol_table, symname_in_debug_hook, coff_pointerize_aux_hook,
2846 coff_print_aux, coff_reloc16_extra_cases, coff_reloc16_estimate,
2847 coff_sym_is_global, coff_compute_section_file_positions,
2848 coff_start_final_link, coff_relocate_section, coff_rtype_to_howto,
2849 coff_adjust_symndx, coff_link_add_one_symbol,
2850 coff_link_output_has_begun, coff_final_link_postscript
2851 };
2852
2853 #define coff_small_close_and_cleanup \
2854 coff_close_and_cleanup
2855 #define coff_small_bfd_free_cached_info \
2856 coff_bfd_free_cached_info
2857 #define coff_small_get_section_contents \
2858 coff_get_section_contents
2859 #define coff_small_get_section_contents_in_window \
2860 coff_get_section_contents_in_window
2861
2862 const bfd_target shcoff_small_vec =
2863 {
2864 "coff-sh-small", /* name */
2865 bfd_target_coff_flavour,
2866 BFD_ENDIAN_BIG, /* data byte order is big */
2867 BFD_ENDIAN_BIG, /* header byte order is big */
2868
2869 (HAS_RELOC | EXEC_P | /* object flags */
2870 HAS_LINENO | HAS_DEBUG |
2871 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
2872
2873 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
2874 '_', /* leading symbol underscore */
2875 '/', /* ar_pad_char */
2876 15, /* ar_max_namelen */
2877 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
2878 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
2879 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
2880 bfd_getb64, bfd_getb_signed_64, bfd_putb64,
2881 bfd_getb32, bfd_getb_signed_32, bfd_putb32,
2882 bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
2883
2884 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
2885 bfd_generic_archive_p, _bfd_dummy_target},
2886 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
2887 bfd_false},
2888 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
2889 _bfd_write_archive_contents, bfd_false},
2890
2891 BFD_JUMP_TABLE_GENERIC (coff_small),
2892 BFD_JUMP_TABLE_COPY (coff),
2893 BFD_JUMP_TABLE_CORE (_bfd_nocore),
2894 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
2895 BFD_JUMP_TABLE_SYMBOLS (coff),
2896 BFD_JUMP_TABLE_RELOCS (coff),
2897 BFD_JUMP_TABLE_WRITE (coff),
2898 BFD_JUMP_TABLE_LINK (coff),
2899 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
2900
2901 (PTR) &bfd_coff_small_swap_table
2902 };
2903
2904 const bfd_target shlcoff_small_vec =
2905 {
2906 "coff-shl-small", /* name */
2907 bfd_target_coff_flavour,
2908 BFD_ENDIAN_LITTLE, /* data byte order is little */
2909 BFD_ENDIAN_LITTLE, /* header byte order is little endian too*/
2910
2911 (HAS_RELOC | EXEC_P | /* object flags */
2912 HAS_LINENO | HAS_DEBUG |
2913 HAS_SYMS | HAS_LOCALS | WP_TEXT | BFD_IS_RELAXABLE),
2914
2915 (SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC),
2916 '_', /* leading symbol underscore */
2917 '/', /* ar_pad_char */
2918 15, /* ar_max_namelen */
2919 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
2920 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
2921 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
2922 bfd_getl64, bfd_getl_signed_64, bfd_putl64,
2923 bfd_getl32, bfd_getl_signed_32, bfd_putl32,
2924 bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
2925
2926 {_bfd_dummy_target, coff_small_object_p, /* bfd_check_format */
2927 bfd_generic_archive_p, _bfd_dummy_target},
2928 {bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
2929 bfd_false},
2930 {bfd_false, coff_write_object_contents, /* bfd_write_contents */
2931 _bfd_write_archive_contents, bfd_false},
2932
2933 BFD_JUMP_TABLE_GENERIC (coff_small),
2934 BFD_JUMP_TABLE_COPY (coff),
2935 BFD_JUMP_TABLE_CORE (_bfd_nocore),
2936 BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
2937 BFD_JUMP_TABLE_SYMBOLS (coff),
2938 BFD_JUMP_TABLE_RELOCS (coff),
2939 BFD_JUMP_TABLE_WRITE (coff),
2940 BFD_JUMP_TABLE_LINK (coff),
2941 BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
2942
2943 (PTR) &bfd_coff_small_swap_table
2944 };