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Make bfd_byte an int8_t, flagword a uint32_t
[binutils-gdb.git] / bfd / elf32-arm.c
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2023 Free Software Foundation, Inc.
3
4 This file is part of BFD, the Binary File Descriptor library.
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
20
21 #include "sysdep.h"
22 #include <limits.h>
23
24 #include "bfd.h"
25 #include "libiberty.h"
26 #include "libbfd.h"
27 #include "elf-bfd.h"
28 #include "elf-nacl.h"
29 #include "elf-vxworks.h"
30 #include "elf/arm.h"
31 #include "elf32-arm.h"
32 #include "cpu-arm.h"
33
34 /* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36 #define RELOC_SECTION(HTAB, NAME) \
37 ((HTAB)->use_rel ? ".rel" NAME : ".rela" NAME)
38
39 /* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41 #define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
45
46 /* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48 #define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
52
53 /* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55 #define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
59
60 #define elf_info_to_howto NULL
61 #define elf_info_to_howto_rel elf32_arm_info_to_howto
62
63 #define ARM_ELF_ABI_VERSION 0
64 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65
66 /* The Adjusted Place, as defined by AAELF. */
67 #define Pa(X) ((X) & 0xfffffffc)
68
69 static bool elf32_arm_write_section (bfd *output_bfd,
70 struct bfd_link_info *link_info,
71 asection *sec,
72 bfd_byte *contents);
73
74 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
77
78 static reloc_howto_type elf32_arm_howto_table_1[] =
79 {
80 /* No relocation. */
81 HOWTO (R_ARM_NONE, /* type */
82 0, /* rightshift */
83 0, /* size */
84 0, /* bitsize */
85 false, /* pc_relative */
86 0, /* bitpos */
87 complain_overflow_dont,/* complain_on_overflow */
88 bfd_elf_generic_reloc, /* special_function */
89 "R_ARM_NONE", /* name */
90 false, /* partial_inplace */
91 0, /* src_mask */
92 0, /* dst_mask */
93 false), /* pcrel_offset */
94
95 HOWTO (R_ARM_PC24, /* type */
96 2, /* rightshift */
97 4, /* size */
98 24, /* bitsize */
99 true, /* pc_relative */
100 0, /* bitpos */
101 complain_overflow_signed,/* complain_on_overflow */
102 bfd_elf_generic_reloc, /* special_function */
103 "R_ARM_PC24", /* name */
104 false, /* partial_inplace */
105 0x00ffffff, /* src_mask */
106 0x00ffffff, /* dst_mask */
107 true), /* pcrel_offset */
108
109 /* 32 bit absolute */
110 HOWTO (R_ARM_ABS32, /* type */
111 0, /* rightshift */
112 4, /* size */
113 32, /* bitsize */
114 false, /* pc_relative */
115 0, /* bitpos */
116 complain_overflow_bitfield,/* complain_on_overflow */
117 bfd_elf_generic_reloc, /* special_function */
118 "R_ARM_ABS32", /* name */
119 false, /* partial_inplace */
120 0xffffffff, /* src_mask */
121 0xffffffff, /* dst_mask */
122 false), /* pcrel_offset */
123
124 /* standard 32bit pc-relative reloc */
125 HOWTO (R_ARM_REL32, /* type */
126 0, /* rightshift */
127 4, /* size */
128 32, /* bitsize */
129 true, /* pc_relative */
130 0, /* bitpos */
131 complain_overflow_bitfield,/* complain_on_overflow */
132 bfd_elf_generic_reloc, /* special_function */
133 "R_ARM_REL32", /* name */
134 false, /* partial_inplace */
135 0xffffffff, /* src_mask */
136 0xffffffff, /* dst_mask */
137 true), /* pcrel_offset */
138
139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
140 HOWTO (R_ARM_LDR_PC_G0, /* type */
141 0, /* rightshift */
142 1, /* size */
143 32, /* bitsize */
144 true, /* pc_relative */
145 0, /* bitpos */
146 complain_overflow_dont,/* complain_on_overflow */
147 bfd_elf_generic_reloc, /* special_function */
148 "R_ARM_LDR_PC_G0", /* name */
149 false, /* partial_inplace */
150 0xffffffff, /* src_mask */
151 0xffffffff, /* dst_mask */
152 true), /* pcrel_offset */
153
154 /* 16 bit absolute */
155 HOWTO (R_ARM_ABS16, /* type */
156 0, /* rightshift */
157 2, /* size */
158 16, /* bitsize */
159 false, /* pc_relative */
160 0, /* bitpos */
161 complain_overflow_bitfield,/* complain_on_overflow */
162 bfd_elf_generic_reloc, /* special_function */
163 "R_ARM_ABS16", /* name */
164 false, /* partial_inplace */
165 0x0000ffff, /* src_mask */
166 0x0000ffff, /* dst_mask */
167 false), /* pcrel_offset */
168
169 /* 12 bit absolute */
170 HOWTO (R_ARM_ABS12, /* type */
171 0, /* rightshift */
172 4, /* size */
173 12, /* bitsize */
174 false, /* pc_relative */
175 0, /* bitpos */
176 complain_overflow_bitfield,/* complain_on_overflow */
177 bfd_elf_generic_reloc, /* special_function */
178 "R_ARM_ABS12", /* name */
179 false, /* partial_inplace */
180 0x00000fff, /* src_mask */
181 0x00000fff, /* dst_mask */
182 false), /* pcrel_offset */
183
184 HOWTO (R_ARM_THM_ABS5, /* type */
185 6, /* rightshift */
186 2, /* size */
187 5, /* bitsize */
188 false, /* pc_relative */
189 0, /* bitpos */
190 complain_overflow_bitfield,/* complain_on_overflow */
191 bfd_elf_generic_reloc, /* special_function */
192 "R_ARM_THM_ABS5", /* name */
193 false, /* partial_inplace */
194 0x000007e0, /* src_mask */
195 0x000007e0, /* dst_mask */
196 false), /* pcrel_offset */
197
198 /* 8 bit absolute */
199 HOWTO (R_ARM_ABS8, /* type */
200 0, /* rightshift */
201 1, /* size */
202 8, /* bitsize */
203 false, /* pc_relative */
204 0, /* bitpos */
205 complain_overflow_bitfield,/* complain_on_overflow */
206 bfd_elf_generic_reloc, /* special_function */
207 "R_ARM_ABS8", /* name */
208 false, /* partial_inplace */
209 0x000000ff, /* src_mask */
210 0x000000ff, /* dst_mask */
211 false), /* pcrel_offset */
212
213 HOWTO (R_ARM_SBREL32, /* type */
214 0, /* rightshift */
215 4, /* size */
216 32, /* bitsize */
217 false, /* pc_relative */
218 0, /* bitpos */
219 complain_overflow_dont,/* complain_on_overflow */
220 bfd_elf_generic_reloc, /* special_function */
221 "R_ARM_SBREL32", /* name */
222 false, /* partial_inplace */
223 0xffffffff, /* src_mask */
224 0xffffffff, /* dst_mask */
225 false), /* pcrel_offset */
226
227 HOWTO (R_ARM_THM_CALL, /* type */
228 1, /* rightshift */
229 4, /* size */
230 24, /* bitsize */
231 true, /* pc_relative */
232 0, /* bitpos */
233 complain_overflow_signed,/* complain_on_overflow */
234 bfd_elf_generic_reloc, /* special_function */
235 "R_ARM_THM_CALL", /* name */
236 false, /* partial_inplace */
237 0x07ff2fff, /* src_mask */
238 0x07ff2fff, /* dst_mask */
239 true), /* pcrel_offset */
240
241 HOWTO (R_ARM_THM_PC8, /* type */
242 1, /* rightshift */
243 2, /* size */
244 8, /* bitsize */
245 true, /* pc_relative */
246 0, /* bitpos */
247 complain_overflow_signed,/* complain_on_overflow */
248 bfd_elf_generic_reloc, /* special_function */
249 "R_ARM_THM_PC8", /* name */
250 false, /* partial_inplace */
251 0x000000ff, /* src_mask */
252 0x000000ff, /* dst_mask */
253 true), /* pcrel_offset */
254
255 HOWTO (R_ARM_BREL_ADJ, /* type */
256 1, /* rightshift */
257 2, /* size */
258 32, /* bitsize */
259 false, /* pc_relative */
260 0, /* bitpos */
261 complain_overflow_signed,/* complain_on_overflow */
262 bfd_elf_generic_reloc, /* special_function */
263 "R_ARM_BREL_ADJ", /* name */
264 false, /* partial_inplace */
265 0xffffffff, /* src_mask */
266 0xffffffff, /* dst_mask */
267 false), /* pcrel_offset */
268
269 HOWTO (R_ARM_TLS_DESC, /* type */
270 0, /* rightshift */
271 4, /* size */
272 32, /* bitsize */
273 false, /* pc_relative */
274 0, /* bitpos */
275 complain_overflow_bitfield,/* complain_on_overflow */
276 bfd_elf_generic_reloc, /* special_function */
277 "R_ARM_TLS_DESC", /* name */
278 false, /* partial_inplace */
279 0xffffffff, /* src_mask */
280 0xffffffff, /* dst_mask */
281 false), /* pcrel_offset */
282
283 HOWTO (R_ARM_THM_SWI8, /* type */
284 0, /* rightshift */
285 0, /* size */
286 0, /* bitsize */
287 false, /* pc_relative */
288 0, /* bitpos */
289 complain_overflow_signed,/* complain_on_overflow */
290 bfd_elf_generic_reloc, /* special_function */
291 "R_ARM_SWI8", /* name */
292 false, /* partial_inplace */
293 0x00000000, /* src_mask */
294 0x00000000, /* dst_mask */
295 false), /* pcrel_offset */
296
297 /* BLX instruction for the ARM. */
298 HOWTO (R_ARM_XPC25, /* type */
299 2, /* rightshift */
300 4, /* size */
301 24, /* bitsize */
302 true, /* pc_relative */
303 0, /* bitpos */
304 complain_overflow_signed,/* complain_on_overflow */
305 bfd_elf_generic_reloc, /* special_function */
306 "R_ARM_XPC25", /* name */
307 false, /* partial_inplace */
308 0x00ffffff, /* src_mask */
309 0x00ffffff, /* dst_mask */
310 true), /* pcrel_offset */
311
312 /* BLX instruction for the Thumb. */
313 HOWTO (R_ARM_THM_XPC22, /* type */
314 2, /* rightshift */
315 4, /* size */
316 24, /* bitsize */
317 true, /* pc_relative */
318 0, /* bitpos */
319 complain_overflow_signed,/* complain_on_overflow */
320 bfd_elf_generic_reloc, /* special_function */
321 "R_ARM_THM_XPC22", /* name */
322 false, /* partial_inplace */
323 0x07ff2fff, /* src_mask */
324 0x07ff2fff, /* dst_mask */
325 true), /* pcrel_offset */
326
327 /* Dynamic TLS relocations. */
328
329 HOWTO (R_ARM_TLS_DTPMOD32, /* type */
330 0, /* rightshift */
331 4, /* size */
332 32, /* bitsize */
333 false, /* pc_relative */
334 0, /* bitpos */
335 complain_overflow_bitfield,/* complain_on_overflow */
336 bfd_elf_generic_reloc, /* special_function */
337 "R_ARM_TLS_DTPMOD32", /* name */
338 true, /* partial_inplace */
339 0xffffffff, /* src_mask */
340 0xffffffff, /* dst_mask */
341 false), /* pcrel_offset */
342
343 HOWTO (R_ARM_TLS_DTPOFF32, /* type */
344 0, /* rightshift */
345 4, /* size */
346 32, /* bitsize */
347 false, /* pc_relative */
348 0, /* bitpos */
349 complain_overflow_bitfield,/* complain_on_overflow */
350 bfd_elf_generic_reloc, /* special_function */
351 "R_ARM_TLS_DTPOFF32", /* name */
352 true, /* partial_inplace */
353 0xffffffff, /* src_mask */
354 0xffffffff, /* dst_mask */
355 false), /* pcrel_offset */
356
357 HOWTO (R_ARM_TLS_TPOFF32, /* type */
358 0, /* rightshift */
359 4, /* size */
360 32, /* bitsize */
361 false, /* pc_relative */
362 0, /* bitpos */
363 complain_overflow_bitfield,/* complain_on_overflow */
364 bfd_elf_generic_reloc, /* special_function */
365 "R_ARM_TLS_TPOFF32", /* name */
366 true, /* partial_inplace */
367 0xffffffff, /* src_mask */
368 0xffffffff, /* dst_mask */
369 false), /* pcrel_offset */
370
371 /* Relocs used in ARM Linux */
372
373 HOWTO (R_ARM_COPY, /* type */
374 0, /* rightshift */
375 4, /* size */
376 32, /* bitsize */
377 false, /* pc_relative */
378 0, /* bitpos */
379 complain_overflow_bitfield,/* complain_on_overflow */
380 bfd_elf_generic_reloc, /* special_function */
381 "R_ARM_COPY", /* name */
382 true, /* partial_inplace */
383 0xffffffff, /* src_mask */
384 0xffffffff, /* dst_mask */
385 false), /* pcrel_offset */
386
387 HOWTO (R_ARM_GLOB_DAT, /* type */
388 0, /* rightshift */
389 4, /* size */
390 32, /* bitsize */
391 false, /* pc_relative */
392 0, /* bitpos */
393 complain_overflow_bitfield,/* complain_on_overflow */
394 bfd_elf_generic_reloc, /* special_function */
395 "R_ARM_GLOB_DAT", /* name */
396 true, /* partial_inplace */
397 0xffffffff, /* src_mask */
398 0xffffffff, /* dst_mask */
399 false), /* pcrel_offset */
400
401 HOWTO (R_ARM_JUMP_SLOT, /* type */
402 0, /* rightshift */
403 4, /* size */
404 32, /* bitsize */
405 false, /* pc_relative */
406 0, /* bitpos */
407 complain_overflow_bitfield,/* complain_on_overflow */
408 bfd_elf_generic_reloc, /* special_function */
409 "R_ARM_JUMP_SLOT", /* name */
410 true, /* partial_inplace */
411 0xffffffff, /* src_mask */
412 0xffffffff, /* dst_mask */
413 false), /* pcrel_offset */
414
415 HOWTO (R_ARM_RELATIVE, /* type */
416 0, /* rightshift */
417 4, /* size */
418 32, /* bitsize */
419 false, /* pc_relative */
420 0, /* bitpos */
421 complain_overflow_bitfield,/* complain_on_overflow */
422 bfd_elf_generic_reloc, /* special_function */
423 "R_ARM_RELATIVE", /* name */
424 true, /* partial_inplace */
425 0xffffffff, /* src_mask */
426 0xffffffff, /* dst_mask */
427 false), /* pcrel_offset */
428
429 HOWTO (R_ARM_GOTOFF32, /* type */
430 0, /* rightshift */
431 4, /* size */
432 32, /* bitsize */
433 false, /* pc_relative */
434 0, /* bitpos */
435 complain_overflow_bitfield,/* complain_on_overflow */
436 bfd_elf_generic_reloc, /* special_function */
437 "R_ARM_GOTOFF32", /* name */
438 true, /* partial_inplace */
439 0xffffffff, /* src_mask */
440 0xffffffff, /* dst_mask */
441 false), /* pcrel_offset */
442
443 HOWTO (R_ARM_GOTPC, /* type */
444 0, /* rightshift */
445 4, /* size */
446 32, /* bitsize */
447 true, /* pc_relative */
448 0, /* bitpos */
449 complain_overflow_bitfield,/* complain_on_overflow */
450 bfd_elf_generic_reloc, /* special_function */
451 "R_ARM_GOTPC", /* name */
452 true, /* partial_inplace */
453 0xffffffff, /* src_mask */
454 0xffffffff, /* dst_mask */
455 true), /* pcrel_offset */
456
457 HOWTO (R_ARM_GOT32, /* type */
458 0, /* rightshift */
459 4, /* size */
460 32, /* bitsize */
461 false, /* pc_relative */
462 0, /* bitpos */
463 complain_overflow_bitfield,/* complain_on_overflow */
464 bfd_elf_generic_reloc, /* special_function */
465 "R_ARM_GOT32", /* name */
466 true, /* partial_inplace */
467 0xffffffff, /* src_mask */
468 0xffffffff, /* dst_mask */
469 false), /* pcrel_offset */
470
471 HOWTO (R_ARM_PLT32, /* type */
472 2, /* rightshift */
473 4, /* size */
474 24, /* bitsize */
475 true, /* pc_relative */
476 0, /* bitpos */
477 complain_overflow_bitfield,/* complain_on_overflow */
478 bfd_elf_generic_reloc, /* special_function */
479 "R_ARM_PLT32", /* name */
480 false, /* partial_inplace */
481 0x00ffffff, /* src_mask */
482 0x00ffffff, /* dst_mask */
483 true), /* pcrel_offset */
484
485 HOWTO (R_ARM_CALL, /* type */
486 2, /* rightshift */
487 4, /* size */
488 24, /* bitsize */
489 true, /* pc_relative */
490 0, /* bitpos */
491 complain_overflow_signed,/* complain_on_overflow */
492 bfd_elf_generic_reloc, /* special_function */
493 "R_ARM_CALL", /* name */
494 false, /* partial_inplace */
495 0x00ffffff, /* src_mask */
496 0x00ffffff, /* dst_mask */
497 true), /* pcrel_offset */
498
499 HOWTO (R_ARM_JUMP24, /* type */
500 2, /* rightshift */
501 4, /* size */
502 24, /* bitsize */
503 true, /* pc_relative */
504 0, /* bitpos */
505 complain_overflow_signed,/* complain_on_overflow */
506 bfd_elf_generic_reloc, /* special_function */
507 "R_ARM_JUMP24", /* name */
508 false, /* partial_inplace */
509 0x00ffffff, /* src_mask */
510 0x00ffffff, /* dst_mask */
511 true), /* pcrel_offset */
512
513 HOWTO (R_ARM_THM_JUMP24, /* type */
514 1, /* rightshift */
515 4, /* size */
516 24, /* bitsize */
517 true, /* pc_relative */
518 0, /* bitpos */
519 complain_overflow_signed,/* complain_on_overflow */
520 bfd_elf_generic_reloc, /* special_function */
521 "R_ARM_THM_JUMP24", /* name */
522 false, /* partial_inplace */
523 0x07ff2fff, /* src_mask */
524 0x07ff2fff, /* dst_mask */
525 true), /* pcrel_offset */
526
527 HOWTO (R_ARM_BASE_ABS, /* type */
528 0, /* rightshift */
529 4, /* size */
530 32, /* bitsize */
531 false, /* pc_relative */
532 0, /* bitpos */
533 complain_overflow_dont,/* complain_on_overflow */
534 bfd_elf_generic_reloc, /* special_function */
535 "R_ARM_BASE_ABS", /* name */
536 false, /* partial_inplace */
537 0xffffffff, /* src_mask */
538 0xffffffff, /* dst_mask */
539 false), /* pcrel_offset */
540
541 HOWTO (R_ARM_ALU_PCREL7_0, /* type */
542 0, /* rightshift */
543 4, /* size */
544 12, /* bitsize */
545 true, /* pc_relative */
546 0, /* bitpos */
547 complain_overflow_dont,/* complain_on_overflow */
548 bfd_elf_generic_reloc, /* special_function */
549 "R_ARM_ALU_PCREL_7_0", /* name */
550 false, /* partial_inplace */
551 0x00000fff, /* src_mask */
552 0x00000fff, /* dst_mask */
553 true), /* pcrel_offset */
554
555 HOWTO (R_ARM_ALU_PCREL15_8, /* type */
556 0, /* rightshift */
557 4, /* size */
558 12, /* bitsize */
559 true, /* pc_relative */
560 8, /* bitpos */
561 complain_overflow_dont,/* complain_on_overflow */
562 bfd_elf_generic_reloc, /* special_function */
563 "R_ARM_ALU_PCREL_15_8",/* name */
564 false, /* partial_inplace */
565 0x00000fff, /* src_mask */
566 0x00000fff, /* dst_mask */
567 true), /* pcrel_offset */
568
569 HOWTO (R_ARM_ALU_PCREL23_15, /* type */
570 0, /* rightshift */
571 4, /* size */
572 12, /* bitsize */
573 true, /* pc_relative */
574 16, /* bitpos */
575 complain_overflow_dont,/* complain_on_overflow */
576 bfd_elf_generic_reloc, /* special_function */
577 "R_ARM_ALU_PCREL_23_15",/* name */
578 false, /* partial_inplace */
579 0x00000fff, /* src_mask */
580 0x00000fff, /* dst_mask */
581 true), /* pcrel_offset */
582
583 HOWTO (R_ARM_LDR_SBREL_11_0, /* type */
584 0, /* rightshift */
585 4, /* size */
586 12, /* bitsize */
587 false, /* pc_relative */
588 0, /* bitpos */
589 complain_overflow_dont,/* complain_on_overflow */
590 bfd_elf_generic_reloc, /* special_function */
591 "R_ARM_LDR_SBREL_11_0",/* name */
592 false, /* partial_inplace */
593 0x00000fff, /* src_mask */
594 0x00000fff, /* dst_mask */
595 false), /* pcrel_offset */
596
597 HOWTO (R_ARM_ALU_SBREL_19_12, /* type */
598 0, /* rightshift */
599 4, /* size */
600 8, /* bitsize */
601 false, /* pc_relative */
602 12, /* bitpos */
603 complain_overflow_dont,/* complain_on_overflow */
604 bfd_elf_generic_reloc, /* special_function */
605 "R_ARM_ALU_SBREL_19_12",/* name */
606 false, /* partial_inplace */
607 0x000ff000, /* src_mask */
608 0x000ff000, /* dst_mask */
609 false), /* pcrel_offset */
610
611 HOWTO (R_ARM_ALU_SBREL_27_20, /* type */
612 0, /* rightshift */
613 4, /* size */
614 8, /* bitsize */
615 false, /* pc_relative */
616 20, /* bitpos */
617 complain_overflow_dont,/* complain_on_overflow */
618 bfd_elf_generic_reloc, /* special_function */
619 "R_ARM_ALU_SBREL_27_20",/* name */
620 false, /* partial_inplace */
621 0x0ff00000, /* src_mask */
622 0x0ff00000, /* dst_mask */
623 false), /* pcrel_offset */
624
625 HOWTO (R_ARM_TARGET1, /* type */
626 0, /* rightshift */
627 4, /* size */
628 32, /* bitsize */
629 false, /* pc_relative */
630 0, /* bitpos */
631 complain_overflow_dont,/* complain_on_overflow */
632 bfd_elf_generic_reloc, /* special_function */
633 "R_ARM_TARGET1", /* name */
634 false, /* partial_inplace */
635 0xffffffff, /* src_mask */
636 0xffffffff, /* dst_mask */
637 false), /* pcrel_offset */
638
639 HOWTO (R_ARM_ROSEGREL32, /* type */
640 0, /* rightshift */
641 4, /* size */
642 32, /* bitsize */
643 false, /* pc_relative */
644 0, /* bitpos */
645 complain_overflow_dont,/* complain_on_overflow */
646 bfd_elf_generic_reloc, /* special_function */
647 "R_ARM_ROSEGREL32", /* name */
648 false, /* partial_inplace */
649 0xffffffff, /* src_mask */
650 0xffffffff, /* dst_mask */
651 false), /* pcrel_offset */
652
653 HOWTO (R_ARM_V4BX, /* type */
654 0, /* rightshift */
655 4, /* size */
656 32, /* bitsize */
657 false, /* pc_relative */
658 0, /* bitpos */
659 complain_overflow_dont,/* complain_on_overflow */
660 bfd_elf_generic_reloc, /* special_function */
661 "R_ARM_V4BX", /* name */
662 false, /* partial_inplace */
663 0xffffffff, /* src_mask */
664 0xffffffff, /* dst_mask */
665 false), /* pcrel_offset */
666
667 HOWTO (R_ARM_TARGET2, /* type */
668 0, /* rightshift */
669 4, /* size */
670 32, /* bitsize */
671 false, /* pc_relative */
672 0, /* bitpos */
673 complain_overflow_signed,/* complain_on_overflow */
674 bfd_elf_generic_reloc, /* special_function */
675 "R_ARM_TARGET2", /* name */
676 false, /* partial_inplace */
677 0xffffffff, /* src_mask */
678 0xffffffff, /* dst_mask */
679 true), /* pcrel_offset */
680
681 HOWTO (R_ARM_PREL31, /* type */
682 0, /* rightshift */
683 4, /* size */
684 31, /* bitsize */
685 true, /* pc_relative */
686 0, /* bitpos */
687 complain_overflow_signed,/* complain_on_overflow */
688 bfd_elf_generic_reloc, /* special_function */
689 "R_ARM_PREL31", /* name */
690 false, /* partial_inplace */
691 0x7fffffff, /* src_mask */
692 0x7fffffff, /* dst_mask */
693 true), /* pcrel_offset */
694
695 HOWTO (R_ARM_MOVW_ABS_NC, /* type */
696 0, /* rightshift */
697 4, /* size */
698 16, /* bitsize */
699 false, /* pc_relative */
700 0, /* bitpos */
701 complain_overflow_dont,/* complain_on_overflow */
702 bfd_elf_generic_reloc, /* special_function */
703 "R_ARM_MOVW_ABS_NC", /* name */
704 false, /* partial_inplace */
705 0x000f0fff, /* src_mask */
706 0x000f0fff, /* dst_mask */
707 false), /* pcrel_offset */
708
709 HOWTO (R_ARM_MOVT_ABS, /* type */
710 0, /* rightshift */
711 4, /* size */
712 16, /* bitsize */
713 false, /* pc_relative */
714 0, /* bitpos */
715 complain_overflow_bitfield,/* complain_on_overflow */
716 bfd_elf_generic_reloc, /* special_function */
717 "R_ARM_MOVT_ABS", /* name */
718 false, /* partial_inplace */
719 0x000f0fff, /* src_mask */
720 0x000f0fff, /* dst_mask */
721 false), /* pcrel_offset */
722
723 HOWTO (R_ARM_MOVW_PREL_NC, /* type */
724 0, /* rightshift */
725 4, /* size */
726 16, /* bitsize */
727 true, /* pc_relative */
728 0, /* bitpos */
729 complain_overflow_dont,/* complain_on_overflow */
730 bfd_elf_generic_reloc, /* special_function */
731 "R_ARM_MOVW_PREL_NC", /* name */
732 false, /* partial_inplace */
733 0x000f0fff, /* src_mask */
734 0x000f0fff, /* dst_mask */
735 true), /* pcrel_offset */
736
737 HOWTO (R_ARM_MOVT_PREL, /* type */
738 0, /* rightshift */
739 4, /* size */
740 16, /* bitsize */
741 true, /* pc_relative */
742 0, /* bitpos */
743 complain_overflow_bitfield,/* complain_on_overflow */
744 bfd_elf_generic_reloc, /* special_function */
745 "R_ARM_MOVT_PREL", /* name */
746 false, /* partial_inplace */
747 0x000f0fff, /* src_mask */
748 0x000f0fff, /* dst_mask */
749 true), /* pcrel_offset */
750
751 HOWTO (R_ARM_THM_MOVW_ABS_NC, /* type */
752 0, /* rightshift */
753 4, /* size */
754 16, /* bitsize */
755 false, /* pc_relative */
756 0, /* bitpos */
757 complain_overflow_dont,/* complain_on_overflow */
758 bfd_elf_generic_reloc, /* special_function */
759 "R_ARM_THM_MOVW_ABS_NC",/* name */
760 false, /* partial_inplace */
761 0x040f70ff, /* src_mask */
762 0x040f70ff, /* dst_mask */
763 false), /* pcrel_offset */
764
765 HOWTO (R_ARM_THM_MOVT_ABS, /* type */
766 0, /* rightshift */
767 4, /* size */
768 16, /* bitsize */
769 false, /* pc_relative */
770 0, /* bitpos */
771 complain_overflow_bitfield,/* complain_on_overflow */
772 bfd_elf_generic_reloc, /* special_function */
773 "R_ARM_THM_MOVT_ABS", /* name */
774 false, /* partial_inplace */
775 0x040f70ff, /* src_mask */
776 0x040f70ff, /* dst_mask */
777 false), /* pcrel_offset */
778
779 HOWTO (R_ARM_THM_MOVW_PREL_NC,/* type */
780 0, /* rightshift */
781 4, /* size */
782 16, /* bitsize */
783 true, /* pc_relative */
784 0, /* bitpos */
785 complain_overflow_dont,/* complain_on_overflow */
786 bfd_elf_generic_reloc, /* special_function */
787 "R_ARM_THM_MOVW_PREL_NC",/* name */
788 false, /* partial_inplace */
789 0x040f70ff, /* src_mask */
790 0x040f70ff, /* dst_mask */
791 true), /* pcrel_offset */
792
793 HOWTO (R_ARM_THM_MOVT_PREL, /* type */
794 0, /* rightshift */
795 4, /* size */
796 16, /* bitsize */
797 true, /* pc_relative */
798 0, /* bitpos */
799 complain_overflow_bitfield,/* complain_on_overflow */
800 bfd_elf_generic_reloc, /* special_function */
801 "R_ARM_THM_MOVT_PREL", /* name */
802 false, /* partial_inplace */
803 0x040f70ff, /* src_mask */
804 0x040f70ff, /* dst_mask */
805 true), /* pcrel_offset */
806
807 HOWTO (R_ARM_THM_JUMP19, /* type */
808 1, /* rightshift */
809 4, /* size */
810 19, /* bitsize */
811 true, /* pc_relative */
812 0, /* bitpos */
813 complain_overflow_signed,/* complain_on_overflow */
814 bfd_elf_generic_reloc, /* special_function */
815 "R_ARM_THM_JUMP19", /* name */
816 false, /* partial_inplace */
817 0x043f2fff, /* src_mask */
818 0x043f2fff, /* dst_mask */
819 true), /* pcrel_offset */
820
821 HOWTO (R_ARM_THM_JUMP6, /* type */
822 1, /* rightshift */
823 2, /* size */
824 6, /* bitsize */
825 true, /* pc_relative */
826 0, /* bitpos */
827 complain_overflow_unsigned,/* complain_on_overflow */
828 bfd_elf_generic_reloc, /* special_function */
829 "R_ARM_THM_JUMP6", /* name */
830 false, /* partial_inplace */
831 0x02f8, /* src_mask */
832 0x02f8, /* dst_mask */
833 true), /* pcrel_offset */
834
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
838 HOWTO (R_ARM_THM_ALU_PREL_11_0,/* type */
839 0, /* rightshift */
840 4, /* size */
841 13, /* bitsize */
842 true, /* pc_relative */
843 0, /* bitpos */
844 complain_overflow_dont,/* complain_on_overflow */
845 bfd_elf_generic_reloc, /* special_function */
846 "R_ARM_THM_ALU_PREL_11_0",/* name */
847 false, /* partial_inplace */
848 0xffffffff, /* src_mask */
849 0xffffffff, /* dst_mask */
850 true), /* pcrel_offset */
851
852 HOWTO (R_ARM_THM_PC12, /* type */
853 0, /* rightshift */
854 4, /* size */
855 13, /* bitsize */
856 true, /* pc_relative */
857 0, /* bitpos */
858 complain_overflow_dont,/* complain_on_overflow */
859 bfd_elf_generic_reloc, /* special_function */
860 "R_ARM_THM_PC12", /* name */
861 false, /* partial_inplace */
862 0xffffffff, /* src_mask */
863 0xffffffff, /* dst_mask */
864 true), /* pcrel_offset */
865
866 HOWTO (R_ARM_ABS32_NOI, /* type */
867 0, /* rightshift */
868 4, /* size */
869 32, /* bitsize */
870 false, /* pc_relative */
871 0, /* bitpos */
872 complain_overflow_dont,/* complain_on_overflow */
873 bfd_elf_generic_reloc, /* special_function */
874 "R_ARM_ABS32_NOI", /* name */
875 false, /* partial_inplace */
876 0xffffffff, /* src_mask */
877 0xffffffff, /* dst_mask */
878 false), /* pcrel_offset */
879
880 HOWTO (R_ARM_REL32_NOI, /* type */
881 0, /* rightshift */
882 4, /* size */
883 32, /* bitsize */
884 true, /* pc_relative */
885 0, /* bitpos */
886 complain_overflow_dont,/* complain_on_overflow */
887 bfd_elf_generic_reloc, /* special_function */
888 "R_ARM_REL32_NOI", /* name */
889 false, /* partial_inplace */
890 0xffffffff, /* src_mask */
891 0xffffffff, /* dst_mask */
892 false), /* pcrel_offset */
893
894 /* Group relocations. */
895
896 HOWTO (R_ARM_ALU_PC_G0_NC, /* type */
897 0, /* rightshift */
898 4, /* size */
899 32, /* bitsize */
900 true, /* pc_relative */
901 0, /* bitpos */
902 complain_overflow_dont,/* complain_on_overflow */
903 bfd_elf_generic_reloc, /* special_function */
904 "R_ARM_ALU_PC_G0_NC", /* name */
905 false, /* partial_inplace */
906 0xffffffff, /* src_mask */
907 0xffffffff, /* dst_mask */
908 true), /* pcrel_offset */
909
910 HOWTO (R_ARM_ALU_PC_G0, /* type */
911 0, /* rightshift */
912 4, /* size */
913 32, /* bitsize */
914 true, /* pc_relative */
915 0, /* bitpos */
916 complain_overflow_dont,/* complain_on_overflow */
917 bfd_elf_generic_reloc, /* special_function */
918 "R_ARM_ALU_PC_G0", /* name */
919 false, /* partial_inplace */
920 0xffffffff, /* src_mask */
921 0xffffffff, /* dst_mask */
922 true), /* pcrel_offset */
923
924 HOWTO (R_ARM_ALU_PC_G1_NC, /* type */
925 0, /* rightshift */
926 4, /* size */
927 32, /* bitsize */
928 true, /* pc_relative */
929 0, /* bitpos */
930 complain_overflow_dont,/* complain_on_overflow */
931 bfd_elf_generic_reloc, /* special_function */
932 "R_ARM_ALU_PC_G1_NC", /* name */
933 false, /* partial_inplace */
934 0xffffffff, /* src_mask */
935 0xffffffff, /* dst_mask */
936 true), /* pcrel_offset */
937
938 HOWTO (R_ARM_ALU_PC_G1, /* type */
939 0, /* rightshift */
940 4, /* size */
941 32, /* bitsize */
942 true, /* pc_relative */
943 0, /* bitpos */
944 complain_overflow_dont,/* complain_on_overflow */
945 bfd_elf_generic_reloc, /* special_function */
946 "R_ARM_ALU_PC_G1", /* name */
947 false, /* partial_inplace */
948 0xffffffff, /* src_mask */
949 0xffffffff, /* dst_mask */
950 true), /* pcrel_offset */
951
952 HOWTO (R_ARM_ALU_PC_G2, /* type */
953 0, /* rightshift */
954 4, /* size */
955 32, /* bitsize */
956 true, /* pc_relative */
957 0, /* bitpos */
958 complain_overflow_dont,/* complain_on_overflow */
959 bfd_elf_generic_reloc, /* special_function */
960 "R_ARM_ALU_PC_G2", /* name */
961 false, /* partial_inplace */
962 0xffffffff, /* src_mask */
963 0xffffffff, /* dst_mask */
964 true), /* pcrel_offset */
965
966 HOWTO (R_ARM_LDR_PC_G1, /* type */
967 0, /* rightshift */
968 4, /* size */
969 32, /* bitsize */
970 true, /* pc_relative */
971 0, /* bitpos */
972 complain_overflow_dont,/* complain_on_overflow */
973 bfd_elf_generic_reloc, /* special_function */
974 "R_ARM_LDR_PC_G1", /* name */
975 false, /* partial_inplace */
976 0xffffffff, /* src_mask */
977 0xffffffff, /* dst_mask */
978 true), /* pcrel_offset */
979
980 HOWTO (R_ARM_LDR_PC_G2, /* type */
981 0, /* rightshift */
982 4, /* size */
983 32, /* bitsize */
984 true, /* pc_relative */
985 0, /* bitpos */
986 complain_overflow_dont,/* complain_on_overflow */
987 bfd_elf_generic_reloc, /* special_function */
988 "R_ARM_LDR_PC_G2", /* name */
989 false, /* partial_inplace */
990 0xffffffff, /* src_mask */
991 0xffffffff, /* dst_mask */
992 true), /* pcrel_offset */
993
994 HOWTO (R_ARM_LDRS_PC_G0, /* type */
995 0, /* rightshift */
996 4, /* size */
997 32, /* bitsize */
998 true, /* pc_relative */
999 0, /* bitpos */
1000 complain_overflow_dont,/* complain_on_overflow */
1001 bfd_elf_generic_reloc, /* special_function */
1002 "R_ARM_LDRS_PC_G0", /* name */
1003 false, /* partial_inplace */
1004 0xffffffff, /* src_mask */
1005 0xffffffff, /* dst_mask */
1006 true), /* pcrel_offset */
1007
1008 HOWTO (R_ARM_LDRS_PC_G1, /* type */
1009 0, /* rightshift */
1010 4, /* size */
1011 32, /* bitsize */
1012 true, /* pc_relative */
1013 0, /* bitpos */
1014 complain_overflow_dont,/* complain_on_overflow */
1015 bfd_elf_generic_reloc, /* special_function */
1016 "R_ARM_LDRS_PC_G1", /* name */
1017 false, /* partial_inplace */
1018 0xffffffff, /* src_mask */
1019 0xffffffff, /* dst_mask */
1020 true), /* pcrel_offset */
1021
1022 HOWTO (R_ARM_LDRS_PC_G2, /* type */
1023 0, /* rightshift */
1024 4, /* size */
1025 32, /* bitsize */
1026 true, /* pc_relative */
1027 0, /* bitpos */
1028 complain_overflow_dont,/* complain_on_overflow */
1029 bfd_elf_generic_reloc, /* special_function */
1030 "R_ARM_LDRS_PC_G2", /* name */
1031 false, /* partial_inplace */
1032 0xffffffff, /* src_mask */
1033 0xffffffff, /* dst_mask */
1034 true), /* pcrel_offset */
1035
1036 HOWTO (R_ARM_LDC_PC_G0, /* type */
1037 0, /* rightshift */
1038 4, /* size */
1039 32, /* bitsize */
1040 true, /* pc_relative */
1041 0, /* bitpos */
1042 complain_overflow_dont,/* complain_on_overflow */
1043 bfd_elf_generic_reloc, /* special_function */
1044 "R_ARM_LDC_PC_G0", /* name */
1045 false, /* partial_inplace */
1046 0xffffffff, /* src_mask */
1047 0xffffffff, /* dst_mask */
1048 true), /* pcrel_offset */
1049
1050 HOWTO (R_ARM_LDC_PC_G1, /* type */
1051 0, /* rightshift */
1052 4, /* size */
1053 32, /* bitsize */
1054 true, /* pc_relative */
1055 0, /* bitpos */
1056 complain_overflow_dont,/* complain_on_overflow */
1057 bfd_elf_generic_reloc, /* special_function */
1058 "R_ARM_LDC_PC_G1", /* name */
1059 false, /* partial_inplace */
1060 0xffffffff, /* src_mask */
1061 0xffffffff, /* dst_mask */
1062 true), /* pcrel_offset */
1063
1064 HOWTO (R_ARM_LDC_PC_G2, /* type */
1065 0, /* rightshift */
1066 4, /* size */
1067 32, /* bitsize */
1068 true, /* pc_relative */
1069 0, /* bitpos */
1070 complain_overflow_dont,/* complain_on_overflow */
1071 bfd_elf_generic_reloc, /* special_function */
1072 "R_ARM_LDC_PC_G2", /* name */
1073 false, /* partial_inplace */
1074 0xffffffff, /* src_mask */
1075 0xffffffff, /* dst_mask */
1076 true), /* pcrel_offset */
1077
1078 HOWTO (R_ARM_ALU_SB_G0_NC, /* type */
1079 0, /* rightshift */
1080 4, /* size */
1081 32, /* bitsize */
1082 true, /* pc_relative */
1083 0, /* bitpos */
1084 complain_overflow_dont,/* complain_on_overflow */
1085 bfd_elf_generic_reloc, /* special_function */
1086 "R_ARM_ALU_SB_G0_NC", /* name */
1087 false, /* partial_inplace */
1088 0xffffffff, /* src_mask */
1089 0xffffffff, /* dst_mask */
1090 true), /* pcrel_offset */
1091
1092 HOWTO (R_ARM_ALU_SB_G0, /* type */
1093 0, /* rightshift */
1094 4, /* size */
1095 32, /* bitsize */
1096 true, /* pc_relative */
1097 0, /* bitpos */
1098 complain_overflow_dont,/* complain_on_overflow */
1099 bfd_elf_generic_reloc, /* special_function */
1100 "R_ARM_ALU_SB_G0", /* name */
1101 false, /* partial_inplace */
1102 0xffffffff, /* src_mask */
1103 0xffffffff, /* dst_mask */
1104 true), /* pcrel_offset */
1105
1106 HOWTO (R_ARM_ALU_SB_G1_NC, /* type */
1107 0, /* rightshift */
1108 4, /* size */
1109 32, /* bitsize */
1110 true, /* pc_relative */
1111 0, /* bitpos */
1112 complain_overflow_dont,/* complain_on_overflow */
1113 bfd_elf_generic_reloc, /* special_function */
1114 "R_ARM_ALU_SB_G1_NC", /* name */
1115 false, /* partial_inplace */
1116 0xffffffff, /* src_mask */
1117 0xffffffff, /* dst_mask */
1118 true), /* pcrel_offset */
1119
1120 HOWTO (R_ARM_ALU_SB_G1, /* type */
1121 0, /* rightshift */
1122 4, /* size */
1123 32, /* bitsize */
1124 true, /* pc_relative */
1125 0, /* bitpos */
1126 complain_overflow_dont,/* complain_on_overflow */
1127 bfd_elf_generic_reloc, /* special_function */
1128 "R_ARM_ALU_SB_G1", /* name */
1129 false, /* partial_inplace */
1130 0xffffffff, /* src_mask */
1131 0xffffffff, /* dst_mask */
1132 true), /* pcrel_offset */
1133
1134 HOWTO (R_ARM_ALU_SB_G2, /* type */
1135 0, /* rightshift */
1136 4, /* size */
1137 32, /* bitsize */
1138 true, /* pc_relative */
1139 0, /* bitpos */
1140 complain_overflow_dont,/* complain_on_overflow */
1141 bfd_elf_generic_reloc, /* special_function */
1142 "R_ARM_ALU_SB_G2", /* name */
1143 false, /* partial_inplace */
1144 0xffffffff, /* src_mask */
1145 0xffffffff, /* dst_mask */
1146 true), /* pcrel_offset */
1147
1148 HOWTO (R_ARM_LDR_SB_G0, /* type */
1149 0, /* rightshift */
1150 4, /* size */
1151 32, /* bitsize */
1152 true, /* pc_relative */
1153 0, /* bitpos */
1154 complain_overflow_dont,/* complain_on_overflow */
1155 bfd_elf_generic_reloc, /* special_function */
1156 "R_ARM_LDR_SB_G0", /* name */
1157 false, /* partial_inplace */
1158 0xffffffff, /* src_mask */
1159 0xffffffff, /* dst_mask */
1160 true), /* pcrel_offset */
1161
1162 HOWTO (R_ARM_LDR_SB_G1, /* type */
1163 0, /* rightshift */
1164 4, /* size */
1165 32, /* bitsize */
1166 true, /* pc_relative */
1167 0, /* bitpos */
1168 complain_overflow_dont,/* complain_on_overflow */
1169 bfd_elf_generic_reloc, /* special_function */
1170 "R_ARM_LDR_SB_G1", /* name */
1171 false, /* partial_inplace */
1172 0xffffffff, /* src_mask */
1173 0xffffffff, /* dst_mask */
1174 true), /* pcrel_offset */
1175
1176 HOWTO (R_ARM_LDR_SB_G2, /* type */
1177 0, /* rightshift */
1178 4, /* size */
1179 32, /* bitsize */
1180 true, /* pc_relative */
1181 0, /* bitpos */
1182 complain_overflow_dont,/* complain_on_overflow */
1183 bfd_elf_generic_reloc, /* special_function */
1184 "R_ARM_LDR_SB_G2", /* name */
1185 false, /* partial_inplace */
1186 0xffffffff, /* src_mask */
1187 0xffffffff, /* dst_mask */
1188 true), /* pcrel_offset */
1189
1190 HOWTO (R_ARM_LDRS_SB_G0, /* type */
1191 0, /* rightshift */
1192 4, /* size */
1193 32, /* bitsize */
1194 true, /* pc_relative */
1195 0, /* bitpos */
1196 complain_overflow_dont,/* complain_on_overflow */
1197 bfd_elf_generic_reloc, /* special_function */
1198 "R_ARM_LDRS_SB_G0", /* name */
1199 false, /* partial_inplace */
1200 0xffffffff, /* src_mask */
1201 0xffffffff, /* dst_mask */
1202 true), /* pcrel_offset */
1203
1204 HOWTO (R_ARM_LDRS_SB_G1, /* type */
1205 0, /* rightshift */
1206 4, /* size */
1207 32, /* bitsize */
1208 true, /* pc_relative */
1209 0, /* bitpos */
1210 complain_overflow_dont,/* complain_on_overflow */
1211 bfd_elf_generic_reloc, /* special_function */
1212 "R_ARM_LDRS_SB_G1", /* name */
1213 false, /* partial_inplace */
1214 0xffffffff, /* src_mask */
1215 0xffffffff, /* dst_mask */
1216 true), /* pcrel_offset */
1217
1218 HOWTO (R_ARM_LDRS_SB_G2, /* type */
1219 0, /* rightshift */
1220 4, /* size */
1221 32, /* bitsize */
1222 true, /* pc_relative */
1223 0, /* bitpos */
1224 complain_overflow_dont,/* complain_on_overflow */
1225 bfd_elf_generic_reloc, /* special_function */
1226 "R_ARM_LDRS_SB_G2", /* name */
1227 false, /* partial_inplace */
1228 0xffffffff, /* src_mask */
1229 0xffffffff, /* dst_mask */
1230 true), /* pcrel_offset */
1231
1232 HOWTO (R_ARM_LDC_SB_G0, /* type */
1233 0, /* rightshift */
1234 4, /* size */
1235 32, /* bitsize */
1236 true, /* pc_relative */
1237 0, /* bitpos */
1238 complain_overflow_dont,/* complain_on_overflow */
1239 bfd_elf_generic_reloc, /* special_function */
1240 "R_ARM_LDC_SB_G0", /* name */
1241 false, /* partial_inplace */
1242 0xffffffff, /* src_mask */
1243 0xffffffff, /* dst_mask */
1244 true), /* pcrel_offset */
1245
1246 HOWTO (R_ARM_LDC_SB_G1, /* type */
1247 0, /* rightshift */
1248 4, /* size */
1249 32, /* bitsize */
1250 true, /* pc_relative */
1251 0, /* bitpos */
1252 complain_overflow_dont,/* complain_on_overflow */
1253 bfd_elf_generic_reloc, /* special_function */
1254 "R_ARM_LDC_SB_G1", /* name */
1255 false, /* partial_inplace */
1256 0xffffffff, /* src_mask */
1257 0xffffffff, /* dst_mask */
1258 true), /* pcrel_offset */
1259
1260 HOWTO (R_ARM_LDC_SB_G2, /* type */
1261 0, /* rightshift */
1262 4, /* size */
1263 32, /* bitsize */
1264 true, /* pc_relative */
1265 0, /* bitpos */
1266 complain_overflow_dont,/* complain_on_overflow */
1267 bfd_elf_generic_reloc, /* special_function */
1268 "R_ARM_LDC_SB_G2", /* name */
1269 false, /* partial_inplace */
1270 0xffffffff, /* src_mask */
1271 0xffffffff, /* dst_mask */
1272 true), /* pcrel_offset */
1273
1274 /* End of group relocations. */
1275
1276 HOWTO (R_ARM_MOVW_BREL_NC, /* type */
1277 0, /* rightshift */
1278 4, /* size */
1279 16, /* bitsize */
1280 false, /* pc_relative */
1281 0, /* bitpos */
1282 complain_overflow_dont,/* complain_on_overflow */
1283 bfd_elf_generic_reloc, /* special_function */
1284 "R_ARM_MOVW_BREL_NC", /* name */
1285 false, /* partial_inplace */
1286 0x0000ffff, /* src_mask */
1287 0x0000ffff, /* dst_mask */
1288 false), /* pcrel_offset */
1289
1290 HOWTO (R_ARM_MOVT_BREL, /* type */
1291 0, /* rightshift */
1292 4, /* size */
1293 16, /* bitsize */
1294 false, /* pc_relative */
1295 0, /* bitpos */
1296 complain_overflow_bitfield,/* complain_on_overflow */
1297 bfd_elf_generic_reloc, /* special_function */
1298 "R_ARM_MOVT_BREL", /* name */
1299 false, /* partial_inplace */
1300 0x0000ffff, /* src_mask */
1301 0x0000ffff, /* dst_mask */
1302 false), /* pcrel_offset */
1303
1304 HOWTO (R_ARM_MOVW_BREL, /* type */
1305 0, /* rightshift */
1306 4, /* size */
1307 16, /* bitsize */
1308 false, /* pc_relative */
1309 0, /* bitpos */
1310 complain_overflow_dont,/* complain_on_overflow */
1311 bfd_elf_generic_reloc, /* special_function */
1312 "R_ARM_MOVW_BREL", /* name */
1313 false, /* partial_inplace */
1314 0x0000ffff, /* src_mask */
1315 0x0000ffff, /* dst_mask */
1316 false), /* pcrel_offset */
1317
1318 HOWTO (R_ARM_THM_MOVW_BREL_NC,/* type */
1319 0, /* rightshift */
1320 4, /* size */
1321 16, /* bitsize */
1322 false, /* pc_relative */
1323 0, /* bitpos */
1324 complain_overflow_dont,/* complain_on_overflow */
1325 bfd_elf_generic_reloc, /* special_function */
1326 "R_ARM_THM_MOVW_BREL_NC",/* name */
1327 false, /* partial_inplace */
1328 0x040f70ff, /* src_mask */
1329 0x040f70ff, /* dst_mask */
1330 false), /* pcrel_offset */
1331
1332 HOWTO (R_ARM_THM_MOVT_BREL, /* type */
1333 0, /* rightshift */
1334 4, /* size */
1335 16, /* bitsize */
1336 false, /* pc_relative */
1337 0, /* bitpos */
1338 complain_overflow_bitfield,/* complain_on_overflow */
1339 bfd_elf_generic_reloc, /* special_function */
1340 "R_ARM_THM_MOVT_BREL", /* name */
1341 false, /* partial_inplace */
1342 0x040f70ff, /* src_mask */
1343 0x040f70ff, /* dst_mask */
1344 false), /* pcrel_offset */
1345
1346 HOWTO (R_ARM_THM_MOVW_BREL, /* type */
1347 0, /* rightshift */
1348 4, /* size */
1349 16, /* bitsize */
1350 false, /* pc_relative */
1351 0, /* bitpos */
1352 complain_overflow_dont,/* complain_on_overflow */
1353 bfd_elf_generic_reloc, /* special_function */
1354 "R_ARM_THM_MOVW_BREL", /* name */
1355 false, /* partial_inplace */
1356 0x040f70ff, /* src_mask */
1357 0x040f70ff, /* dst_mask */
1358 false), /* pcrel_offset */
1359
1360 HOWTO (R_ARM_TLS_GOTDESC, /* type */
1361 0, /* rightshift */
1362 4, /* size */
1363 32, /* bitsize */
1364 false, /* pc_relative */
1365 0, /* bitpos */
1366 complain_overflow_bitfield,/* complain_on_overflow */
1367 NULL, /* special_function */
1368 "R_ARM_TLS_GOTDESC", /* name */
1369 true, /* partial_inplace */
1370 0xffffffff, /* src_mask */
1371 0xffffffff, /* dst_mask */
1372 false), /* pcrel_offset */
1373
1374 HOWTO (R_ARM_TLS_CALL, /* type */
1375 0, /* rightshift */
1376 4, /* size */
1377 24, /* bitsize */
1378 false, /* pc_relative */
1379 0, /* bitpos */
1380 complain_overflow_dont,/* complain_on_overflow */
1381 bfd_elf_generic_reloc, /* special_function */
1382 "R_ARM_TLS_CALL", /* name */
1383 false, /* partial_inplace */
1384 0x00ffffff, /* src_mask */
1385 0x00ffffff, /* dst_mask */
1386 false), /* pcrel_offset */
1387
1388 HOWTO (R_ARM_TLS_DESCSEQ, /* type */
1389 0, /* rightshift */
1390 4, /* size */
1391 0, /* bitsize */
1392 false, /* pc_relative */
1393 0, /* bitpos */
1394 complain_overflow_dont,/* complain_on_overflow */
1395 bfd_elf_generic_reloc, /* special_function */
1396 "R_ARM_TLS_DESCSEQ", /* name */
1397 false, /* partial_inplace */
1398 0x00000000, /* src_mask */
1399 0x00000000, /* dst_mask */
1400 false), /* pcrel_offset */
1401
1402 HOWTO (R_ARM_THM_TLS_CALL, /* type */
1403 0, /* rightshift */
1404 4, /* size */
1405 24, /* bitsize */
1406 false, /* pc_relative */
1407 0, /* bitpos */
1408 complain_overflow_dont,/* complain_on_overflow */
1409 bfd_elf_generic_reloc, /* special_function */
1410 "R_ARM_THM_TLS_CALL", /* name */
1411 false, /* partial_inplace */
1412 0x07ff07ff, /* src_mask */
1413 0x07ff07ff, /* dst_mask */
1414 false), /* pcrel_offset */
1415
1416 HOWTO (R_ARM_PLT32_ABS, /* type */
1417 0, /* rightshift */
1418 4, /* size */
1419 32, /* bitsize */
1420 false, /* pc_relative */
1421 0, /* bitpos */
1422 complain_overflow_dont,/* complain_on_overflow */
1423 bfd_elf_generic_reloc, /* special_function */
1424 "R_ARM_PLT32_ABS", /* name */
1425 false, /* partial_inplace */
1426 0xffffffff, /* src_mask */
1427 0xffffffff, /* dst_mask */
1428 false), /* pcrel_offset */
1429
1430 HOWTO (R_ARM_GOT_ABS, /* type */
1431 0, /* rightshift */
1432 4, /* size */
1433 32, /* bitsize */
1434 false, /* pc_relative */
1435 0, /* bitpos */
1436 complain_overflow_dont,/* complain_on_overflow */
1437 bfd_elf_generic_reloc, /* special_function */
1438 "R_ARM_GOT_ABS", /* name */
1439 false, /* partial_inplace */
1440 0xffffffff, /* src_mask */
1441 0xffffffff, /* dst_mask */
1442 false), /* pcrel_offset */
1443
1444 HOWTO (R_ARM_GOT_PREL, /* type */
1445 0, /* rightshift */
1446 4, /* size */
1447 32, /* bitsize */
1448 true, /* pc_relative */
1449 0, /* bitpos */
1450 complain_overflow_dont, /* complain_on_overflow */
1451 bfd_elf_generic_reloc, /* special_function */
1452 "R_ARM_GOT_PREL", /* name */
1453 false, /* partial_inplace */
1454 0xffffffff, /* src_mask */
1455 0xffffffff, /* dst_mask */
1456 true), /* pcrel_offset */
1457
1458 HOWTO (R_ARM_GOT_BREL12, /* type */
1459 0, /* rightshift */
1460 4, /* size */
1461 12, /* bitsize */
1462 false, /* pc_relative */
1463 0, /* bitpos */
1464 complain_overflow_bitfield,/* complain_on_overflow */
1465 bfd_elf_generic_reloc, /* special_function */
1466 "R_ARM_GOT_BREL12", /* name */
1467 false, /* partial_inplace */
1468 0x00000fff, /* src_mask */
1469 0x00000fff, /* dst_mask */
1470 false), /* pcrel_offset */
1471
1472 HOWTO (R_ARM_GOTOFF12, /* type */
1473 0, /* rightshift */
1474 4, /* size */
1475 12, /* bitsize */
1476 false, /* pc_relative */
1477 0, /* bitpos */
1478 complain_overflow_bitfield,/* complain_on_overflow */
1479 bfd_elf_generic_reloc, /* special_function */
1480 "R_ARM_GOTOFF12", /* name */
1481 false, /* partial_inplace */
1482 0x00000fff, /* src_mask */
1483 0x00000fff, /* dst_mask */
1484 false), /* pcrel_offset */
1485
1486 EMPTY_HOWTO (R_ARM_GOTRELAX), /* reserved for future GOT-load optimizations */
1487
1488 /* GNU extension to record C++ vtable member usage */
1489 HOWTO (R_ARM_GNU_VTENTRY, /* type */
1490 0, /* rightshift */
1491 4, /* size */
1492 0, /* bitsize */
1493 false, /* pc_relative */
1494 0, /* bitpos */
1495 complain_overflow_dont, /* complain_on_overflow */
1496 _bfd_elf_rel_vtable_reloc_fn, /* special_function */
1497 "R_ARM_GNU_VTENTRY", /* name */
1498 false, /* partial_inplace */
1499 0, /* src_mask */
1500 0, /* dst_mask */
1501 false), /* pcrel_offset */
1502
1503 /* GNU extension to record C++ vtable hierarchy */
1504 HOWTO (R_ARM_GNU_VTINHERIT, /* type */
1505 0, /* rightshift */
1506 4, /* size */
1507 0, /* bitsize */
1508 false, /* pc_relative */
1509 0, /* bitpos */
1510 complain_overflow_dont, /* complain_on_overflow */
1511 NULL, /* special_function */
1512 "R_ARM_GNU_VTINHERIT", /* name */
1513 false, /* partial_inplace */
1514 0, /* src_mask */
1515 0, /* dst_mask */
1516 false), /* pcrel_offset */
1517
1518 HOWTO (R_ARM_THM_JUMP11, /* type */
1519 1, /* rightshift */
1520 2, /* size */
1521 11, /* bitsize */
1522 true, /* pc_relative */
1523 0, /* bitpos */
1524 complain_overflow_signed, /* complain_on_overflow */
1525 bfd_elf_generic_reloc, /* special_function */
1526 "R_ARM_THM_JUMP11", /* name */
1527 false, /* partial_inplace */
1528 0x000007ff, /* src_mask */
1529 0x000007ff, /* dst_mask */
1530 true), /* pcrel_offset */
1531
1532 HOWTO (R_ARM_THM_JUMP8, /* type */
1533 1, /* rightshift */
1534 2, /* size */
1535 8, /* bitsize */
1536 true, /* pc_relative */
1537 0, /* bitpos */
1538 complain_overflow_signed, /* complain_on_overflow */
1539 bfd_elf_generic_reloc, /* special_function */
1540 "R_ARM_THM_JUMP8", /* name */
1541 false, /* partial_inplace */
1542 0x000000ff, /* src_mask */
1543 0x000000ff, /* dst_mask */
1544 true), /* pcrel_offset */
1545
1546 /* TLS relocations */
1547 HOWTO (R_ARM_TLS_GD32, /* type */
1548 0, /* rightshift */
1549 4, /* size */
1550 32, /* bitsize */
1551 false, /* pc_relative */
1552 0, /* bitpos */
1553 complain_overflow_bitfield,/* complain_on_overflow */
1554 NULL, /* special_function */
1555 "R_ARM_TLS_GD32", /* name */
1556 true, /* partial_inplace */
1557 0xffffffff, /* src_mask */
1558 0xffffffff, /* dst_mask */
1559 false), /* pcrel_offset */
1560
1561 HOWTO (R_ARM_TLS_LDM32, /* type */
1562 0, /* rightshift */
1563 4, /* size */
1564 32, /* bitsize */
1565 false, /* pc_relative */
1566 0, /* bitpos */
1567 complain_overflow_bitfield,/* complain_on_overflow */
1568 bfd_elf_generic_reloc, /* special_function */
1569 "R_ARM_TLS_LDM32", /* name */
1570 true, /* partial_inplace */
1571 0xffffffff, /* src_mask */
1572 0xffffffff, /* dst_mask */
1573 false), /* pcrel_offset */
1574
1575 HOWTO (R_ARM_TLS_LDO32, /* type */
1576 0, /* rightshift */
1577 4, /* size */
1578 32, /* bitsize */
1579 false, /* pc_relative */
1580 0, /* bitpos */
1581 complain_overflow_bitfield,/* complain_on_overflow */
1582 bfd_elf_generic_reloc, /* special_function */
1583 "R_ARM_TLS_LDO32", /* name */
1584 true, /* partial_inplace */
1585 0xffffffff, /* src_mask */
1586 0xffffffff, /* dst_mask */
1587 false), /* pcrel_offset */
1588
1589 HOWTO (R_ARM_TLS_IE32, /* type */
1590 0, /* rightshift */
1591 4, /* size */
1592 32, /* bitsize */
1593 false, /* pc_relative */
1594 0, /* bitpos */
1595 complain_overflow_bitfield,/* complain_on_overflow */
1596 NULL, /* special_function */
1597 "R_ARM_TLS_IE32", /* name */
1598 true, /* partial_inplace */
1599 0xffffffff, /* src_mask */
1600 0xffffffff, /* dst_mask */
1601 false), /* pcrel_offset */
1602
1603 HOWTO (R_ARM_TLS_LE32, /* type */
1604 0, /* rightshift */
1605 4, /* size */
1606 32, /* bitsize */
1607 false, /* pc_relative */
1608 0, /* bitpos */
1609 complain_overflow_bitfield,/* complain_on_overflow */
1610 NULL, /* special_function */
1611 "R_ARM_TLS_LE32", /* name */
1612 true, /* partial_inplace */
1613 0xffffffff, /* src_mask */
1614 0xffffffff, /* dst_mask */
1615 false), /* pcrel_offset */
1616
1617 HOWTO (R_ARM_TLS_LDO12, /* type */
1618 0, /* rightshift */
1619 4, /* size */
1620 12, /* bitsize */
1621 false, /* pc_relative */
1622 0, /* bitpos */
1623 complain_overflow_bitfield,/* complain_on_overflow */
1624 bfd_elf_generic_reloc, /* special_function */
1625 "R_ARM_TLS_LDO12", /* name */
1626 false, /* partial_inplace */
1627 0x00000fff, /* src_mask */
1628 0x00000fff, /* dst_mask */
1629 false), /* pcrel_offset */
1630
1631 HOWTO (R_ARM_TLS_LE12, /* type */
1632 0, /* rightshift */
1633 4, /* size */
1634 12, /* bitsize */
1635 false, /* pc_relative */
1636 0, /* bitpos */
1637 complain_overflow_bitfield,/* complain_on_overflow */
1638 bfd_elf_generic_reloc, /* special_function */
1639 "R_ARM_TLS_LE12", /* name */
1640 false, /* partial_inplace */
1641 0x00000fff, /* src_mask */
1642 0x00000fff, /* dst_mask */
1643 false), /* pcrel_offset */
1644
1645 HOWTO (R_ARM_TLS_IE12GP, /* type */
1646 0, /* rightshift */
1647 4, /* size */
1648 12, /* bitsize */
1649 false, /* pc_relative */
1650 0, /* bitpos */
1651 complain_overflow_bitfield,/* complain_on_overflow */
1652 bfd_elf_generic_reloc, /* special_function */
1653 "R_ARM_TLS_IE12GP", /* name */
1654 false, /* partial_inplace */
1655 0x00000fff, /* src_mask */
1656 0x00000fff, /* dst_mask */
1657 false), /* pcrel_offset */
1658
1659 /* 112-127 private relocations. */
1660 EMPTY_HOWTO (112),
1661 EMPTY_HOWTO (113),
1662 EMPTY_HOWTO (114),
1663 EMPTY_HOWTO (115),
1664 EMPTY_HOWTO (116),
1665 EMPTY_HOWTO (117),
1666 EMPTY_HOWTO (118),
1667 EMPTY_HOWTO (119),
1668 EMPTY_HOWTO (120),
1669 EMPTY_HOWTO (121),
1670 EMPTY_HOWTO (122),
1671 EMPTY_HOWTO (123),
1672 EMPTY_HOWTO (124),
1673 EMPTY_HOWTO (125),
1674 EMPTY_HOWTO (126),
1675 EMPTY_HOWTO (127),
1676
1677 /* R_ARM_ME_TOO, obsolete. */
1678 EMPTY_HOWTO (128),
1679
1680 HOWTO (R_ARM_THM_TLS_DESCSEQ, /* type */
1681 0, /* rightshift */
1682 2, /* size */
1683 0, /* bitsize */
1684 false, /* pc_relative */
1685 0, /* bitpos */
1686 complain_overflow_dont,/* complain_on_overflow */
1687 bfd_elf_generic_reloc, /* special_function */
1688 "R_ARM_THM_TLS_DESCSEQ",/* name */
1689 false, /* partial_inplace */
1690 0x00000000, /* src_mask */
1691 0x00000000, /* dst_mask */
1692 false), /* pcrel_offset */
1693 EMPTY_HOWTO (130),
1694 EMPTY_HOWTO (131),
1695 HOWTO (R_ARM_THM_ALU_ABS_G0_NC,/* type. */
1696 0, /* rightshift. */
1697 2, /* size. */
1698 16, /* bitsize. */
1699 false, /* pc_relative. */
1700 0, /* bitpos. */
1701 complain_overflow_bitfield,/* complain_on_overflow. */
1702 bfd_elf_generic_reloc, /* special_function. */
1703 "R_ARM_THM_ALU_ABS_G0_NC",/* name. */
1704 false, /* partial_inplace. */
1705 0x00000000, /* src_mask. */
1706 0x00000000, /* dst_mask. */
1707 false), /* pcrel_offset. */
1708 HOWTO (R_ARM_THM_ALU_ABS_G1_NC,/* type. */
1709 0, /* rightshift. */
1710 2, /* size. */
1711 16, /* bitsize. */
1712 false, /* pc_relative. */
1713 0, /* bitpos. */
1714 complain_overflow_bitfield,/* complain_on_overflow. */
1715 bfd_elf_generic_reloc, /* special_function. */
1716 "R_ARM_THM_ALU_ABS_G1_NC",/* name. */
1717 false, /* partial_inplace. */
1718 0x00000000, /* src_mask. */
1719 0x00000000, /* dst_mask. */
1720 false), /* pcrel_offset. */
1721 HOWTO (R_ARM_THM_ALU_ABS_G2_NC,/* type. */
1722 0, /* rightshift. */
1723 2, /* size. */
1724 16, /* bitsize. */
1725 false, /* pc_relative. */
1726 0, /* bitpos. */
1727 complain_overflow_bitfield,/* complain_on_overflow. */
1728 bfd_elf_generic_reloc, /* special_function. */
1729 "R_ARM_THM_ALU_ABS_G2_NC",/* name. */
1730 false, /* partial_inplace. */
1731 0x00000000, /* src_mask. */
1732 0x00000000, /* dst_mask. */
1733 false), /* pcrel_offset. */
1734 HOWTO (R_ARM_THM_ALU_ABS_G3_NC,/* type. */
1735 0, /* rightshift. */
1736 2, /* size. */
1737 16, /* bitsize. */
1738 false, /* pc_relative. */
1739 0, /* bitpos. */
1740 complain_overflow_bitfield,/* complain_on_overflow. */
1741 bfd_elf_generic_reloc, /* special_function. */
1742 "R_ARM_THM_ALU_ABS_G3_NC",/* name. */
1743 false, /* partial_inplace. */
1744 0x00000000, /* src_mask. */
1745 0x00000000, /* dst_mask. */
1746 false), /* pcrel_offset. */
1747 /* Relocations for Armv8.1-M Mainline. */
1748 HOWTO (R_ARM_THM_BF16, /* type. */
1749 0, /* rightshift. */
1750 2, /* size. */
1751 16, /* bitsize. */
1752 true, /* pc_relative. */
1753 0, /* bitpos. */
1754 complain_overflow_dont,/* do not complain_on_overflow. */
1755 bfd_elf_generic_reloc, /* special_function. */
1756 "R_ARM_THM_BF16", /* name. */
1757 false, /* partial_inplace. */
1758 0x001f0ffe, /* src_mask. */
1759 0x001f0ffe, /* dst_mask. */
1760 true), /* pcrel_offset. */
1761 HOWTO (R_ARM_THM_BF12, /* type. */
1762 0, /* rightshift. */
1763 2, /* size. */
1764 12, /* bitsize. */
1765 true, /* pc_relative. */
1766 0, /* bitpos. */
1767 complain_overflow_dont,/* do not complain_on_overflow. */
1768 bfd_elf_generic_reloc, /* special_function. */
1769 "R_ARM_THM_BF12", /* name. */
1770 false, /* partial_inplace. */
1771 0x00010ffe, /* src_mask. */
1772 0x00010ffe, /* dst_mask. */
1773 true), /* pcrel_offset. */
1774 HOWTO (R_ARM_THM_BF18, /* type. */
1775 0, /* rightshift. */
1776 2, /* size. */
1777 18, /* bitsize. */
1778 true, /* pc_relative. */
1779 0, /* bitpos. */
1780 complain_overflow_dont,/* do not complain_on_overflow. */
1781 bfd_elf_generic_reloc, /* special_function. */
1782 "R_ARM_THM_BF18", /* name. */
1783 false, /* partial_inplace. */
1784 0x007f0ffe, /* src_mask. */
1785 0x007f0ffe, /* dst_mask. */
1786 true), /* pcrel_offset. */
1787 };
1788
1789 /* 160 onwards: */
1790 static reloc_howto_type elf32_arm_howto_table_2[8] =
1791 {
1792 HOWTO (R_ARM_IRELATIVE, /* type */
1793 0, /* rightshift */
1794 4, /* size */
1795 32, /* bitsize */
1796 false, /* pc_relative */
1797 0, /* bitpos */
1798 complain_overflow_bitfield,/* complain_on_overflow */
1799 bfd_elf_generic_reloc, /* special_function */
1800 "R_ARM_IRELATIVE", /* name */
1801 true, /* partial_inplace */
1802 0xffffffff, /* src_mask */
1803 0xffffffff, /* dst_mask */
1804 false), /* pcrel_offset */
1805 HOWTO (R_ARM_GOTFUNCDESC, /* type */
1806 0, /* rightshift */
1807 4, /* size */
1808 32, /* bitsize */
1809 false, /* pc_relative */
1810 0, /* bitpos */
1811 complain_overflow_bitfield,/* complain_on_overflow */
1812 bfd_elf_generic_reloc, /* special_function */
1813 "R_ARM_GOTFUNCDESC", /* name */
1814 false, /* partial_inplace */
1815 0, /* src_mask */
1816 0xffffffff, /* dst_mask */
1817 false), /* pcrel_offset */
1818 HOWTO (R_ARM_GOTOFFFUNCDESC, /* type */
1819 0, /* rightshift */
1820 4, /* size */
1821 32, /* bitsize */
1822 false, /* pc_relative */
1823 0, /* bitpos */
1824 complain_overflow_bitfield,/* complain_on_overflow */
1825 bfd_elf_generic_reloc, /* special_function */
1826 "R_ARM_GOTOFFFUNCDESC",/* name */
1827 false, /* partial_inplace */
1828 0, /* src_mask */
1829 0xffffffff, /* dst_mask */
1830 false), /* pcrel_offset */
1831 HOWTO (R_ARM_FUNCDESC, /* type */
1832 0, /* rightshift */
1833 4, /* size */
1834 32, /* bitsize */
1835 false, /* pc_relative */
1836 0, /* bitpos */
1837 complain_overflow_bitfield,/* complain_on_overflow */
1838 bfd_elf_generic_reloc, /* special_function */
1839 "R_ARM_FUNCDESC", /* name */
1840 false, /* partial_inplace */
1841 0, /* src_mask */
1842 0xffffffff, /* dst_mask */
1843 false), /* pcrel_offset */
1844 HOWTO (R_ARM_FUNCDESC_VALUE, /* type */
1845 0, /* rightshift */
1846 4, /* size */
1847 64, /* bitsize */
1848 false, /* pc_relative */
1849 0, /* bitpos */
1850 complain_overflow_bitfield,/* complain_on_overflow */
1851 bfd_elf_generic_reloc, /* special_function */
1852 "R_ARM_FUNCDESC_VALUE",/* name */
1853 false, /* partial_inplace */
1854 0, /* src_mask */
1855 0xffffffff, /* dst_mask */
1856 false), /* pcrel_offset */
1857 HOWTO (R_ARM_TLS_GD32_FDPIC, /* type */
1858 0, /* rightshift */
1859 4, /* size */
1860 32, /* bitsize */
1861 false, /* pc_relative */
1862 0, /* bitpos */
1863 complain_overflow_bitfield,/* complain_on_overflow */
1864 bfd_elf_generic_reloc, /* special_function */
1865 "R_ARM_TLS_GD32_FDPIC",/* name */
1866 false, /* partial_inplace */
1867 0, /* src_mask */
1868 0xffffffff, /* dst_mask */
1869 false), /* pcrel_offset */
1870 HOWTO (R_ARM_TLS_LDM32_FDPIC, /* type */
1871 0, /* rightshift */
1872 4, /* size */
1873 32, /* bitsize */
1874 false, /* pc_relative */
1875 0, /* bitpos */
1876 complain_overflow_bitfield,/* complain_on_overflow */
1877 bfd_elf_generic_reloc, /* special_function */
1878 "R_ARM_TLS_LDM32_FDPIC",/* name */
1879 false, /* partial_inplace */
1880 0, /* src_mask */
1881 0xffffffff, /* dst_mask */
1882 false), /* pcrel_offset */
1883 HOWTO (R_ARM_TLS_IE32_FDPIC, /* type */
1884 0, /* rightshift */
1885 4, /* size */
1886 32, /* bitsize */
1887 false, /* pc_relative */
1888 0, /* bitpos */
1889 complain_overflow_bitfield,/* complain_on_overflow */
1890 bfd_elf_generic_reloc, /* special_function */
1891 "R_ARM_TLS_IE32_FDPIC",/* name */
1892 false, /* partial_inplace */
1893 0, /* src_mask */
1894 0xffffffff, /* dst_mask */
1895 false), /* pcrel_offset */
1896 };
1897
1898 /* 249-255 extended, currently unused, relocations: */
1899 static reloc_howto_type elf32_arm_howto_table_3[4] =
1900 {
1901 HOWTO (R_ARM_RREL32, /* type */
1902 0, /* rightshift */
1903 0, /* size */
1904 0, /* bitsize */
1905 false, /* pc_relative */
1906 0, /* bitpos */
1907 complain_overflow_dont,/* complain_on_overflow */
1908 bfd_elf_generic_reloc, /* special_function */
1909 "R_ARM_RREL32", /* name */
1910 false, /* partial_inplace */
1911 0, /* src_mask */
1912 0, /* dst_mask */
1913 false), /* pcrel_offset */
1914
1915 HOWTO (R_ARM_RABS32, /* type */
1916 0, /* rightshift */
1917 0, /* size */
1918 0, /* bitsize */
1919 false, /* pc_relative */
1920 0, /* bitpos */
1921 complain_overflow_dont,/* complain_on_overflow */
1922 bfd_elf_generic_reloc, /* special_function */
1923 "R_ARM_RABS32", /* name */
1924 false, /* partial_inplace */
1925 0, /* src_mask */
1926 0, /* dst_mask */
1927 false), /* pcrel_offset */
1928
1929 HOWTO (R_ARM_RPC24, /* type */
1930 0, /* rightshift */
1931 0, /* size */
1932 0, /* bitsize */
1933 false, /* pc_relative */
1934 0, /* bitpos */
1935 complain_overflow_dont,/* complain_on_overflow */
1936 bfd_elf_generic_reloc, /* special_function */
1937 "R_ARM_RPC24", /* name */
1938 false, /* partial_inplace */
1939 0, /* src_mask */
1940 0, /* dst_mask */
1941 false), /* pcrel_offset */
1942
1943 HOWTO (R_ARM_RBASE, /* type */
1944 0, /* rightshift */
1945 0, /* size */
1946 0, /* bitsize */
1947 false, /* pc_relative */
1948 0, /* bitpos */
1949 complain_overflow_dont,/* complain_on_overflow */
1950 bfd_elf_generic_reloc, /* special_function */
1951 "R_ARM_RBASE", /* name */
1952 false, /* partial_inplace */
1953 0, /* src_mask */
1954 0, /* dst_mask */
1955 false) /* pcrel_offset */
1956 };
1957
1958 static reloc_howto_type *
1959 elf32_arm_howto_from_type (unsigned int r_type)
1960 {
1961 if (r_type < ARRAY_SIZE (elf32_arm_howto_table_1))
1962 return &elf32_arm_howto_table_1[r_type];
1963
1964 if (r_type >= R_ARM_IRELATIVE
1965 && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2))
1966 return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE];
1967
1968 if (r_type >= R_ARM_RREL32
1969 && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3))
1970 return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32];
1971
1972 return NULL;
1973 }
1974
1975 static bool
1976 elf32_arm_info_to_howto (bfd * abfd, arelent * bfd_reloc,
1977 Elf_Internal_Rela * elf_reloc)
1978 {
1979 unsigned int r_type;
1980
1981 r_type = ELF32_R_TYPE (elf_reloc->r_info);
1982 if ((bfd_reloc->howto = elf32_arm_howto_from_type (r_type)) == NULL)
1983 {
1984 /* xgettext:c-format */
1985 _bfd_error_handler (_("%pB: unsupported relocation type %#x"),
1986 abfd, r_type);
1987 bfd_set_error (bfd_error_bad_value);
1988 return false;
1989 }
1990 return true;
1991 }
1992
1993 struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
1996 unsigned char elf_reloc_val;
1997 };
1998
1999 /* All entries in this list must also be present in elf32_arm_howto_table. */
2000 static const struct elf32_arm_reloc_map elf32_arm_reloc_map[] =
2001 {
2002 {BFD_RELOC_NONE, R_ARM_NONE},
2003 {BFD_RELOC_ARM_PCREL_BRANCH, R_ARM_PC24},
2004 {BFD_RELOC_ARM_PCREL_CALL, R_ARM_CALL},
2005 {BFD_RELOC_ARM_PCREL_JUMP, R_ARM_JUMP24},
2006 {BFD_RELOC_ARM_PCREL_BLX, R_ARM_XPC25},
2007 {BFD_RELOC_THUMB_PCREL_BLX, R_ARM_THM_XPC22},
2008 {BFD_RELOC_32, R_ARM_ABS32},
2009 {BFD_RELOC_32_PCREL, R_ARM_REL32},
2010 {BFD_RELOC_8, R_ARM_ABS8},
2011 {BFD_RELOC_16, R_ARM_ABS16},
2012 {BFD_RELOC_ARM_OFFSET_IMM, R_ARM_ABS12},
2013 {BFD_RELOC_ARM_THUMB_OFFSET, R_ARM_THM_ABS5},
2014 {BFD_RELOC_THUMB_PCREL_BRANCH25, R_ARM_THM_JUMP24},
2015 {BFD_RELOC_THUMB_PCREL_BRANCH23, R_ARM_THM_CALL},
2016 {BFD_RELOC_THUMB_PCREL_BRANCH12, R_ARM_THM_JUMP11},
2017 {BFD_RELOC_THUMB_PCREL_BRANCH20, R_ARM_THM_JUMP19},
2018 {BFD_RELOC_THUMB_PCREL_BRANCH9, R_ARM_THM_JUMP8},
2019 {BFD_RELOC_THUMB_PCREL_BRANCH7, R_ARM_THM_JUMP6},
2020 {BFD_RELOC_ARM_GLOB_DAT, R_ARM_GLOB_DAT},
2021 {BFD_RELOC_ARM_JUMP_SLOT, R_ARM_JUMP_SLOT},
2022 {BFD_RELOC_ARM_RELATIVE, R_ARM_RELATIVE},
2023 {BFD_RELOC_ARM_GOTOFF, R_ARM_GOTOFF32},
2024 {BFD_RELOC_ARM_GOTPC, R_ARM_GOTPC},
2025 {BFD_RELOC_ARM_GOT_PREL, R_ARM_GOT_PREL},
2026 {BFD_RELOC_ARM_GOT32, R_ARM_GOT32},
2027 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2028 {BFD_RELOC_ARM_TARGET1, R_ARM_TARGET1},
2029 {BFD_RELOC_ARM_ROSEGREL32, R_ARM_ROSEGREL32},
2030 {BFD_RELOC_ARM_SBREL32, R_ARM_SBREL32},
2031 {BFD_RELOC_ARM_PREL31, R_ARM_PREL31},
2032 {BFD_RELOC_ARM_TARGET2, R_ARM_TARGET2},
2033 {BFD_RELOC_ARM_PLT32, R_ARM_PLT32},
2034 {BFD_RELOC_ARM_TLS_GOTDESC, R_ARM_TLS_GOTDESC},
2035 {BFD_RELOC_ARM_TLS_CALL, R_ARM_TLS_CALL},
2036 {BFD_RELOC_ARM_THM_TLS_CALL, R_ARM_THM_TLS_CALL},
2037 {BFD_RELOC_ARM_TLS_DESCSEQ, R_ARM_TLS_DESCSEQ},
2038 {BFD_RELOC_ARM_THM_TLS_DESCSEQ, R_ARM_THM_TLS_DESCSEQ},
2039 {BFD_RELOC_ARM_TLS_DESC, R_ARM_TLS_DESC},
2040 {BFD_RELOC_ARM_TLS_GD32, R_ARM_TLS_GD32},
2041 {BFD_RELOC_ARM_TLS_LDO32, R_ARM_TLS_LDO32},
2042 {BFD_RELOC_ARM_TLS_LDM32, R_ARM_TLS_LDM32},
2043 {BFD_RELOC_ARM_TLS_DTPMOD32, R_ARM_TLS_DTPMOD32},
2044 {BFD_RELOC_ARM_TLS_DTPOFF32, R_ARM_TLS_DTPOFF32},
2045 {BFD_RELOC_ARM_TLS_TPOFF32, R_ARM_TLS_TPOFF32},
2046 {BFD_RELOC_ARM_TLS_IE32, R_ARM_TLS_IE32},
2047 {BFD_RELOC_ARM_TLS_LE32, R_ARM_TLS_LE32},
2048 {BFD_RELOC_ARM_IRELATIVE, R_ARM_IRELATIVE},
2049 {BFD_RELOC_ARM_GOTFUNCDESC, R_ARM_GOTFUNCDESC},
2050 {BFD_RELOC_ARM_GOTOFFFUNCDESC, R_ARM_GOTOFFFUNCDESC},
2051 {BFD_RELOC_ARM_FUNCDESC, R_ARM_FUNCDESC},
2052 {BFD_RELOC_ARM_FUNCDESC_VALUE, R_ARM_FUNCDESC_VALUE},
2053 {BFD_RELOC_ARM_TLS_GD32_FDPIC, R_ARM_TLS_GD32_FDPIC},
2054 {BFD_RELOC_ARM_TLS_LDM32_FDPIC, R_ARM_TLS_LDM32_FDPIC},
2055 {BFD_RELOC_ARM_TLS_IE32_FDPIC, R_ARM_TLS_IE32_FDPIC},
2056 {BFD_RELOC_VTABLE_INHERIT, R_ARM_GNU_VTINHERIT},
2057 {BFD_RELOC_VTABLE_ENTRY, R_ARM_GNU_VTENTRY},
2058 {BFD_RELOC_ARM_MOVW, R_ARM_MOVW_ABS_NC},
2059 {BFD_RELOC_ARM_MOVT, R_ARM_MOVT_ABS},
2060 {BFD_RELOC_ARM_MOVW_PCREL, R_ARM_MOVW_PREL_NC},
2061 {BFD_RELOC_ARM_MOVT_PCREL, R_ARM_MOVT_PREL},
2062 {BFD_RELOC_ARM_THUMB_MOVW, R_ARM_THM_MOVW_ABS_NC},
2063 {BFD_RELOC_ARM_THUMB_MOVT, R_ARM_THM_MOVT_ABS},
2064 {BFD_RELOC_ARM_THUMB_MOVW_PCREL, R_ARM_THM_MOVW_PREL_NC},
2065 {BFD_RELOC_ARM_THUMB_MOVT_PCREL, R_ARM_THM_MOVT_PREL},
2066 {BFD_RELOC_ARM_ALU_PC_G0_NC, R_ARM_ALU_PC_G0_NC},
2067 {BFD_RELOC_ARM_ALU_PC_G0, R_ARM_ALU_PC_G0},
2068 {BFD_RELOC_ARM_ALU_PC_G1_NC, R_ARM_ALU_PC_G1_NC},
2069 {BFD_RELOC_ARM_ALU_PC_G1, R_ARM_ALU_PC_G1},
2070 {BFD_RELOC_ARM_ALU_PC_G2, R_ARM_ALU_PC_G2},
2071 {BFD_RELOC_ARM_LDR_PC_G0, R_ARM_LDR_PC_G0},
2072 {BFD_RELOC_ARM_LDR_PC_G1, R_ARM_LDR_PC_G1},
2073 {BFD_RELOC_ARM_LDR_PC_G2, R_ARM_LDR_PC_G2},
2074 {BFD_RELOC_ARM_LDRS_PC_G0, R_ARM_LDRS_PC_G0},
2075 {BFD_RELOC_ARM_LDRS_PC_G1, R_ARM_LDRS_PC_G1},
2076 {BFD_RELOC_ARM_LDRS_PC_G2, R_ARM_LDRS_PC_G2},
2077 {BFD_RELOC_ARM_LDC_PC_G0, R_ARM_LDC_PC_G0},
2078 {BFD_RELOC_ARM_LDC_PC_G1, R_ARM_LDC_PC_G1},
2079 {BFD_RELOC_ARM_LDC_PC_G2, R_ARM_LDC_PC_G2},
2080 {BFD_RELOC_ARM_ALU_SB_G0_NC, R_ARM_ALU_SB_G0_NC},
2081 {BFD_RELOC_ARM_ALU_SB_G0, R_ARM_ALU_SB_G0},
2082 {BFD_RELOC_ARM_ALU_SB_G1_NC, R_ARM_ALU_SB_G1_NC},
2083 {BFD_RELOC_ARM_ALU_SB_G1, R_ARM_ALU_SB_G1},
2084 {BFD_RELOC_ARM_ALU_SB_G2, R_ARM_ALU_SB_G2},
2085 {BFD_RELOC_ARM_LDR_SB_G0, R_ARM_LDR_SB_G0},
2086 {BFD_RELOC_ARM_LDR_SB_G1, R_ARM_LDR_SB_G1},
2087 {BFD_RELOC_ARM_LDR_SB_G2, R_ARM_LDR_SB_G2},
2088 {BFD_RELOC_ARM_LDRS_SB_G0, R_ARM_LDRS_SB_G0},
2089 {BFD_RELOC_ARM_LDRS_SB_G1, R_ARM_LDRS_SB_G1},
2090 {BFD_RELOC_ARM_LDRS_SB_G2, R_ARM_LDRS_SB_G2},
2091 {BFD_RELOC_ARM_LDC_SB_G0, R_ARM_LDC_SB_G0},
2092 {BFD_RELOC_ARM_LDC_SB_G1, R_ARM_LDC_SB_G1},
2093 {BFD_RELOC_ARM_LDC_SB_G2, R_ARM_LDC_SB_G2},
2094 {BFD_RELOC_ARM_V4BX, R_ARM_V4BX},
2095 {BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC, R_ARM_THM_ALU_ABS_G3_NC},
2096 {BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC, R_ARM_THM_ALU_ABS_G2_NC},
2097 {BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC, R_ARM_THM_ALU_ABS_G1_NC},
2098 {BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC, R_ARM_THM_ALU_ABS_G0_NC},
2099 {BFD_RELOC_ARM_THUMB_BF17, R_ARM_THM_BF16},
2100 {BFD_RELOC_ARM_THUMB_BF13, R_ARM_THM_BF12},
2101 {BFD_RELOC_ARM_THUMB_BF19, R_ARM_THM_BF18}
2102 };
2103
2104 static reloc_howto_type *
2105 elf32_arm_reloc_type_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2106 bfd_reloc_code_real_type code)
2107 {
2108 unsigned int i;
2109
2110 for (i = 0; i < ARRAY_SIZE (elf32_arm_reloc_map); i ++)
2111 if (elf32_arm_reloc_map[i].bfd_reloc_val == code)
2112 return elf32_arm_howto_from_type (elf32_arm_reloc_map[i].elf_reloc_val);
2113
2114 return NULL;
2115 }
2116
2117 static reloc_howto_type *
2118 elf32_arm_reloc_name_lookup (bfd *abfd ATTRIBUTE_UNUSED,
2119 const char *r_name)
2120 {
2121 unsigned int i;
2122
2123 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_1); i++)
2124 if (elf32_arm_howto_table_1[i].name != NULL
2125 && strcasecmp (elf32_arm_howto_table_1[i].name, r_name) == 0)
2126 return &elf32_arm_howto_table_1[i];
2127
2128 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_2); i++)
2129 if (elf32_arm_howto_table_2[i].name != NULL
2130 && strcasecmp (elf32_arm_howto_table_2[i].name, r_name) == 0)
2131 return &elf32_arm_howto_table_2[i];
2132
2133 for (i = 0; i < ARRAY_SIZE (elf32_arm_howto_table_3); i++)
2134 if (elf32_arm_howto_table_3[i].name != NULL
2135 && strcasecmp (elf32_arm_howto_table_3[i].name, r_name) == 0)
2136 return &elf32_arm_howto_table_3[i];
2137
2138 return NULL;
2139 }
2140
2141 /* Support for core dump NOTE sections. */
2142
2143 static bool
2144 elf32_arm_nabi_grok_prstatus (bfd *abfd, Elf_Internal_Note *note)
2145 {
2146 int offset;
2147 size_t size;
2148
2149 switch (note->descsz)
2150 {
2151 default:
2152 return false;
2153
2154 case 148: /* Linux/ARM 32-bit. */
2155 /* pr_cursig */
2156 elf_tdata (abfd)->core->signal = bfd_get_16 (abfd, note->descdata + 12);
2157
2158 /* pr_pid */
2159 elf_tdata (abfd)->core->lwpid = bfd_get_32 (abfd, note->descdata + 24);
2160
2161 /* pr_reg */
2162 offset = 72;
2163 size = 72;
2164
2165 break;
2166 }
2167
2168 /* Make a ".reg/999" section. */
2169 return _bfd_elfcore_make_pseudosection (abfd, ".reg",
2170 size, note->descpos + offset);
2171 }
2172
2173 static bool
2174 elf32_arm_nabi_grok_psinfo (bfd *abfd, Elf_Internal_Note *note)
2175 {
2176 switch (note->descsz)
2177 {
2178 default:
2179 return false;
2180
2181 case 124: /* Linux/ARM elf_prpsinfo. */
2182 elf_tdata (abfd)->core->pid
2183 = bfd_get_32 (abfd, note->descdata + 12);
2184 elf_tdata (abfd)->core->program
2185 = _bfd_elfcore_strndup (abfd, note->descdata + 28, 16);
2186 elf_tdata (abfd)->core->command
2187 = _bfd_elfcore_strndup (abfd, note->descdata + 44, 80);
2188 }
2189
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
2193 {
2194 char *command = elf_tdata (abfd)->core->command;
2195 int n = strlen (command);
2196
2197 if (0 < n && command[n - 1] == ' ')
2198 command[n - 1] = '\0';
2199 }
2200
2201 return true;
2202 }
2203
2204 static char *
2205 elf32_arm_nabi_write_core_note (bfd *abfd, char *buf, int *bufsiz,
2206 int note_type, ...)
2207 {
2208 switch (note_type)
2209 {
2210 default:
2211 return NULL;
2212
2213 case NT_PRPSINFO:
2214 {
2215 char data[124] ATTRIBUTE_NONSTRING;
2216 va_list ap;
2217
2218 va_start (ap, note_type);
2219 memset (data, 0, sizeof (data));
2220 strncpy (data + 28, va_arg (ap, const char *), 16);
2221 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2222 DIAGNOSTIC_PUSH;
2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228 #endif
2229 strncpy (data + 44, va_arg (ap, const char *), 80);
2230 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2231 DIAGNOSTIC_POP;
2232 #endif
2233 va_end (ap);
2234
2235 return elfcore_write_note (abfd, buf, bufsiz,
2236 "CORE", note_type, data, sizeof (data));
2237 }
2238
2239 case NT_PRSTATUS:
2240 {
2241 char data[148];
2242 va_list ap;
2243 long pid;
2244 int cursig;
2245 const void *greg;
2246
2247 va_start (ap, note_type);
2248 memset (data, 0, sizeof (data));
2249 pid = va_arg (ap, long);
2250 bfd_put_32 (abfd, pid, data + 24);
2251 cursig = va_arg (ap, int);
2252 bfd_put_16 (abfd, cursig, data + 12);
2253 greg = va_arg (ap, const void *);
2254 memcpy (data + 72, greg, 72);
2255 va_end (ap);
2256
2257 return elfcore_write_note (abfd, buf, bufsiz,
2258 "CORE", note_type, data, sizeof (data));
2259 }
2260 }
2261 }
2262
2263 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2264 #define TARGET_LITTLE_NAME "elf32-littlearm"
2265 #define TARGET_BIG_SYM arm_elf32_be_vec
2266 #define TARGET_BIG_NAME "elf32-bigarm"
2267
2268 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2270 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2271
2272 typedef unsigned long int insn32;
2273 typedef unsigned short int insn16;
2274
2275 /* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
2277 #define INTERWORK_FLAG(abfd) \
2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
2281
2282 /* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
2285 name can be changed. The only requirement is the %s be present. */
2286 #define THUMB2ARM_GLUE_SECTION_NAME ".glue_7t"
2287 #define THUMB2ARM_GLUE_ENTRY_NAME "__%s_from_thumb"
2288
2289 #define ARM2THUMB_GLUE_SECTION_NAME ".glue_7"
2290 #define ARM2THUMB_GLUE_ENTRY_NAME "__%s_from_arm"
2291
2292 #define VFP11_ERRATUM_VENEER_SECTION_NAME ".vfp11_veneer"
2293 #define VFP11_ERRATUM_VENEER_ENTRY_NAME "__vfp11_veneer_%x"
2294
2295 #define STM32L4XX_ERRATUM_VENEER_SECTION_NAME ".text.stm32l4xx_veneer"
2296 #define STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "__stm32l4xx_veneer_%x"
2297
2298 #define ARM_BX_GLUE_SECTION_NAME ".v4_bx"
2299 #define ARM_BX_GLUE_ENTRY_NAME "__bx_r%d"
2300
2301 #define STUB_ENTRY_NAME "__%s_veneer"
2302
2303 #define CMSE_PREFIX "__acle_se_"
2304
2305 #define CMSE_STUB_NAME ".gnu.sgstubs"
2306
2307 /* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2309 #define ELF_DYNAMIC_INTERPRETER "/usr/lib/ld.so.1"
2310
2311 /* FDPIC default stack size. */
2312 #define DEFAULT_STACK_SIZE 0x8000
2313
2314 static const unsigned long tls_trampoline [] =
2315 {
2316 0xe08e0000, /* add r0, lr, r0 */
2317 0xe5901004, /* ldr r1, [r0,#4] */
2318 0xe12fff11, /* bx r1 */
2319 };
2320
2321 static const unsigned long dl_tlsdesc_lazy_trampoline [] =
2322 {
2323 0xe52d2004, /* push {r2} */
2324 0xe59f200c, /* ldr r2, [pc, #3f - . - 8] */
2325 0xe59f100c, /* ldr r1, [pc, #4f - . - 8] */
2326 0xe79f2002, /* 1: ldr r2, [pc, r2] */
2327 0xe081100f, /* 2: add r1, pc */
2328 0xe12fff12, /* bx r2 */
2329 0x00000014, /* 3: .word _GLOBAL_OFFSET_TABLE_ - 1b - 8
2330 + dl_tlsdesc_lazy_resolver(GOT) */
2331 0x00000018, /* 4: .word _GLOBAL_OFFSET_TABLE_ - 2b - 8 */
2332 };
2333
2334 /* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2338
2339 /* ARM FDPIC PLT entry. */
2340 /* The last 5 words contain PLT lazy fragment code and data. */
2341 static const bfd_vma elf32_arm_fdpic_plt_entry [] =
2342 {
2343 0xe59fc008, /* ldr r12, .L1 */
2344 0xe08cc009, /* add r12, r12, r9 */
2345 0xe59c9004, /* ldr r9, [r12, #4] */
2346 0xe59cf000, /* ldr pc, [r12] */
2347 0x00000000, /* L1. .word foo(GOTOFFFUNCDESC) */
2348 0x00000000, /* L1. .word foo(funcdesc_value_reloc_offset) */
2349 0xe51fc00c, /* ldr r12, [pc, #-12] */
2350 0xe92d1000, /* push {r12} */
2351 0xe599c004, /* ldr r12, [r9, #4] */
2352 0xe599f000, /* ldr pc, [r9] */
2353 };
2354
2355 /* Thumb FDPIC PLT entry. */
2356 /* The last 5 words contain PLT lazy fragment code and data. */
2357 static const bfd_vma elf32_arm_fdpic_thumb_plt_entry [] =
2358 {
2359 0xc00cf8df, /* ldr.w r12, .L1 */
2360 0x0c09eb0c, /* add.w r12, r12, r9 */
2361 0x9004f8dc, /* ldr.w r9, [r12, #4] */
2362 0xf000f8dc, /* ldr.w pc, [r12] */
2363 0x00000000, /* .L1 .word foo(GOTOFFFUNCDESC) */
2364 0x00000000, /* .L2 .word foo(funcdesc_value_reloc_offset) */
2365 0xc008f85f, /* ldr.w r12, .L2 */
2366 0xcd04f84d, /* push {r12} */
2367 0xc004f8d9, /* ldr.w r12, [r9, #4] */
2368 0xf000f8d9, /* ldr.w pc, [r9] */
2369 };
2370
2371 #ifdef FOUR_WORD_PLT
2372
2373 /* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
2375 called before the relocation has been set up calls the dynamic
2376 linker first. */
2377 static const bfd_vma elf32_arm_plt0_entry [] =
2378 {
2379 0xe52de004, /* str lr, [sp, #-4]! */
2380 0xe59fe010, /* ldr lr, [pc, #16] */
2381 0xe08fe00e, /* add lr, pc, lr */
2382 0xe5bef008, /* ldr pc, [lr, #8]! */
2383 };
2384
2385 /* Subsequent entries in a procedure linkage table look like
2386 this. */
2387 static const bfd_vma elf32_arm_plt_entry [] =
2388 {
2389 0xe28fc600, /* add ip, pc, #NN */
2390 0xe28cca00, /* add ip, ip, #NN */
2391 0xe5bcf000, /* ldr pc, [ip, #NN]! */
2392 0x00000000, /* unused */
2393 };
2394
2395 #else /* not FOUR_WORD_PLT */
2396
2397 /* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
2401 static const bfd_vma elf32_arm_plt0_entry [] =
2402 {
2403 0xe52de004, /* str lr, [sp, #-4]! */
2404 0xe59fe004, /* ldr lr, [pc, #4] */
2405 0xe08fe00e, /* add lr, pc, lr */
2406 0xe5bef008, /* ldr pc, [lr, #8]! */
2407 0x00000000, /* &GOT[0] - . */
2408 };
2409
2410 /* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2412 static const bfd_vma elf32_arm_plt_entry_short [] =
2413 {
2414 0xe28fc600, /* add ip, pc, #0xNN00000 */
2415 0xe28cca00, /* add ip, ip, #0xNN000 */
2416 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2417 };
2418
2419 /* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2421 static const bfd_vma elf32_arm_plt_entry_long [] =
2422 {
2423 0xe28fc200, /* add ip, pc, #0xN0000000 */
2424 0xe28cc600, /* add ip, ip, #0xNN00000 */
2425 0xe28cca00, /* add ip, ip, #0xNN000 */
2426 0xe5bcf000, /* ldr pc, [ip, #0xNNN]! */
2427 };
2428
2429 static bool elf32_arm_use_long_plt_entry = false;
2430
2431 #endif /* not FOUR_WORD_PLT */
2432
2433 /* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2436 static const bfd_vma elf32_thumb2_plt0_entry [] =
2437 {
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
2440 0xf8dfb500, /* push {lr} */
2441 0x44fee008, /* ldr.w lr, [pc, #8] */
2442 /* add lr, pc */
2443 0xff08f85e, /* ldr.w pc, [lr, #8]! */
2444 0x00000000, /* &GOT[0] - . */
2445 };
2446
2447 /* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2449 static const bfd_vma elf32_thumb2_plt_entry [] =
2450 {
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
2453 0x0c00f240, /* movw ip, #0xNNNN */
2454 0x0c00f2c0, /* movt ip, #0xNNNN */
2455 0xf8dc44fc, /* add ip, pc */
2456 0xe7fcf000 /* ldr.w pc, [ip] */
2457 /* b .-4 */
2458 };
2459
2460 /* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2462 static const bfd_vma elf32_arm_vxworks_exec_plt0_entry[] =
2463 {
2464 0xe52dc008, /* str ip,[sp,#-8]! */
2465 0xe59fc000, /* ldr ip,[pc] */
2466 0xe59cf008, /* ldr pc,[ip,#8] */
2467 0x00000000, /* .long _GLOBAL_OFFSET_TABLE_ */
2468 };
2469
2470 /* The format of subsequent entries in a VxWorks executable. */
2471 static const bfd_vma elf32_arm_vxworks_exec_plt_entry[] =
2472 {
2473 0xe59fc000, /* ldr ip,[pc] */
2474 0xe59cf000, /* ldr pc,[ip] */
2475 0x00000000, /* .long @got */
2476 0xe59fc000, /* ldr ip,[pc] */
2477 0xea000000, /* b _PLT */
2478 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2479 };
2480
2481 /* The format of entries in a VxWorks shared library. */
2482 static const bfd_vma elf32_arm_vxworks_shared_plt_entry[] =
2483 {
2484 0xe59fc000, /* ldr ip,[pc] */
2485 0xe79cf009, /* ldr pc,[ip,r9] */
2486 0x00000000, /* .long @got */
2487 0xe59fc000, /* ldr ip,[pc] */
2488 0xe599f008, /* ldr pc,[r9,#8] */
2489 0x00000000, /* .long @pltindex*sizeof(Elf32_Rela) */
2490 };
2491
2492 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2493 #define PLT_THUMB_STUB_SIZE 4
2494 static const bfd_vma elf32_arm_plt_thumb_stub [] =
2495 {
2496 0x4778, /* bx pc */
2497 0xe7fd /* b .-2 */
2498 };
2499
2500 /* The first entry in a procedure linkage table looks like
2501 this. It is set up so that any shared library function that is
2502 called before the relocation has been set up calls the dynamic
2503 linker first. */
2504 static const bfd_vma elf32_arm_nacl_plt0_entry [] =
2505 {
2506 /* First bundle: */
2507 0xe300c000, /* movw ip, #:lower16:&GOT[2]-.+8 */
2508 0xe340c000, /* movt ip, #:upper16:&GOT[2]-.+8 */
2509 0xe08cc00f, /* add ip, ip, pc */
2510 0xe52dc008, /* str ip, [sp, #-8]! */
2511 /* Second bundle: */
2512 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2513 0xe59cc000, /* ldr ip, [ip] */
2514 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
2515 0xe12fff1c, /* bx ip */
2516 /* Third bundle: */
2517 0xe320f000, /* nop */
2518 0xe320f000, /* nop */
2519 0xe320f000, /* nop */
2520 /* .Lplt_tail: */
2521 0xe50dc004, /* str ip, [sp, #-4] */
2522 /* Fourth bundle: */
2523 0xe3ccc103, /* bic ip, ip, #0xc0000000 */
2524 0xe59cc000, /* ldr ip, [ip] */
2525 0xe3ccc13f, /* bic ip, ip, #0xc000000f */
2526 0xe12fff1c, /* bx ip */
2527 };
2528 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2529
2530 /* Subsequent entries in a procedure linkage table look like this. */
2531 static const bfd_vma elf32_arm_nacl_plt_entry [] =
2532 {
2533 0xe300c000, /* movw ip, #:lower16:&GOT[n]-.+8 */
2534 0xe340c000, /* movt ip, #:upper16:&GOT[n]-.+8 */
2535 0xe08cc00f, /* add ip, ip, pc */
2536 0xea000000, /* b .Lplt_tail */
2537 };
2538
2539 /* PR 28924:
2540 There was a bug due to too high values of THM_MAX_FWD_BRANCH_OFFSET and
2541 THM2_MAX_FWD_BRANCH_OFFSET. The first macro concerns the case when Thumb-2
2542 is not available, and second macro when Thumb-2 is available. Among other
2543 things, they affect the range of branches represented as BLX instructions
2544 in Encoding T2 defined in Section A8.8.25 of the ARM Architecture
2545 Reference Manual ARMv7-A and ARMv7-R edition issue C.d. Such branches are
2546 specified there to have a maximum forward offset that is a multiple of 4.
2547 Previously, the respective values defined here were multiples of 2 but not
2548 4 and they are included in comments for reference. */
2549 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2550 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2551 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 4 + 4)
2552 /* #def THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 2 + 4) */
2553 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2554 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 4) + 4)
2555 /* #def THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4) */
2556 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2557 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2558 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2559
2560 enum stub_insn_type
2561 {
2562 THUMB16_TYPE = 1,
2563 THUMB32_TYPE,
2564 ARM_TYPE,
2565 DATA_TYPE
2566 };
2567
2568 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2569 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2570 is inserted in arm_build_one_stub(). */
2571 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2572 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2573 #define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2574 #define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
2575 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2576 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2577 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2578 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2579
2580 typedef struct
2581 {
2582 bfd_vma data;
2583 enum stub_insn_type type;
2584 unsigned int r_type;
2585 int reloc_addend;
2586 } insn_sequence;
2587
2588 /* See note [Thumb nop sequence] when adding a veneer. */
2589
2590 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2591 to reach the stub if necessary. */
2592 static const insn_sequence elf32_arm_stub_long_branch_any_any[] =
2593 {
2594 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2595 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2596 };
2597
2598 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2599 available. */
2600 static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb[] =
2601 {
2602 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2603 ARM_INSN (0xe12fff1c), /* bx ip */
2604 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2605 };
2606
2607 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2608 static const insn_sequence elf32_arm_stub_long_branch_thumb_only[] =
2609 {
2610 THUMB16_INSN (0xb401), /* push {r0} */
2611 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2612 THUMB16_INSN (0x4684), /* mov ip, r0 */
2613 THUMB16_INSN (0xbc01), /* pop {r0} */
2614 THUMB16_INSN (0x4760), /* bx ip */
2615 THUMB16_INSN (0xbf00), /* nop */
2616 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2617 };
2618
2619 /* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2620 static const insn_sequence elf32_arm_stub_long_branch_thumb2_only[] =
2621 {
2622 THUMB32_INSN (0xf85ff000), /* ldr.w pc, [pc, #-0] */
2623 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(x) */
2624 };
2625
2626 /* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2627 M-profile architectures. */
2628 static const insn_sequence elf32_arm_stub_long_branch_thumb2_only_pure[] =
2629 {
2630 THUMB32_MOVW (0xf2400c00), /* mov.w ip, R_ARM_MOVW_ABS_NC */
2631 THUMB32_MOVT (0xf2c00c00), /* movt ip, R_ARM_MOVT_ABS << 16 */
2632 THUMB16_INSN (0x4760), /* bx ip */
2633 };
2634
2635 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2636 allowed. */
2637 static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb[] =
2638 {
2639 THUMB16_INSN (0x4778), /* bx pc */
2640 THUMB16_INSN (0xe7fd), /* b .-2 */
2641 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2642 ARM_INSN (0xe12fff1c), /* bx ip */
2643 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2644 };
2645
2646 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2647 available. */
2648 static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm[] =
2649 {
2650 THUMB16_INSN (0x4778), /* bx pc */
2651 THUMB16_INSN (0xe7fd), /* b .-2 */
2652 ARM_INSN (0xe51ff004), /* ldr pc, [pc, #-4] */
2653 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2654 };
2655
2656 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2657 one, when the destination is close enough. */
2658 static const insn_sequence elf32_arm_stub_short_branch_v4t_thumb_arm[] =
2659 {
2660 THUMB16_INSN (0x4778), /* bx pc */
2661 THUMB16_INSN (0xe7fd), /* b .-2 */
2662 ARM_REL_INSN (0xea000000, -8), /* b (X-8) */
2663 };
2664
2665 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2666 blx to reach the stub if necessary. */
2667 static const insn_sequence elf32_arm_stub_long_branch_any_arm_pic[] =
2668 {
2669 ARM_INSN (0xe59fc000), /* ldr ip, [pc] */
2670 ARM_INSN (0xe08ff00c), /* add pc, pc, ip */
2671 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2672 };
2673
2674 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2675 blx to reach the stub if necessary. We can not add into pc;
2676 it is not guaranteed to mode switch (different in ARMv6 and
2677 ARMv7). */
2678 static const insn_sequence elf32_arm_stub_long_branch_any_thumb_pic[] =
2679 {
2680 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2681 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2682 ARM_INSN (0xe12fff1c), /* bx ip */
2683 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2684 };
2685
2686 /* V4T ARM -> ARM long branch stub, PIC. */
2687 static const insn_sequence elf32_arm_stub_long_branch_v4t_arm_thumb_pic[] =
2688 {
2689 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2690 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2691 ARM_INSN (0xe12fff1c), /* bx ip */
2692 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2693 };
2694
2695 /* V4T Thumb -> ARM long branch stub, PIC. */
2696 static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_arm_pic[] =
2697 {
2698 THUMB16_INSN (0x4778), /* bx pc */
2699 THUMB16_INSN (0xe7fd), /* b .-2 */
2700 ARM_INSN (0xe59fc000), /* ldr ip, [pc, #0] */
2701 ARM_INSN (0xe08cf00f), /* add pc, ip, pc */
2702 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2703 };
2704
2705 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2706 architectures. */
2707 static const insn_sequence elf32_arm_stub_long_branch_thumb_only_pic[] =
2708 {
2709 THUMB16_INSN (0xb401), /* push {r0} */
2710 THUMB16_INSN (0x4802), /* ldr r0, [pc, #8] */
2711 THUMB16_INSN (0x46fc), /* mov ip, pc */
2712 THUMB16_INSN (0x4484), /* add ip, r0 */
2713 THUMB16_INSN (0xbc01), /* pop {r0} */
2714 THUMB16_INSN (0x4760), /* bx ip */
2715 DATA_WORD (0, R_ARM_REL32, 4), /* dcd R_ARM_REL32(X) */
2716 };
2717
2718 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2719 allowed. */
2720 static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_thumb_pic[] =
2721 {
2722 THUMB16_INSN (0x4778), /* bx pc */
2723 THUMB16_INSN (0xe7fd), /* b .-2 */
2724 ARM_INSN (0xe59fc004), /* ldr ip, [pc, #4] */
2725 ARM_INSN (0xe08fc00c), /* add ip, pc, ip */
2726 ARM_INSN (0xe12fff1c), /* bx ip */
2727 DATA_WORD (0, R_ARM_REL32, 0), /* dcd R_ARM_REL32(X) */
2728 };
2729
2730 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2731 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2732 static const insn_sequence elf32_arm_stub_long_branch_any_tls_pic[] =
2733 {
2734 ARM_INSN (0xe59f1000), /* ldr r1, [pc] */
2735 ARM_INSN (0xe08ff001), /* add pc, pc, r1 */
2736 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X-4) */
2737 };
2738
2739 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2740 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2741 static const insn_sequence elf32_arm_stub_long_branch_v4t_thumb_tls_pic[] =
2742 {
2743 THUMB16_INSN (0x4778), /* bx pc */
2744 THUMB16_INSN (0xe7fd), /* b .-2 */
2745 ARM_INSN (0xe59f1000), /* ldr r1, [pc, #0] */
2746 ARM_INSN (0xe081f00f), /* add pc, r1, pc */
2747 DATA_WORD (0, R_ARM_REL32, -4), /* dcd R_ARM_REL32(X) */
2748 };
2749
2750 /* NaCl ARM -> ARM long branch stub. */
2751 static const insn_sequence elf32_arm_stub_long_branch_arm_nacl[] =
2752 {
2753 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2754 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2755 ARM_INSN (0xe12fff1c), /* bx ip */
2756 ARM_INSN (0xe320f000), /* nop */
2757 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2758 DATA_WORD (0, R_ARM_ABS32, 0), /* dcd R_ARM_ABS32(X) */
2759 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2760 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2761 };
2762
2763 /* NaCl ARM -> ARM long branch stub, PIC. */
2764 static const insn_sequence elf32_arm_stub_long_branch_arm_nacl_pic[] =
2765 {
2766 ARM_INSN (0xe59fc00c), /* ldr ip, [pc, #12] */
2767 ARM_INSN (0xe08cc00f), /* add ip, ip, pc */
2768 ARM_INSN (0xe3ccc13f), /* bic ip, ip, #0xc000000f */
2769 ARM_INSN (0xe12fff1c), /* bx ip */
2770 ARM_INSN (0xe125be70), /* bkpt 0x5be0 */
2771 DATA_WORD (0, R_ARM_REL32, 8), /* dcd R_ARM_REL32(X+8) */
2772 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2773 DATA_WORD (0, R_ARM_NONE, 0), /* .word 0 */
2774 };
2775
2776 /* Stub used for transition to secure state (aka SG veneer). */
2777 static const insn_sequence elf32_arm_stub_cmse_branch_thumb_only[] =
2778 {
2779 THUMB32_INSN (0xe97fe97f), /* sg. */
2780 THUMB32_B_INSN (0xf000b800, -4), /* b.w original_branch_dest. */
2781 };
2782
2783
2784 /* Cortex-A8 erratum-workaround stubs. */
2785
2786 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2787 can't use a conditional branch to reach this stub). */
2788
2789 static const insn_sequence elf32_arm_stub_a8_veneer_b_cond[] =
2790 {
2791 THUMB16_BCOND_INSN (0xd001), /* b<cond>.n true. */
2792 THUMB32_B_INSN (0xf000b800, -4), /* b.w insn_after_original_branch. */
2793 THUMB32_B_INSN (0xf000b800, -4) /* true: b.w original_branch_dest. */
2794 };
2795
2796 /* Stub used for b.w and bl.w instructions. */
2797
2798 static const insn_sequence elf32_arm_stub_a8_veneer_b[] =
2799 {
2800 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2801 };
2802
2803 static const insn_sequence elf32_arm_stub_a8_veneer_bl[] =
2804 {
2805 THUMB32_B_INSN (0xf000b800, -4) /* b.w original_branch_dest. */
2806 };
2807
2808 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2809 instruction (which switches to ARM mode) to point to this stub. Jump to the
2810 real destination using an ARM-mode branch. */
2811
2812 static const insn_sequence elf32_arm_stub_a8_veneer_blx[] =
2813 {
2814 ARM_REL_INSN (0xea000000, -8) /* b original_branch_dest. */
2815 };
2816
2817 /* For each section group there can be a specially created linker section
2818 to hold the stubs for that group. The name of the stub section is based
2819 upon the name of another section within that group with the suffix below
2820 applied.
2821
2822 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2823 create what appeared to be a linker stub section when it actually
2824 contained user code/data. For example, consider this fragment:
2825
2826 const char * stubborn_problems[] = { "np" };
2827
2828 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2829 section called:
2830
2831 .data.rel.local.stubborn_problems
2832
2833 This then causes problems in arm32_arm_build_stubs() as it triggers:
2834
2835 // Ignore non-stub sections.
2836 if (!strstr (stub_sec->name, STUB_SUFFIX))
2837 continue;
2838
2839 And so the section would be ignored instead of being processed. Hence
2840 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2841 C identifier. */
2842 #define STUB_SUFFIX ".__stub"
2843
2844 /* One entry per long/short branch stub defined above. */
2845 #define DEF_STUBS \
2846 DEF_STUB (long_branch_any_any) \
2847 DEF_STUB (long_branch_v4t_arm_thumb) \
2848 DEF_STUB (long_branch_thumb_only) \
2849 DEF_STUB (long_branch_v4t_thumb_thumb) \
2850 DEF_STUB (long_branch_v4t_thumb_arm) \
2851 DEF_STUB (short_branch_v4t_thumb_arm) \
2852 DEF_STUB (long_branch_any_arm_pic) \
2853 DEF_STUB (long_branch_any_thumb_pic) \
2854 DEF_STUB (long_branch_v4t_thumb_thumb_pic) \
2855 DEF_STUB (long_branch_v4t_arm_thumb_pic) \
2856 DEF_STUB (long_branch_v4t_thumb_arm_pic) \
2857 DEF_STUB (long_branch_thumb_only_pic) \
2858 DEF_STUB (long_branch_any_tls_pic) \
2859 DEF_STUB (long_branch_v4t_thumb_tls_pic) \
2860 DEF_STUB (long_branch_arm_nacl) \
2861 DEF_STUB (long_branch_arm_nacl_pic) \
2862 DEF_STUB (cmse_branch_thumb_only) \
2863 DEF_STUB (a8_veneer_b_cond) \
2864 DEF_STUB (a8_veneer_b) \
2865 DEF_STUB (a8_veneer_bl) \
2866 DEF_STUB (a8_veneer_blx) \
2867 DEF_STUB (long_branch_thumb2_only) \
2868 DEF_STUB (long_branch_thumb2_only_pure)
2869
2870 #define DEF_STUB(x) arm_stub_##x,
2871 enum elf32_arm_stub_type
2872 {
2873 arm_stub_none,
2874 DEF_STUBS
2875 max_stub_type
2876 };
2877 #undef DEF_STUB
2878
2879 /* Note the first a8_veneer type. */
2880 const unsigned arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond;
2881
2882 typedef struct
2883 {
2884 const insn_sequence* template_sequence;
2885 int template_size;
2886 } stub_def;
2887
2888 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2889 static const stub_def stub_definitions[] =
2890 {
2891 {NULL, 0},
2892 DEF_STUBS
2893 };
2894
2895 struct elf32_arm_stub_hash_entry
2896 {
2897 /* Base hash table entry structure. */
2898 struct bfd_hash_entry root;
2899
2900 /* The stub section. */
2901 asection *stub_sec;
2902
2903 /* Offset within stub_sec of the beginning of this stub. */
2904 bfd_vma stub_offset;
2905
2906 /* Given the symbol's value and its section we can determine its final
2907 value when building the stubs (so the stub knows where to jump). */
2908 bfd_vma target_value;
2909 asection *target_section;
2910
2911 /* Same as above but for the source of the branch to the stub. Used for
2912 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2913 such, source section does not need to be recorded since Cortex-A8 erratum
2914 workaround stubs are only generated when both source and target are in the
2915 same section. */
2916 bfd_vma source_value;
2917
2918 /* The instruction which caused this stub to be generated (only valid for
2919 Cortex-A8 erratum workaround stubs at present). */
2920 unsigned long orig_insn;
2921
2922 /* The stub type. */
2923 enum elf32_arm_stub_type stub_type;
2924 /* Its encoding size in bytes. */
2925 int stub_size;
2926 /* Its template. */
2927 const insn_sequence *stub_template;
2928 /* The size of the template (number of entries). */
2929 int stub_template_size;
2930
2931 /* The symbol table entry, if any, that this was derived from. */
2932 struct elf32_arm_link_hash_entry *h;
2933
2934 /* Type of branch. */
2935 enum arm_st_branch_type branch_type;
2936
2937 /* Where this stub is being called from, or, in the case of combined
2938 stub sections, the first input section in the group. */
2939 asection *id_sec;
2940
2941 /* The name for the local symbol at the start of this stub. The
2942 stub name in the hash table has to be unique; this does not, so
2943 it can be friendlier. */
2944 char *output_name;
2945 };
2946
2947 /* Used to build a map of a section. This is required for mixed-endian
2948 code/data. */
2949
2950 typedef struct elf32_elf_section_map
2951 {
2952 bfd_vma vma;
2953 char type;
2954 }
2955 elf32_arm_section_map;
2956
2957 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2958
2959 typedef enum
2960 {
2961 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2962 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2963 VFP11_ERRATUM_ARM_VENEER,
2964 VFP11_ERRATUM_THUMB_VENEER
2965 }
2966 elf32_vfp11_erratum_type;
2967
2968 typedef struct elf32_vfp11_erratum_list
2969 {
2970 struct elf32_vfp11_erratum_list *next;
2971 bfd_vma vma;
2972 union
2973 {
2974 struct
2975 {
2976 struct elf32_vfp11_erratum_list *veneer;
2977 unsigned int vfp_insn;
2978 } b;
2979 struct
2980 {
2981 struct elf32_vfp11_erratum_list *branch;
2982 unsigned int id;
2983 } v;
2984 } u;
2985 elf32_vfp11_erratum_type type;
2986 }
2987 elf32_vfp11_erratum_list;
2988
2989 /* Information about a STM32L4XX erratum veneer, or a branch to such a
2990 veneer. */
2991 typedef enum
2992 {
2993 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2994 STM32L4XX_ERRATUM_VENEER
2995 }
2996 elf32_stm32l4xx_erratum_type;
2997
2998 typedef struct elf32_stm32l4xx_erratum_list
2999 {
3000 struct elf32_stm32l4xx_erratum_list *next;
3001 bfd_vma vma;
3002 union
3003 {
3004 struct
3005 {
3006 struct elf32_stm32l4xx_erratum_list *veneer;
3007 unsigned int insn;
3008 } b;
3009 struct
3010 {
3011 struct elf32_stm32l4xx_erratum_list *branch;
3012 unsigned int id;
3013 } v;
3014 } u;
3015 elf32_stm32l4xx_erratum_type type;
3016 }
3017 elf32_stm32l4xx_erratum_list;
3018
3019 typedef enum
3020 {
3021 DELETE_EXIDX_ENTRY,
3022 INSERT_EXIDX_CANTUNWIND_AT_END
3023 }
3024 arm_unwind_edit_type;
3025
3026 /* A (sorted) list of edits to apply to an unwind table. */
3027 typedef struct arm_unwind_table_edit
3028 {
3029 arm_unwind_edit_type type;
3030 /* Note: we sometimes want to insert an unwind entry corresponding to a
3031 section different from the one we're currently writing out, so record the
3032 (text) section this edit relates to here. */
3033 asection *linked_section;
3034 unsigned int index;
3035 struct arm_unwind_table_edit *next;
3036 }
3037 arm_unwind_table_edit;
3038
3039 typedef struct _arm_elf_section_data
3040 {
3041 /* Information about mapping symbols. */
3042 struct bfd_elf_section_data elf;
3043 unsigned int mapcount;
3044 unsigned int mapsize;
3045 elf32_arm_section_map *map;
3046 /* Information about CPU errata. */
3047 unsigned int erratumcount;
3048 elf32_vfp11_erratum_list *erratumlist;
3049 unsigned int stm32l4xx_erratumcount;
3050 elf32_stm32l4xx_erratum_list *stm32l4xx_erratumlist;
3051 unsigned int additional_reloc_count;
3052 /* Information about unwind tables. */
3053 union
3054 {
3055 /* Unwind info attached to a text section. */
3056 struct
3057 {
3058 asection *arm_exidx_sec;
3059 } text;
3060
3061 /* Unwind info attached to an .ARM.exidx section. */
3062 struct
3063 {
3064 arm_unwind_table_edit *unwind_edit_list;
3065 arm_unwind_table_edit *unwind_edit_tail;
3066 } exidx;
3067 } u;
3068 }
3069 _arm_elf_section_data;
3070
3071 #define elf32_arm_section_data(sec) \
3072 ((_arm_elf_section_data *) elf_section_data (sec))
3073
3074 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3075 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3076 so may be created multiple times: we use an array of these entries whilst
3077 relaxing which we can refresh easily, then create stubs for each potentially
3078 erratum-triggering instruction once we've settled on a solution. */
3079
3080 struct a8_erratum_fix
3081 {
3082 bfd *input_bfd;
3083 asection *section;
3084 bfd_vma offset;
3085 bfd_vma target_offset;
3086 unsigned long orig_insn;
3087 char *stub_name;
3088 enum elf32_arm_stub_type stub_type;
3089 enum arm_st_branch_type branch_type;
3090 };
3091
3092 /* A table of relocs applied to branches which might trigger Cortex-A8
3093 erratum. */
3094
3095 struct a8_erratum_reloc
3096 {
3097 bfd_vma from;
3098 bfd_vma destination;
3099 struct elf32_arm_link_hash_entry *hash;
3100 const char *sym_name;
3101 unsigned int r_type;
3102 enum arm_st_branch_type branch_type;
3103 bool non_a8_stub;
3104 };
3105
3106 /* The size of the thread control block. */
3107 #define TCB_SIZE 8
3108
3109 /* ARM-specific information about a PLT entry, over and above the usual
3110 gotplt_union. */
3111 struct arm_plt_info
3112 {
3113 /* We reference count Thumb references to a PLT entry separately,
3114 so that we can emit the Thumb trampoline only if needed. */
3115 bfd_signed_vma thumb_refcount;
3116
3117 /* Some references from Thumb code may be eliminated by BL->BLX
3118 conversion, so record them separately. */
3119 bfd_signed_vma maybe_thumb_refcount;
3120
3121 /* How many of the recorded PLT accesses were from non-call relocations.
3122 This information is useful when deciding whether anything takes the
3123 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3124 non-call references to the function should resolve directly to the
3125 real runtime target. */
3126 unsigned int noncall_refcount;
3127
3128 /* Since PLT entries have variable size if the Thumb prologue is
3129 used, we need to record the index into .got.plt instead of
3130 recomputing it from the PLT offset. */
3131 bfd_signed_vma got_offset;
3132 };
3133
3134 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
3135 struct arm_local_iplt_info
3136 {
3137 /* The information that is usually found in the generic ELF part of
3138 the hash table entry. */
3139 union gotplt_union root;
3140
3141 /* The information that is usually found in the ARM-specific part of
3142 the hash table entry. */
3143 struct arm_plt_info arm;
3144
3145 /* A list of all potential dynamic relocations against this symbol. */
3146 struct elf_dyn_relocs *dyn_relocs;
3147 };
3148
3149 /* Structure to handle FDPIC support for local functions. */
3150 struct fdpic_local
3151 {
3152 unsigned int funcdesc_cnt;
3153 unsigned int gotofffuncdesc_cnt;
3154 int funcdesc_offset;
3155 };
3156
3157 struct elf_arm_obj_tdata
3158 {
3159 struct elf_obj_tdata root;
3160
3161 /* Zero to warn when linking objects with incompatible enum sizes. */
3162 int no_enum_size_warning;
3163
3164 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3165 int no_wchar_size_warning;
3166
3167 /* The number of entries in each of the arrays in this strcuture.
3168 Used to avoid buffer overruns. */
3169 bfd_size_type num_entries;
3170
3171 /* tls_type for each local got entry. */
3172 char *local_got_tls_type;
3173
3174 /* GOTPLT entries for TLS descriptors. */
3175 bfd_vma *local_tlsdesc_gotent;
3176
3177 /* Information for local symbols that need entries in .iplt. */
3178 struct arm_local_iplt_info **local_iplt;
3179
3180 /* Maintains FDPIC counters and funcdesc info. */
3181 struct fdpic_local *local_fdpic_cnts;
3182 };
3183
3184 #define elf_arm_tdata(bfd) \
3185 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
3186
3187 #define elf32_arm_num_entries(bfd) \
3188 (elf_arm_tdata (bfd)->num_entries)
3189
3190 #define elf32_arm_local_got_tls_type(bfd) \
3191 (elf_arm_tdata (bfd)->local_got_tls_type)
3192
3193 #define elf32_arm_local_tlsdesc_gotent(bfd) \
3194 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3195
3196 #define elf32_arm_local_iplt(bfd) \
3197 (elf_arm_tdata (bfd)->local_iplt)
3198
3199 #define elf32_arm_local_fdpic_cnts(bfd) \
3200 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3201
3202 #define is_arm_elf(bfd) \
3203 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3204 && elf_tdata (bfd) != NULL \
3205 && elf_object_id (bfd) == ARM_ELF_DATA)
3206
3207 static bool
3208 elf32_arm_mkobject (bfd *abfd)
3209 {
3210 return bfd_elf_allocate_object (abfd, sizeof (struct elf_arm_obj_tdata),
3211 ARM_ELF_DATA);
3212 }
3213
3214 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3215
3216 /* Structure to handle FDPIC support for extern functions. */
3217 struct fdpic_global {
3218 unsigned int gotofffuncdesc_cnt;
3219 unsigned int gotfuncdesc_cnt;
3220 unsigned int funcdesc_cnt;
3221 int funcdesc_offset;
3222 int gotfuncdesc_offset;
3223 };
3224
3225 /* Arm ELF linker hash entry. */
3226 struct elf32_arm_link_hash_entry
3227 {
3228 struct elf_link_hash_entry root;
3229
3230 /* ARM-specific PLT information. */
3231 struct arm_plt_info plt;
3232
3233 #define GOT_UNKNOWN 0
3234 #define GOT_NORMAL 1
3235 #define GOT_TLS_GD 2
3236 #define GOT_TLS_IE 4
3237 #define GOT_TLS_GDESC 8
3238 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
3239 unsigned int tls_type : 8;
3240
3241 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3242 unsigned int is_iplt : 1;
3243
3244 unsigned int unused : 23;
3245
3246 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3247 starting at the end of the jump table. */
3248 bfd_vma tlsdesc_got;
3249
3250 /* The symbol marking the real symbol location for exported thumb
3251 symbols with Arm stubs. */
3252 struct elf_link_hash_entry *export_glue;
3253
3254 /* A pointer to the most recently used stub hash entry against this
3255 symbol. */
3256 struct elf32_arm_stub_hash_entry *stub_cache;
3257
3258 /* Counter for FDPIC relocations against this symbol. */
3259 struct fdpic_global fdpic_cnts;
3260 };
3261
3262 /* Traverse an arm ELF linker hash table. */
3263 #define elf32_arm_link_hash_traverse(table, func, info) \
3264 (elf_link_hash_traverse \
3265 (&(table)->root, \
3266 (bool (*) (struct elf_link_hash_entry *, void *)) (func), \
3267 (info)))
3268
3269 /* Get the ARM elf linker hash table from a link_info structure. */
3270 #define elf32_arm_hash_table(p) \
3271 ((is_elf_hash_table ((p)->hash) \
3272 && elf_hash_table_id (elf_hash_table (p)) == ARM_ELF_DATA) \
3273 ? (struct elf32_arm_link_hash_table *) (p)->hash : NULL)
3274
3275 #define arm_stub_hash_lookup(table, string, create, copy) \
3276 ((struct elf32_arm_stub_hash_entry *) \
3277 bfd_hash_lookup ((table), (string), (create), (copy)))
3278
3279 /* Array to keep track of which stub sections have been created, and
3280 information on stub grouping. */
3281 struct map_stub
3282 {
3283 /* This is the section to which stubs in the group will be
3284 attached. */
3285 asection *link_sec;
3286 /* The stub section. */
3287 asection *stub_sec;
3288 };
3289
3290 #define elf32_arm_compute_jump_table_size(htab) \
3291 ((htab)->next_tls_desc_index * 4)
3292
3293 /* ARM ELF linker hash table. */
3294 struct elf32_arm_link_hash_table
3295 {
3296 /* The main hash table. */
3297 struct elf_link_hash_table root;
3298
3299 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3300 bfd_size_type thumb_glue_size;
3301
3302 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3303 bfd_size_type arm_glue_size;
3304
3305 /* The size in bytes of section containing the ARMv4 BX veneers. */
3306 bfd_size_type bx_glue_size;
3307
3308 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3309 veneer has been populated. */
3310 bfd_vma bx_glue_offset[15];
3311
3312 /* The size in bytes of the section containing glue for VFP11 erratum
3313 veneers. */
3314 bfd_size_type vfp11_erratum_glue_size;
3315
3316 /* The size in bytes of the section containing glue for STM32L4XX erratum
3317 veneers. */
3318 bfd_size_type stm32l4xx_erratum_glue_size;
3319
3320 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3321 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3322 elf32_arm_write_section(). */
3323 struct a8_erratum_fix *a8_erratum_fixes;
3324 unsigned int num_a8_erratum_fixes;
3325
3326 /* An arbitrary input BFD chosen to hold the glue sections. */
3327 bfd * bfd_of_glue_owner;
3328
3329 /* Nonzero to output a BE8 image. */
3330 int byteswap_code;
3331
3332 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3333 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3334 int target1_is_rel;
3335
3336 /* The relocation to use for R_ARM_TARGET2 relocations. */
3337 int target2_reloc;
3338
3339 /* 0 = Ignore R_ARM_V4BX.
3340 1 = Convert BX to MOV PC.
3341 2 = Generate v4 interworing stubs. */
3342 int fix_v4bx;
3343
3344 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3345 int fix_cortex_a8;
3346
3347 /* Whether we should fix the ARM1176 BLX immediate issue. */
3348 int fix_arm1176;
3349
3350 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3351 int use_blx;
3352
3353 /* What sort of code sequences we should look for which may trigger the
3354 VFP11 denorm erratum. */
3355 bfd_arm_vfp11_fix vfp11_fix;
3356
3357 /* Global counter for the number of fixes we have emitted. */
3358 int num_vfp11_fixes;
3359
3360 /* What sort of code sequences we should look for which may trigger the
3361 STM32L4XX erratum. */
3362 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3363
3364 /* Global counter for the number of fixes we have emitted. */
3365 int num_stm32l4xx_fixes;
3366
3367 /* Nonzero to force PIC branch veneers. */
3368 int pic_veneer;
3369
3370 /* The number of bytes in the initial entry in the PLT. */
3371 bfd_size_type plt_header_size;
3372
3373 /* The number of bytes in the subsequent PLT etries. */
3374 bfd_size_type plt_entry_size;
3375
3376 /* True if the target uses REL relocations. */
3377 bool use_rel;
3378
3379 /* Nonzero if import library must be a secure gateway import library
3380 as per ARMv8-M Security Extensions. */
3381 int cmse_implib;
3382
3383 /* The import library whose symbols' address must remain stable in
3384 the import library generated. */
3385 bfd *in_implib_bfd;
3386
3387 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3388 bfd_vma next_tls_desc_index;
3389
3390 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3391 bfd_vma num_tls_desc;
3392
3393 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3394 asection *srelplt2;
3395
3396 /* Offset in .plt section of tls_arm_trampoline. */
3397 bfd_vma tls_trampoline;
3398
3399 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
3400 union
3401 {
3402 bfd_signed_vma refcount;
3403 bfd_vma offset;
3404 } tls_ldm_got;
3405
3406 /* For convenience in allocate_dynrelocs. */
3407 bfd * obfd;
3408
3409 /* The amount of space used by the reserved portion of the sgotplt
3410 section, plus whatever space is used by the jump slots. */
3411 bfd_vma sgotplt_jump_table_size;
3412
3413 /* The stub hash table. */
3414 struct bfd_hash_table stub_hash_table;
3415
3416 /* Linker stub bfd. */
3417 bfd *stub_bfd;
3418
3419 /* Linker call-backs. */
3420 asection * (*add_stub_section) (const char *, asection *, asection *,
3421 unsigned int);
3422 void (*layout_sections_again) (void);
3423
3424 /* Array to keep track of which stub sections have been created, and
3425 information on stub grouping. */
3426 struct map_stub *stub_group;
3427
3428 /* Input stub section holding secure gateway veneers. */
3429 asection *cmse_stub_sec;
3430
3431 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3432 start to be allocated. */
3433 bfd_vma new_cmse_stub_offset;
3434
3435 /* Number of elements in stub_group. */
3436 unsigned int top_id;
3437
3438 /* Assorted information used by elf32_arm_size_stubs. */
3439 unsigned int bfd_count;
3440 unsigned int top_index;
3441 asection **input_list;
3442
3443 /* True if the target system uses FDPIC. */
3444 int fdpic_p;
3445
3446 /* Fixup section. Used for FDPIC. */
3447 asection *srofixup;
3448 };
3449
3450 /* Add an FDPIC read-only fixup. */
3451 static void
3452 arm_elf_add_rofixup (bfd *output_bfd, asection *srofixup, bfd_vma offset)
3453 {
3454 bfd_vma fixup_offset;
3455
3456 fixup_offset = srofixup->reloc_count++ * 4;
3457 BFD_ASSERT (fixup_offset < srofixup->size);
3458 bfd_put_32 (output_bfd, offset, srofixup->contents + fixup_offset);
3459 }
3460
3461 static inline int
3462 ctz (unsigned int mask)
3463 {
3464 #if GCC_VERSION >= 3004
3465 return __builtin_ctz (mask);
3466 #else
3467 unsigned int i;
3468
3469 for (i = 0; i < 8 * sizeof (mask); i++)
3470 {
3471 if (mask & 0x1)
3472 break;
3473 mask = (mask >> 1);
3474 }
3475 return i;
3476 #endif
3477 }
3478
3479 static inline int
3480 elf32_arm_popcount (unsigned int mask)
3481 {
3482 #if GCC_VERSION >= 3004
3483 return __builtin_popcount (mask);
3484 #else
3485 unsigned int i;
3486 int sum = 0;
3487
3488 for (i = 0; i < 8 * sizeof (mask); i++)
3489 {
3490 if (mask & 0x1)
3491 sum++;
3492 mask = (mask >> 1);
3493 }
3494 return sum;
3495 #endif
3496 }
3497
3498 static void elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
3499 asection *sreloc, Elf_Internal_Rela *rel);
3500
3501 static void
3502 arm_elf_fill_funcdesc (bfd *output_bfd,
3503 struct bfd_link_info *info,
3504 int *funcdesc_offset,
3505 int dynindx,
3506 int offset,
3507 bfd_vma addr,
3508 bfd_vma dynreloc_value,
3509 bfd_vma seg)
3510 {
3511 if ((*funcdesc_offset & 1) == 0)
3512 {
3513 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
3514 asection *sgot = globals->root.sgot;
3515
3516 if (bfd_link_pic (info))
3517 {
3518 asection *srelgot = globals->root.srelgot;
3519 Elf_Internal_Rela outrel;
3520
3521 outrel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
3522 outrel.r_offset = sgot->output_section->vma + sgot->output_offset + offset;
3523 outrel.r_addend = 0;
3524
3525 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
3526 bfd_put_32 (output_bfd, addr, sgot->contents + offset);
3527 bfd_put_32 (output_bfd, seg, sgot->contents + offset + 4);
3528 }
3529 else
3530 {
3531 struct elf_link_hash_entry *hgot = globals->root.hgot;
3532 bfd_vma got_value = hgot->root.u.def.value
3533 + hgot->root.u.def.section->output_section->vma
3534 + hgot->root.u.def.section->output_offset;
3535
3536 arm_elf_add_rofixup (output_bfd, globals->srofixup,
3537 sgot->output_section->vma + sgot->output_offset
3538 + offset);
3539 arm_elf_add_rofixup (output_bfd, globals->srofixup,
3540 sgot->output_section->vma + sgot->output_offset
3541 + offset + 4);
3542 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + offset);
3543 bfd_put_32 (output_bfd, got_value, sgot->contents + offset + 4);
3544 }
3545 *funcdesc_offset |= 1;
3546 }
3547 }
3548
3549 /* Create an entry in an ARM ELF linker hash table. */
3550
3551 static struct bfd_hash_entry *
3552 elf32_arm_link_hash_newfunc (struct bfd_hash_entry * entry,
3553 struct bfd_hash_table * table,
3554 const char * string)
3555 {
3556 struct elf32_arm_link_hash_entry * ret =
3557 (struct elf32_arm_link_hash_entry *) entry;
3558
3559 /* Allocate the structure if it has not already been allocated by a
3560 subclass. */
3561 if (ret == NULL)
3562 ret = (struct elf32_arm_link_hash_entry *)
3563 bfd_hash_allocate (table, sizeof (struct elf32_arm_link_hash_entry));
3564 if (ret == NULL)
3565 return (struct bfd_hash_entry *) ret;
3566
3567 /* Call the allocation method of the superclass. */
3568 ret = ((struct elf32_arm_link_hash_entry *)
3569 _bfd_elf_link_hash_newfunc ((struct bfd_hash_entry *) ret,
3570 table, string));
3571 if (ret != NULL)
3572 {
3573 ret->tls_type = GOT_UNKNOWN;
3574 ret->tlsdesc_got = (bfd_vma) -1;
3575 ret->plt.thumb_refcount = 0;
3576 ret->plt.maybe_thumb_refcount = 0;
3577 ret->plt.noncall_refcount = 0;
3578 ret->plt.got_offset = -1;
3579 ret->is_iplt = false;
3580 ret->export_glue = NULL;
3581
3582 ret->stub_cache = NULL;
3583
3584 ret->fdpic_cnts.gotofffuncdesc_cnt = 0;
3585 ret->fdpic_cnts.gotfuncdesc_cnt = 0;
3586 ret->fdpic_cnts.funcdesc_cnt = 0;
3587 ret->fdpic_cnts.funcdesc_offset = -1;
3588 ret->fdpic_cnts.gotfuncdesc_offset = -1;
3589 }
3590
3591 return (struct bfd_hash_entry *) ret;
3592 }
3593
3594 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3595 symbols. */
3596
3597 static bool
3598 elf32_arm_allocate_local_sym_info (bfd *abfd)
3599 {
3600 if (elf_local_got_refcounts (abfd) == NULL)
3601 {
3602 bfd_size_type num_syms;
3603
3604 elf32_arm_num_entries (abfd) = 0;
3605
3606 /* Whilst it might be tempting to allocate a single block of memory and
3607 then divide it up amoungst the arrays in the elf_arm_obj_tdata
3608 structure, this interferes with the work of memory checkers looking
3609 for buffer overruns. So allocate each array individually. */
3610
3611 num_syms = elf_tdata (abfd)->symtab_hdr.sh_info;
3612
3613 elf_local_got_refcounts (abfd) = bfd_zalloc
3614 (abfd, num_syms * sizeof (* elf_local_got_refcounts (abfd)));
3615
3616 if (elf_local_got_refcounts (abfd) == NULL)
3617 return false;
3618
3619 elf32_arm_local_tlsdesc_gotent (abfd) = bfd_zalloc
3620 (abfd, num_syms * sizeof (* elf32_arm_local_tlsdesc_gotent (abfd)));
3621
3622 if (elf32_arm_local_tlsdesc_gotent (abfd) == NULL)
3623 return false;
3624
3625 elf32_arm_local_iplt (abfd) = bfd_zalloc
3626 (abfd, num_syms * sizeof (* elf32_arm_local_iplt (abfd)));
3627
3628 if (elf32_arm_local_iplt (abfd) == NULL)
3629 return false;
3630
3631 elf32_arm_local_fdpic_cnts (abfd) = bfd_zalloc
3632 (abfd, num_syms * sizeof (* elf32_arm_local_fdpic_cnts (abfd)));
3633
3634 if (elf32_arm_local_fdpic_cnts (abfd) == NULL)
3635 return false;
3636
3637 elf32_arm_local_got_tls_type (abfd) = bfd_zalloc
3638 (abfd, num_syms * sizeof (* elf32_arm_local_got_tls_type (abfd)));
3639
3640 if (elf32_arm_local_got_tls_type (abfd) == NULL)
3641 return false;
3642
3643 elf32_arm_num_entries (abfd) = num_syms;
3644
3645 #if GCC_VERSION >= 3000
3646 BFD_ASSERT (__alignof__ (*elf32_arm_local_tlsdesc_gotent (abfd))
3647 <= __alignof__ (*elf_local_got_refcounts (abfd)));
3648 BFD_ASSERT (__alignof__ (*elf32_arm_local_iplt (abfd))
3649 <= __alignof__ (*elf32_arm_local_tlsdesc_gotent (abfd)));
3650 BFD_ASSERT (__alignof__ (*elf32_arm_local_fdpic_cnts (abfd))
3651 <= __alignof__ (*elf32_arm_local_iplt (abfd)));
3652 BFD_ASSERT (__alignof__ (*elf32_arm_local_got_tls_type (abfd))
3653 <= __alignof__ (*elf32_arm_local_fdpic_cnts (abfd)));
3654 #endif
3655 }
3656 return true;
3657 }
3658
3659 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3660 to input bfd ABFD. Create the information if it doesn't already exist.
3661 Return null if an allocation fails. */
3662
3663 static struct arm_local_iplt_info *
3664 elf32_arm_create_local_iplt (bfd *abfd, unsigned long r_symndx)
3665 {
3666 struct arm_local_iplt_info **ptr;
3667
3668 if (!elf32_arm_allocate_local_sym_info (abfd))
3669 return NULL;
3670
3671 BFD_ASSERT (r_symndx < elf_tdata (abfd)->symtab_hdr.sh_info);
3672 BFD_ASSERT (r_symndx < elf32_arm_num_entries (abfd));
3673 ptr = &elf32_arm_local_iplt (abfd)[r_symndx];
3674 if (*ptr == NULL)
3675 *ptr = bfd_zalloc (abfd, sizeof (**ptr));
3676 return *ptr;
3677 }
3678
3679 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3680 in ABFD's symbol table. If the symbol is global, H points to its
3681 hash table entry, otherwise H is null.
3682
3683 Return true if the symbol does have PLT information. When returning
3684 true, point *ROOT_PLT at the target-independent reference count/offset
3685 union and *ARM_PLT at the ARM-specific information. */
3686
3687 static bool
3688 elf32_arm_get_plt_info (bfd *abfd, struct elf32_arm_link_hash_table *globals,
3689 struct elf32_arm_link_hash_entry *h,
3690 unsigned long r_symndx, union gotplt_union **root_plt,
3691 struct arm_plt_info **arm_plt)
3692 {
3693 struct arm_local_iplt_info *local_iplt;
3694
3695 if (globals->root.splt == NULL && globals->root.iplt == NULL)
3696 return false;
3697
3698 if (h != NULL)
3699 {
3700 *root_plt = &h->root.plt;
3701 *arm_plt = &h->plt;
3702 return true;
3703 }
3704
3705 if (elf32_arm_local_iplt (abfd) == NULL)
3706 return false;
3707
3708 if (r_symndx >= elf32_arm_num_entries (abfd))
3709 return false;
3710
3711 local_iplt = elf32_arm_local_iplt (abfd)[r_symndx];
3712 if (local_iplt == NULL)
3713 return false;
3714
3715 *root_plt = &local_iplt->root;
3716 *arm_plt = &local_iplt->arm;
3717 return true;
3718 }
3719
3720 static bool using_thumb_only (struct elf32_arm_link_hash_table *globals);
3721
3722 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3723 before it. */
3724
3725 static bool
3726 elf32_arm_plt_needs_thumb_stub_p (struct bfd_link_info *info,
3727 struct arm_plt_info *arm_plt)
3728 {
3729 struct elf32_arm_link_hash_table *htab;
3730
3731 htab = elf32_arm_hash_table (info);
3732
3733 return (!using_thumb_only (htab) && (arm_plt->thumb_refcount != 0
3734 || (!htab->use_blx && arm_plt->maybe_thumb_refcount != 0)));
3735 }
3736
3737 /* Return a pointer to the head of the dynamic reloc list that should
3738 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3739 ABFD's symbol table. Return null if an error occurs. */
3740
3741 static struct elf_dyn_relocs **
3742 elf32_arm_get_local_dynreloc_list (bfd *abfd, unsigned long r_symndx,
3743 Elf_Internal_Sym *isym)
3744 {
3745 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC)
3746 {
3747 struct arm_local_iplt_info *local_iplt;
3748
3749 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
3750 if (local_iplt == NULL)
3751 return NULL;
3752 return &local_iplt->dyn_relocs;
3753 }
3754 else
3755 {
3756 /* Track dynamic relocs needed for local syms too.
3757 We really need local syms available to do this
3758 easily. Oh well. */
3759 asection *s;
3760 void *vpp;
3761
3762 s = bfd_section_from_elf_index (abfd, isym->st_shndx);
3763 if (s == NULL)
3764 return NULL;
3765
3766 vpp = &elf_section_data (s)->local_dynrel;
3767 return (struct elf_dyn_relocs **) vpp;
3768 }
3769 }
3770
3771 /* Initialize an entry in the stub hash table. */
3772
3773 static struct bfd_hash_entry *
3774 stub_hash_newfunc (struct bfd_hash_entry *entry,
3775 struct bfd_hash_table *table,
3776 const char *string)
3777 {
3778 /* Allocate the structure if it has not already been allocated by a
3779 subclass. */
3780 if (entry == NULL)
3781 {
3782 entry = (struct bfd_hash_entry *)
3783 bfd_hash_allocate (table, sizeof (struct elf32_arm_stub_hash_entry));
3784 if (entry == NULL)
3785 return entry;
3786 }
3787
3788 /* Call the allocation method of the superclass. */
3789 entry = bfd_hash_newfunc (entry, table, string);
3790 if (entry != NULL)
3791 {
3792 struct elf32_arm_stub_hash_entry *eh;
3793
3794 /* Initialize the local fields. */
3795 eh = (struct elf32_arm_stub_hash_entry *) entry;
3796 eh->stub_sec = NULL;
3797 eh->stub_offset = (bfd_vma) -1;
3798 eh->source_value = 0;
3799 eh->target_value = 0;
3800 eh->target_section = NULL;
3801 eh->orig_insn = 0;
3802 eh->stub_type = arm_stub_none;
3803 eh->stub_size = 0;
3804 eh->stub_template = NULL;
3805 eh->stub_template_size = -1;
3806 eh->h = NULL;
3807 eh->id_sec = NULL;
3808 eh->output_name = NULL;
3809 }
3810
3811 return entry;
3812 }
3813
3814 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3815 shortcuts to them in our hash table. */
3816
3817 static bool
3818 create_got_section (bfd *dynobj, struct bfd_link_info *info)
3819 {
3820 struct elf32_arm_link_hash_table *htab;
3821
3822 htab = elf32_arm_hash_table (info);
3823 if (htab == NULL)
3824 return false;
3825
3826 if (! _bfd_elf_create_got_section (dynobj, info))
3827 return false;
3828
3829 /* Also create .rofixup. */
3830 if (htab->fdpic_p)
3831 {
3832 htab->srofixup = bfd_make_section_with_flags (dynobj, ".rofixup",
3833 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS
3834 | SEC_IN_MEMORY | SEC_LINKER_CREATED | SEC_READONLY));
3835 if (htab->srofixup == NULL
3836 || !bfd_set_section_alignment (htab->srofixup, 2))
3837 return false;
3838 }
3839
3840 return true;
3841 }
3842
3843 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3844
3845 static bool
3846 create_ifunc_sections (struct bfd_link_info *info)
3847 {
3848 struct elf32_arm_link_hash_table *htab;
3849 const struct elf_backend_data *bed;
3850 bfd *dynobj;
3851 asection *s;
3852 flagword flags;
3853
3854 htab = elf32_arm_hash_table (info);
3855 dynobj = htab->root.dynobj;
3856 bed = get_elf_backend_data (dynobj);
3857 flags = bed->dynamic_sec_flags;
3858
3859 if (htab->root.iplt == NULL)
3860 {
3861 s = bfd_make_section_anyway_with_flags (dynobj, ".iplt",
3862 flags | SEC_READONLY | SEC_CODE);
3863 if (s == NULL
3864 || !bfd_set_section_alignment (s, bed->plt_alignment))
3865 return false;
3866 htab->root.iplt = s;
3867 }
3868
3869 if (htab->root.irelplt == NULL)
3870 {
3871 s = bfd_make_section_anyway_with_flags (dynobj,
3872 RELOC_SECTION (htab, ".iplt"),
3873 flags | SEC_READONLY);
3874 if (s == NULL
3875 || !bfd_set_section_alignment (s, bed->s->log_file_align))
3876 return false;
3877 htab->root.irelplt = s;
3878 }
3879
3880 if (htab->root.igotplt == NULL)
3881 {
3882 s = bfd_make_section_anyway_with_flags (dynobj, ".igot.plt", flags);
3883 if (s == NULL
3884 || !bfd_set_section_alignment (s, bed->s->log_file_align))
3885 return false;
3886 htab->root.igotplt = s;
3887 }
3888 return true;
3889 }
3890
3891 /* Determine if we're dealing with a Thumb only architecture. */
3892
3893 static bool
3894 using_thumb_only (struct elf32_arm_link_hash_table *globals)
3895 {
3896 int arch;
3897 int profile = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3898 Tag_CPU_arch_profile);
3899
3900 if (profile)
3901 return profile == 'M';
3902
3903 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3904
3905 /* Force return logic to be reviewed for each new architecture. */
3906 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
3907
3908 if (arch == TAG_CPU_ARCH_V6_M
3909 || arch == TAG_CPU_ARCH_V6S_M
3910 || arch == TAG_CPU_ARCH_V7E_M
3911 || arch == TAG_CPU_ARCH_V8M_BASE
3912 || arch == TAG_CPU_ARCH_V8M_MAIN
3913 || arch == TAG_CPU_ARCH_V8_1M_MAIN)
3914 return true;
3915
3916 return false;
3917 }
3918
3919 /* Determine if we're dealing with a Thumb-2 object. */
3920
3921 static bool
3922 using_thumb2 (struct elf32_arm_link_hash_table *globals)
3923 {
3924 int arch;
3925 int thumb_isa = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
3926 Tag_THUMB_ISA_use);
3927
3928 /* No use of thumb permitted, or a legacy thumb-1/2 definition. */
3929 if (thumb_isa < 3)
3930 return thumb_isa == 2;
3931
3932 /* Variant of thumb is described by the architecture tag. */
3933 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3934
3935 /* Force return logic to be reviewed for each new architecture. */
3936 BFD_ASSERT (arch <= TAG_CPU_ARCH_V8_1M_MAIN);
3937
3938 return (arch == TAG_CPU_ARCH_V6T2
3939 || arch == TAG_CPU_ARCH_V7
3940 || arch == TAG_CPU_ARCH_V7E_M
3941 || arch == TAG_CPU_ARCH_V8
3942 || arch == TAG_CPU_ARCH_V8R
3943 || arch == TAG_CPU_ARCH_V8M_MAIN
3944 || arch == TAG_CPU_ARCH_V8_1M_MAIN);
3945 }
3946
3947 /* Determine whether Thumb-2 BL instruction is available. */
3948
3949 static bool
3950 using_thumb2_bl (struct elf32_arm_link_hash_table *globals)
3951 {
3952 int arch =
3953 bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
3954
3955 /* Force return logic to be reviewed for each new architecture. */
3956 BFD_ASSERT (arch <= TAG_CPU_ARCH_V9);
3957
3958 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3959 return (arch == TAG_CPU_ARCH_V6T2
3960 || arch >= TAG_CPU_ARCH_V7);
3961 }
3962
3963 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3964 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3965 hash table. */
3966
3967 static bool
3968 elf32_arm_create_dynamic_sections (bfd *dynobj, struct bfd_link_info *info)
3969 {
3970 struct elf32_arm_link_hash_table *htab;
3971
3972 htab = elf32_arm_hash_table (info);
3973 if (htab == NULL)
3974 return false;
3975
3976 if (!htab->root.sgot && !create_got_section (dynobj, info))
3977 return false;
3978
3979 if (!_bfd_elf_create_dynamic_sections (dynobj, info))
3980 return false;
3981
3982 if (htab->root.target_os == is_vxworks)
3983 {
3984 if (!elf_vxworks_create_dynamic_sections (dynobj, info, &htab->srelplt2))
3985 return false;
3986
3987 if (bfd_link_pic (info))
3988 {
3989 htab->plt_header_size = 0;
3990 htab->plt_entry_size
3991 = 4 * ARRAY_SIZE (elf32_arm_vxworks_shared_plt_entry);
3992 }
3993 else
3994 {
3995 htab->plt_header_size
3996 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt0_entry);
3997 htab->plt_entry_size
3998 = 4 * ARRAY_SIZE (elf32_arm_vxworks_exec_plt_entry);
3999 }
4000
4001 if (elf_elfheader (dynobj))
4002 elf_elfheader (dynobj)->e_ident[EI_CLASS] = ELFCLASS32;
4003 }
4004 else
4005 {
4006 /* PR ld/16017
4007 Test for thumb only architectures. Note - we cannot just call
4008 using_thumb_only() as the attributes in the output bfd have not been
4009 initialised at this point, so instead we use the input bfd. */
4010 bfd * saved_obfd = htab->obfd;
4011
4012 htab->obfd = dynobj;
4013 if (using_thumb_only (htab))
4014 {
4015 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
4016 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
4017 }
4018 htab->obfd = saved_obfd;
4019 }
4020
4021 if (htab->fdpic_p) {
4022 htab->plt_header_size = 0;
4023 if (info->flags & DF_BIND_NOW)
4024 htab->plt_entry_size = 4 * (ARRAY_SIZE (elf32_arm_fdpic_plt_entry) - 5);
4025 else
4026 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_fdpic_plt_entry);
4027 }
4028
4029 if (!htab->root.splt
4030 || !htab->root.srelplt
4031 || !htab->root.sdynbss
4032 || (!bfd_link_pic (info) && !htab->root.srelbss))
4033 abort ();
4034
4035 return true;
4036 }
4037
4038 /* Copy the extra info we tack onto an elf_link_hash_entry. */
4039
4040 static void
4041 elf32_arm_copy_indirect_symbol (struct bfd_link_info *info,
4042 struct elf_link_hash_entry *dir,
4043 struct elf_link_hash_entry *ind)
4044 {
4045 struct elf32_arm_link_hash_entry *edir, *eind;
4046
4047 edir = (struct elf32_arm_link_hash_entry *) dir;
4048 eind = (struct elf32_arm_link_hash_entry *) ind;
4049
4050 if (ind->root.type == bfd_link_hash_indirect)
4051 {
4052 /* Copy over PLT info. */
4053 edir->plt.thumb_refcount += eind->plt.thumb_refcount;
4054 eind->plt.thumb_refcount = 0;
4055 edir->plt.maybe_thumb_refcount += eind->plt.maybe_thumb_refcount;
4056 eind->plt.maybe_thumb_refcount = 0;
4057 edir->plt.noncall_refcount += eind->plt.noncall_refcount;
4058 eind->plt.noncall_refcount = 0;
4059
4060 /* Copy FDPIC counters. */
4061 edir->fdpic_cnts.gotofffuncdesc_cnt += eind->fdpic_cnts.gotofffuncdesc_cnt;
4062 edir->fdpic_cnts.gotfuncdesc_cnt += eind->fdpic_cnts.gotfuncdesc_cnt;
4063 edir->fdpic_cnts.funcdesc_cnt += eind->fdpic_cnts.funcdesc_cnt;
4064
4065 /* We should only allocate a function to .iplt once the final
4066 symbol information is known. */
4067 BFD_ASSERT (!eind->is_iplt);
4068
4069 if (dir->got.refcount <= 0)
4070 {
4071 edir->tls_type = eind->tls_type;
4072 eind->tls_type = GOT_UNKNOWN;
4073 }
4074 }
4075
4076 _bfd_elf_link_hash_copy_indirect (info, dir, ind);
4077 }
4078
4079 /* Destroy an ARM elf linker hash table. */
4080
4081 static void
4082 elf32_arm_link_hash_table_free (bfd *obfd)
4083 {
4084 struct elf32_arm_link_hash_table *ret
4085 = (struct elf32_arm_link_hash_table *) obfd->link.hash;
4086
4087 bfd_hash_table_free (&ret->stub_hash_table);
4088 _bfd_elf_link_hash_table_free (obfd);
4089 }
4090
4091 /* Create an ARM elf linker hash table. */
4092
4093 static struct bfd_link_hash_table *
4094 elf32_arm_link_hash_table_create (bfd *abfd)
4095 {
4096 struct elf32_arm_link_hash_table *ret;
4097 size_t amt = sizeof (struct elf32_arm_link_hash_table);
4098
4099 ret = (struct elf32_arm_link_hash_table *) bfd_zmalloc (amt);
4100 if (ret == NULL)
4101 return NULL;
4102
4103 if (!_bfd_elf_link_hash_table_init (& ret->root, abfd,
4104 elf32_arm_link_hash_newfunc,
4105 sizeof (struct elf32_arm_link_hash_entry),
4106 ARM_ELF_DATA))
4107 {
4108 free (ret);
4109 return NULL;
4110 }
4111
4112 ret->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
4113 ret->stm32l4xx_fix = BFD_ARM_STM32L4XX_FIX_NONE;
4114 #ifdef FOUR_WORD_PLT
4115 ret->plt_header_size = 16;
4116 ret->plt_entry_size = 16;
4117 #else
4118 ret->plt_header_size = 20;
4119 ret->plt_entry_size = elf32_arm_use_long_plt_entry ? 16 : 12;
4120 #endif
4121 ret->use_rel = true;
4122 ret->obfd = abfd;
4123 ret->fdpic_p = 0;
4124
4125 if (!bfd_hash_table_init (&ret->stub_hash_table, stub_hash_newfunc,
4126 sizeof (struct elf32_arm_stub_hash_entry)))
4127 {
4128 _bfd_elf_link_hash_table_free (abfd);
4129 return NULL;
4130 }
4131 ret->root.root.hash_table_free = elf32_arm_link_hash_table_free;
4132
4133 return &ret->root.root;
4134 }
4135
4136 /* Determine what kind of NOPs are available. */
4137
4138 static bool
4139 arch_has_arm_nop (struct elf32_arm_link_hash_table *globals)
4140 {
4141 const int arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
4142 Tag_CPU_arch);
4143
4144 /* Force return logic to be reviewed for each new architecture. */
4145 BFD_ASSERT (arch <= TAG_CPU_ARCH_V9);
4146
4147 return (arch == TAG_CPU_ARCH_V6T2
4148 || arch == TAG_CPU_ARCH_V6K
4149 || arch == TAG_CPU_ARCH_V7
4150 || arch == TAG_CPU_ARCH_V8
4151 || arch == TAG_CPU_ARCH_V8R
4152 || arch == TAG_CPU_ARCH_V9);
4153 }
4154
4155 static bool
4156 arm_stub_is_thumb (enum elf32_arm_stub_type stub_type)
4157 {
4158 switch (stub_type)
4159 {
4160 case arm_stub_long_branch_thumb_only:
4161 case arm_stub_long_branch_thumb2_only:
4162 case arm_stub_long_branch_thumb2_only_pure:
4163 case arm_stub_long_branch_v4t_thumb_arm:
4164 case arm_stub_short_branch_v4t_thumb_arm:
4165 case arm_stub_long_branch_v4t_thumb_arm_pic:
4166 case arm_stub_long_branch_v4t_thumb_tls_pic:
4167 case arm_stub_long_branch_thumb_only_pic:
4168 case arm_stub_cmse_branch_thumb_only:
4169 return true;
4170 case arm_stub_none:
4171 BFD_FAIL ();
4172 return false;
4173 break;
4174 default:
4175 return false;
4176 }
4177 }
4178
4179 /* Determine the type of stub needed, if any, for a call. */
4180
4181 static enum elf32_arm_stub_type
4182 arm_type_of_stub (struct bfd_link_info *info,
4183 asection *input_sec,
4184 const Elf_Internal_Rela *rel,
4185 unsigned char st_type,
4186 enum arm_st_branch_type *actual_branch_type,
4187 struct elf32_arm_link_hash_entry *hash,
4188 bfd_vma destination,
4189 asection *sym_sec,
4190 bfd *input_bfd,
4191 const char *name)
4192 {
4193 bfd_vma location;
4194 bfd_signed_vma branch_offset;
4195 unsigned int r_type;
4196 struct elf32_arm_link_hash_table * globals;
4197 bool thumb2, thumb2_bl, thumb_only;
4198 enum elf32_arm_stub_type stub_type = arm_stub_none;
4199 int use_plt = 0;
4200 enum arm_st_branch_type branch_type = *actual_branch_type;
4201 union gotplt_union *root_plt;
4202 struct arm_plt_info *arm_plt;
4203 int arch;
4204 int thumb2_movw;
4205
4206 if (branch_type == ST_BRANCH_LONG)
4207 return stub_type;
4208
4209 globals = elf32_arm_hash_table (info);
4210 if (globals == NULL)
4211 return stub_type;
4212
4213 thumb_only = using_thumb_only (globals);
4214 thumb2 = using_thumb2 (globals);
4215 thumb2_bl = using_thumb2_bl (globals);
4216
4217 arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC, Tag_CPU_arch);
4218
4219 /* True for architectures that implement the thumb2 movw instruction. */
4220 thumb2_movw = thumb2 || (arch == TAG_CPU_ARCH_V8M_BASE);
4221
4222 /* Determine where the call point is. */
4223 location = (input_sec->output_offset
4224 + input_sec->output_section->vma
4225 + rel->r_offset);
4226
4227 r_type = ELF32_R_TYPE (rel->r_info);
4228
4229 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4230 are considering a function call relocation. */
4231 if (thumb_only && (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
4232 || r_type == R_ARM_THM_JUMP19)
4233 && branch_type == ST_BRANCH_TO_ARM)
4234 branch_type = ST_BRANCH_TO_THUMB;
4235
4236 /* For TLS call relocs, it is the caller's responsibility to provide
4237 the address of the appropriate trampoline. */
4238 if (r_type != R_ARM_TLS_CALL
4239 && r_type != R_ARM_THM_TLS_CALL
4240 && elf32_arm_get_plt_info (input_bfd, globals, hash,
4241 ELF32_R_SYM (rel->r_info), &root_plt,
4242 &arm_plt)
4243 && root_plt->offset != (bfd_vma) -1)
4244 {
4245 asection *splt;
4246
4247 if (hash == NULL || hash->is_iplt)
4248 splt = globals->root.iplt;
4249 else
4250 splt = globals->root.splt;
4251 if (splt != NULL)
4252 {
4253 use_plt = 1;
4254
4255 /* Note when dealing with PLT entries: the main PLT stub is in
4256 ARM mode, so if the branch is in Thumb mode, another
4257 Thumb->ARM stub will be inserted later just before the ARM
4258 PLT stub. If a long branch stub is needed, we'll add a
4259 Thumb->Arm one and branch directly to the ARM PLT entry.
4260 Here, we have to check if a pre-PLT Thumb->ARM stub
4261 is needed and if it will be close enough. */
4262
4263 destination = (splt->output_section->vma
4264 + splt->output_offset
4265 + root_plt->offset);
4266 st_type = STT_FUNC;
4267
4268 /* Thumb branch/call to PLT: it can become a branch to ARM
4269 or to Thumb. We must perform the same checks and
4270 corrections as in elf32_arm_final_link_relocate. */
4271 if ((r_type == R_ARM_THM_CALL)
4272 || (r_type == R_ARM_THM_JUMP24))
4273 {
4274 if (globals->use_blx
4275 && r_type == R_ARM_THM_CALL
4276 && !thumb_only)
4277 {
4278 /* If the Thumb BLX instruction is available, convert
4279 the BL to a BLX instruction to call the ARM-mode
4280 PLT entry. */
4281 branch_type = ST_BRANCH_TO_ARM;
4282 }
4283 else
4284 {
4285 if (!thumb_only)
4286 /* Target the Thumb stub before the ARM PLT entry. */
4287 destination -= PLT_THUMB_STUB_SIZE;
4288 branch_type = ST_BRANCH_TO_THUMB;
4289 }
4290 }
4291 else
4292 {
4293 branch_type = ST_BRANCH_TO_ARM;
4294 }
4295 }
4296 }
4297 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4298 BFD_ASSERT (st_type != STT_GNU_IFUNC);
4299
4300 branch_offset = (bfd_signed_vma)(destination - location);
4301
4302 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24
4303 || r_type == R_ARM_THM_TLS_CALL || r_type == R_ARM_THM_JUMP19)
4304 {
4305 /* Handle cases where:
4306 - this call goes too far (different Thumb/Thumb2 max
4307 distance)
4308 - it's a Thumb->Arm call and blx is not available, or it's a
4309 Thumb->Arm branch (not bl). A stub is needed in this case,
4310 but only if this call is not through a PLT entry. Indeed,
4311 PLT stubs handle mode switching already. */
4312 if ((!thumb2_bl
4313 && (branch_offset > THM_MAX_FWD_BRANCH_OFFSET
4314 || (branch_offset < THM_MAX_BWD_BRANCH_OFFSET)))
4315 || (thumb2_bl
4316 && (branch_offset > THM2_MAX_FWD_BRANCH_OFFSET
4317 || (branch_offset < THM2_MAX_BWD_BRANCH_OFFSET)))
4318 || (thumb2
4319 && (branch_offset > THM2_MAX_FWD_COND_BRANCH_OFFSET
4320 || (branch_offset < THM2_MAX_BWD_COND_BRANCH_OFFSET))
4321 && (r_type == R_ARM_THM_JUMP19))
4322 || (branch_type == ST_BRANCH_TO_ARM
4323 && (((r_type == R_ARM_THM_CALL
4324 || r_type == R_ARM_THM_TLS_CALL) && !globals->use_blx)
4325 || (r_type == R_ARM_THM_JUMP24)
4326 || (r_type == R_ARM_THM_JUMP19))
4327 && !use_plt))
4328 {
4329 /* If we need to insert a Thumb-Thumb long branch stub to a
4330 PLT, use one that branches directly to the ARM PLT
4331 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4332 stub, undo this now. */
4333 if ((branch_type == ST_BRANCH_TO_THUMB) && use_plt && !thumb_only)
4334 {
4335 branch_type = ST_BRANCH_TO_ARM;
4336 branch_offset += PLT_THUMB_STUB_SIZE;
4337 }
4338
4339 if (branch_type == ST_BRANCH_TO_THUMB)
4340 {
4341 /* Thumb to thumb. */
4342 if (!thumb_only)
4343 {
4344 if (input_sec->flags & SEC_ELF_PURECODE)
4345 _bfd_error_handler
4346 (_("%pB(%pA): warning: long branch veneers used in"
4347 " section with SHF_ARM_PURECODE section"
4348 " attribute is only supported for M-profile"
4349 " targets that implement the movw instruction"),
4350 input_bfd, input_sec);
4351
4352 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4353 /* PIC stubs. */
4354 ? ((globals->use_blx
4355 && (r_type == R_ARM_THM_CALL))
4356 /* V5T and above. Stub starts with ARM code, so
4357 we must be able to switch mode before
4358 reaching it, which is only possible for 'bl'
4359 (ie R_ARM_THM_CALL relocation). */
4360 ? arm_stub_long_branch_any_thumb_pic
4361 /* On V4T, use Thumb code only. */
4362 : arm_stub_long_branch_v4t_thumb_thumb_pic)
4363
4364 /* non-PIC stubs. */
4365 : ((globals->use_blx
4366 && (r_type == R_ARM_THM_CALL))
4367 /* V5T and above. */
4368 ? arm_stub_long_branch_any_any
4369 /* V4T. */
4370 : arm_stub_long_branch_v4t_thumb_thumb);
4371 }
4372 else
4373 {
4374 if (thumb2_movw && (input_sec->flags & SEC_ELF_PURECODE))
4375 stub_type = arm_stub_long_branch_thumb2_only_pure;
4376 else
4377 {
4378 if (input_sec->flags & SEC_ELF_PURECODE)
4379 _bfd_error_handler
4380 (_("%pB(%pA): warning: long branch veneers used in"
4381 " section with SHF_ARM_PURECODE section"
4382 " attribute is only supported for M-profile"
4383 " targets that implement the movw instruction"),
4384 input_bfd, input_sec);
4385
4386 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4387 /* PIC stub. */
4388 ? arm_stub_long_branch_thumb_only_pic
4389 /* non-PIC stub. */
4390 : (thumb2 ? arm_stub_long_branch_thumb2_only
4391 : arm_stub_long_branch_thumb_only);
4392 }
4393 }
4394 }
4395 else
4396 {
4397 if (input_sec->flags & SEC_ELF_PURECODE)
4398 _bfd_error_handler
4399 (_("%pB(%pA): warning: long branch veneers used in"
4400 " section with SHF_ARM_PURECODE section"
4401 " attribute is only supported" " for M-profile"
4402 " targets that implement the movw instruction"),
4403 input_bfd, input_sec);
4404
4405 /* Thumb to arm. */
4406 if (sym_sec != NULL
4407 && sym_sec->owner != NULL
4408 && !INTERWORK_FLAG (sym_sec->owner))
4409 {
4410 _bfd_error_handler
4411 (_("%pB(%s): warning: interworking not enabled;"
4412 " first occurrence: %pB: %s call to %s"),
4413 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
4414 }
4415
4416 stub_type =
4417 (bfd_link_pic (info) | globals->pic_veneer)
4418 /* PIC stubs. */
4419 ? (r_type == R_ARM_THM_TLS_CALL
4420 /* TLS PIC stubs. */
4421 ? (globals->use_blx ? arm_stub_long_branch_any_tls_pic
4422 : arm_stub_long_branch_v4t_thumb_tls_pic)
4423 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4424 /* V5T PIC and above. */
4425 ? arm_stub_long_branch_any_arm_pic
4426 /* V4T PIC stub. */
4427 : arm_stub_long_branch_v4t_thumb_arm_pic))
4428
4429 /* non-PIC stubs. */
4430 : ((globals->use_blx && r_type == R_ARM_THM_CALL)
4431 /* V5T and above. */
4432 ? arm_stub_long_branch_any_any
4433 /* V4T. */
4434 : arm_stub_long_branch_v4t_thumb_arm);
4435
4436 /* Handle v4t short branches. */
4437 if ((stub_type == arm_stub_long_branch_v4t_thumb_arm)
4438 && (branch_offset <= THM_MAX_FWD_BRANCH_OFFSET)
4439 && (branch_offset >= THM_MAX_BWD_BRANCH_OFFSET))
4440 stub_type = arm_stub_short_branch_v4t_thumb_arm;
4441 }
4442 }
4443 }
4444 else if (r_type == R_ARM_CALL
4445 || r_type == R_ARM_JUMP24
4446 || r_type == R_ARM_PLT32
4447 || r_type == R_ARM_TLS_CALL)
4448 {
4449 if (input_sec->flags & SEC_ELF_PURECODE)
4450 _bfd_error_handler
4451 (_("%pB(%pA): warning: long branch veneers used in"
4452 " section with SHF_ARM_PURECODE section"
4453 " attribute is only supported for M-profile"
4454 " targets that implement the movw instruction"),
4455 input_bfd, input_sec);
4456 if (branch_type == ST_BRANCH_TO_THUMB)
4457 {
4458 /* Arm to thumb. */
4459
4460 if (sym_sec != NULL
4461 && sym_sec->owner != NULL
4462 && !INTERWORK_FLAG (sym_sec->owner))
4463 {
4464 _bfd_error_handler
4465 (_("%pB(%s): warning: interworking not enabled;"
4466 " first occurrence: %pB: %s call to %s"),
4467 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
4468 }
4469
4470 /* We have an extra 2-bytes reach because of
4471 the mode change (bit 24 (H) of BLX encoding). */
4472 if (branch_offset > (ARM_MAX_FWD_BRANCH_OFFSET + 2)
4473 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET)
4474 || (r_type == R_ARM_CALL && !globals->use_blx)
4475 || (r_type == R_ARM_JUMP24)
4476 || (r_type == R_ARM_PLT32))
4477 {
4478 stub_type = (bfd_link_pic (info) | globals->pic_veneer)
4479 /* PIC stubs. */
4480 ? ((globals->use_blx)
4481 /* V5T and above. */
4482 ? arm_stub_long_branch_any_thumb_pic
4483 /* V4T stub. */
4484 : arm_stub_long_branch_v4t_arm_thumb_pic)
4485
4486 /* non-PIC stubs. */
4487 : ((globals->use_blx)
4488 /* V5T and above. */
4489 ? arm_stub_long_branch_any_any
4490 /* V4T. */
4491 : arm_stub_long_branch_v4t_arm_thumb);
4492 }
4493 }
4494 else
4495 {
4496 /* Arm to arm. */
4497 if (branch_offset > ARM_MAX_FWD_BRANCH_OFFSET
4498 || (branch_offset < ARM_MAX_BWD_BRANCH_OFFSET))
4499 {
4500 stub_type =
4501 (bfd_link_pic (info) | globals->pic_veneer)
4502 /* PIC stubs. */
4503 ? (r_type == R_ARM_TLS_CALL
4504 /* TLS PIC Stub. */
4505 ? arm_stub_long_branch_any_tls_pic
4506 : (globals->root.target_os == is_nacl
4507 ? arm_stub_long_branch_arm_nacl_pic
4508 : arm_stub_long_branch_any_arm_pic))
4509 /* non-PIC stubs. */
4510 : (globals->root.target_os == is_nacl
4511 ? arm_stub_long_branch_arm_nacl
4512 : arm_stub_long_branch_any_any);
4513 }
4514 }
4515 }
4516
4517 /* If a stub is needed, record the actual destination type. */
4518 if (stub_type != arm_stub_none)
4519 *actual_branch_type = branch_type;
4520
4521 return stub_type;
4522 }
4523
4524 /* Build a name for an entry in the stub hash table. */
4525
4526 static char *
4527 elf32_arm_stub_name (const asection *input_section,
4528 const asection *sym_sec,
4529 const struct elf32_arm_link_hash_entry *hash,
4530 const Elf_Internal_Rela *rel,
4531 enum elf32_arm_stub_type stub_type)
4532 {
4533 char *stub_name;
4534 bfd_size_type len;
4535
4536 if (hash)
4537 {
4538 len = 8 + 1 + strlen (hash->root.root.root.string) + 1 + 8 + 1 + 2 + 1;
4539 stub_name = (char *) bfd_malloc (len);
4540 if (stub_name != NULL)
4541 sprintf (stub_name, "%08x_%s+%x_%d",
4542 input_section->id & 0xffffffff,
4543 hash->root.root.root.string,
4544 (int) rel->r_addend & 0xffffffff,
4545 (int) stub_type);
4546 }
4547 else
4548 {
4549 len = 8 + 1 + 8 + 1 + 8 + 1 + 8 + 1 + 2 + 1;
4550 stub_name = (char *) bfd_malloc (len);
4551 if (stub_name != NULL)
4552 sprintf (stub_name, "%08x_%x:%x+%x_%d",
4553 input_section->id & 0xffffffff,
4554 sym_sec->id & 0xffffffff,
4555 ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
4556 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL
4557 ? 0 : (int) ELF32_R_SYM (rel->r_info) & 0xffffffff,
4558 (int) rel->r_addend & 0xffffffff,
4559 (int) stub_type);
4560 }
4561
4562 return stub_name;
4563 }
4564
4565 /* Look up an entry in the stub hash. Stub entries are cached because
4566 creating the stub name takes a bit of time. */
4567
4568 static struct elf32_arm_stub_hash_entry *
4569 elf32_arm_get_stub_entry (const asection *input_section,
4570 const asection *sym_sec,
4571 struct elf_link_hash_entry *hash,
4572 const Elf_Internal_Rela *rel,
4573 struct elf32_arm_link_hash_table *htab,
4574 enum elf32_arm_stub_type stub_type)
4575 {
4576 struct elf32_arm_stub_hash_entry *stub_entry;
4577 struct elf32_arm_link_hash_entry *h = (struct elf32_arm_link_hash_entry *) hash;
4578 const asection *id_sec;
4579
4580 if ((input_section->flags & SEC_CODE) == 0)
4581 return NULL;
4582
4583 /* If the input section is the CMSE stubs one and it needs a long
4584 branch stub to reach it's final destination, give up with an
4585 error message: this is not supported. See PR ld/24709. */
4586 if (!strncmp (input_section->name, CMSE_STUB_NAME, strlen (CMSE_STUB_NAME)))
4587 {
4588 bfd *output_bfd = htab->obfd;
4589 asection *out_sec = bfd_get_section_by_name (output_bfd, CMSE_STUB_NAME);
4590
4591 _bfd_error_handler (_("ERROR: CMSE stub (%s section) too far "
4592 "(%#" PRIx64 ") from destination (%#" PRIx64 ")"),
4593 CMSE_STUB_NAME,
4594 (uint64_t)out_sec->output_section->vma
4595 + out_sec->output_offset,
4596 (uint64_t)sym_sec->output_section->vma
4597 + sym_sec->output_offset
4598 + h->root.root.u.def.value);
4599 /* Exit, rather than leave incompletely processed
4600 relocations. */
4601 xexit (1);
4602 }
4603
4604 /* If this input section is part of a group of sections sharing one
4605 stub section, then use the id of the first section in the group.
4606 Stub names need to include a section id, as there may well be
4607 more than one stub used to reach say, printf, and we need to
4608 distinguish between them. */
4609 BFD_ASSERT (input_section->id <= htab->top_id);
4610 id_sec = htab->stub_group[input_section->id].link_sec;
4611
4612 if (h != NULL && h->stub_cache != NULL
4613 && h->stub_cache->h == h
4614 && h->stub_cache->id_sec == id_sec
4615 && h->stub_cache->stub_type == stub_type)
4616 {
4617 stub_entry = h->stub_cache;
4618 }
4619 else
4620 {
4621 char *stub_name;
4622
4623 stub_name = elf32_arm_stub_name (id_sec, sym_sec, h, rel, stub_type);
4624 if (stub_name == NULL)
4625 return NULL;
4626
4627 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table,
4628 stub_name, false, false);
4629 if (h != NULL)
4630 h->stub_cache = stub_entry;
4631
4632 free (stub_name);
4633 }
4634
4635 return stub_entry;
4636 }
4637
4638 /* Whether veneers of type STUB_TYPE require to be in a dedicated output
4639 section. */
4640
4641 static bool
4642 arm_dedicated_stub_output_section_required (enum elf32_arm_stub_type stub_type)
4643 {
4644 if (stub_type >= max_stub_type)
4645 abort (); /* Should be unreachable. */
4646
4647 switch (stub_type)
4648 {
4649 case arm_stub_cmse_branch_thumb_only:
4650 return true;
4651
4652 default:
4653 return false;
4654 }
4655
4656 abort (); /* Should be unreachable. */
4657 }
4658
4659 /* Required alignment (as a power of 2) for the dedicated section holding
4660 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4661 with input sections. */
4662
4663 static int
4664 arm_dedicated_stub_output_section_required_alignment
4665 (enum elf32_arm_stub_type stub_type)
4666 {
4667 if (stub_type >= max_stub_type)
4668 abort (); /* Should be unreachable. */
4669
4670 switch (stub_type)
4671 {
4672 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4673 boundary. */
4674 case arm_stub_cmse_branch_thumb_only:
4675 return 5;
4676
4677 default:
4678 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4679 return 0;
4680 }
4681
4682 abort (); /* Should be unreachable. */
4683 }
4684
4685 /* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4686 NULL if veneers of this type are interspersed with input sections. */
4687
4688 static const char *
4689 arm_dedicated_stub_output_section_name (enum elf32_arm_stub_type stub_type)
4690 {
4691 if (stub_type >= max_stub_type)
4692 abort (); /* Should be unreachable. */
4693
4694 switch (stub_type)
4695 {
4696 case arm_stub_cmse_branch_thumb_only:
4697 return CMSE_STUB_NAME;
4698
4699 default:
4700 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4701 return NULL;
4702 }
4703
4704 abort (); /* Should be unreachable. */
4705 }
4706
4707 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4708 returns the address of the hash table field in HTAB holding a pointer to the
4709 corresponding input section. Otherwise, returns NULL. */
4710
4711 static asection **
4712 arm_dedicated_stub_input_section_ptr (struct elf32_arm_link_hash_table *htab,
4713 enum elf32_arm_stub_type stub_type)
4714 {
4715 if (stub_type >= max_stub_type)
4716 abort (); /* Should be unreachable. */
4717
4718 switch (stub_type)
4719 {
4720 case arm_stub_cmse_branch_thumb_only:
4721 return &htab->cmse_stub_sec;
4722
4723 default:
4724 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
4725 return NULL;
4726 }
4727
4728 abort (); /* Should be unreachable. */
4729 }
4730
4731 /* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4732 is the section that branch into veneer and can be NULL if stub should go in
4733 a dedicated output section. Returns a pointer to the stub section, and the
4734 section to which the stub section will be attached (in *LINK_SEC_P).
4735 LINK_SEC_P may be NULL. */
4736
4737 static asection *
4738 elf32_arm_create_or_find_stub_sec (asection **link_sec_p, asection *section,
4739 struct elf32_arm_link_hash_table *htab,
4740 enum elf32_arm_stub_type stub_type)
4741 {
4742 asection *link_sec, *out_sec, **stub_sec_p;
4743 const char *stub_sec_prefix;
4744 bool dedicated_output_section =
4745 arm_dedicated_stub_output_section_required (stub_type);
4746 int align;
4747
4748 if (dedicated_output_section)
4749 {
4750 bfd *output_bfd = htab->obfd;
4751 const char *out_sec_name =
4752 arm_dedicated_stub_output_section_name (stub_type);
4753 link_sec = NULL;
4754 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
4755 stub_sec_prefix = out_sec_name;
4756 align = arm_dedicated_stub_output_section_required_alignment (stub_type);
4757 out_sec = bfd_get_section_by_name (output_bfd, out_sec_name);
4758 if (out_sec == NULL)
4759 {
4760 _bfd_error_handler (_("no address assigned to the veneers output "
4761 "section %s"), out_sec_name);
4762 return NULL;
4763 }
4764 }
4765 else
4766 {
4767 BFD_ASSERT (section->id <= htab->top_id);
4768 link_sec = htab->stub_group[section->id].link_sec;
4769 BFD_ASSERT (link_sec != NULL);
4770 stub_sec_p = &htab->stub_group[section->id].stub_sec;
4771 if (*stub_sec_p == NULL)
4772 stub_sec_p = &htab->stub_group[link_sec->id].stub_sec;
4773 stub_sec_prefix = link_sec->name;
4774 out_sec = link_sec->output_section;
4775 align = htab->root.target_os == is_nacl ? 4 : 3;
4776 }
4777
4778 if (*stub_sec_p == NULL)
4779 {
4780 size_t namelen;
4781 bfd_size_type len;
4782 char *s_name;
4783
4784 namelen = strlen (stub_sec_prefix);
4785 len = namelen + sizeof (STUB_SUFFIX);
4786 s_name = (char *) bfd_alloc (htab->stub_bfd, len);
4787 if (s_name == NULL)
4788 return NULL;
4789
4790 memcpy (s_name, stub_sec_prefix, namelen);
4791 memcpy (s_name + namelen, STUB_SUFFIX, sizeof (STUB_SUFFIX));
4792 *stub_sec_p = (*htab->add_stub_section) (s_name, out_sec, link_sec,
4793 align);
4794 if (*stub_sec_p == NULL)
4795 return NULL;
4796
4797 out_sec->flags |= SEC_ALLOC | SEC_LOAD | SEC_READONLY | SEC_CODE
4798 | SEC_HAS_CONTENTS | SEC_RELOC | SEC_IN_MEMORY
4799 | SEC_KEEP;
4800 }
4801
4802 if (!dedicated_output_section)
4803 htab->stub_group[section->id].stub_sec = *stub_sec_p;
4804
4805 if (link_sec_p)
4806 *link_sec_p = link_sec;
4807
4808 return *stub_sec_p;
4809 }
4810
4811 /* Add a new stub entry to the stub hash. Not all fields of the new
4812 stub entry are initialised. */
4813
4814 static struct elf32_arm_stub_hash_entry *
4815 elf32_arm_add_stub (const char *stub_name, asection *section,
4816 struct elf32_arm_link_hash_table *htab,
4817 enum elf32_arm_stub_type stub_type)
4818 {
4819 asection *link_sec;
4820 asection *stub_sec;
4821 struct elf32_arm_stub_hash_entry *stub_entry;
4822
4823 stub_sec = elf32_arm_create_or_find_stub_sec (&link_sec, section, htab,
4824 stub_type);
4825 if (stub_sec == NULL)
4826 return NULL;
4827
4828 /* Enter this entry into the linker stub hash table. */
4829 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
4830 true, false);
4831 if (stub_entry == NULL)
4832 {
4833 if (section == NULL)
4834 section = stub_sec;
4835 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
4836 section->owner, stub_name);
4837 return NULL;
4838 }
4839
4840 stub_entry->stub_sec = stub_sec;
4841 stub_entry->stub_offset = (bfd_vma) -1;
4842 stub_entry->id_sec = link_sec;
4843
4844 return stub_entry;
4845 }
4846
4847 /* Store an Arm insn into an output section not processed by
4848 elf32_arm_write_section. */
4849
4850 static void
4851 put_arm_insn (struct elf32_arm_link_hash_table * htab,
4852 bfd * output_bfd, bfd_vma val, void * ptr)
4853 {
4854 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4855 bfd_putl32 (val, ptr);
4856 else
4857 bfd_putb32 (val, ptr);
4858 }
4859
4860 /* Store a 16-bit Thumb insn into an output section not processed by
4861 elf32_arm_write_section. */
4862
4863 static void
4864 put_thumb_insn (struct elf32_arm_link_hash_table * htab,
4865 bfd * output_bfd, bfd_vma val, void * ptr)
4866 {
4867 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4868 bfd_putl16 (val, ptr);
4869 else
4870 bfd_putb16 (val, ptr);
4871 }
4872
4873 /* Store a Thumb2 insn into an output section not processed by
4874 elf32_arm_write_section. */
4875
4876 static void
4877 put_thumb2_insn (struct elf32_arm_link_hash_table * htab,
4878 bfd * output_bfd, bfd_vma val, bfd_byte * ptr)
4879 {
4880 /* T2 instructions are 16-bit streamed. */
4881 if (htab->byteswap_code != bfd_little_endian (output_bfd))
4882 {
4883 bfd_putl16 ((val >> 16) & 0xffff, ptr);
4884 bfd_putl16 ((val & 0xffff), ptr + 2);
4885 }
4886 else
4887 {
4888 bfd_putb16 ((val >> 16) & 0xffff, ptr);
4889 bfd_putb16 ((val & 0xffff), ptr + 2);
4890 }
4891 }
4892
4893 /* If it's possible to change R_TYPE to a more efficient access
4894 model, return the new reloc type. */
4895
4896 static unsigned
4897 elf32_arm_tls_transition (struct bfd_link_info *info, int r_type,
4898 struct elf_link_hash_entry *h)
4899 {
4900 int is_local = (h == NULL);
4901
4902 if (bfd_link_dll (info)
4903 || (h && h->root.type == bfd_link_hash_undefweak))
4904 return r_type;
4905
4906 /* We do not support relaxations for Old TLS models. */
4907 switch (r_type)
4908 {
4909 case R_ARM_TLS_GOTDESC:
4910 case R_ARM_TLS_CALL:
4911 case R_ARM_THM_TLS_CALL:
4912 case R_ARM_TLS_DESCSEQ:
4913 case R_ARM_THM_TLS_DESCSEQ:
4914 return is_local ? R_ARM_TLS_LE32 : R_ARM_TLS_IE32;
4915 }
4916
4917 return r_type;
4918 }
4919
4920 static bfd_reloc_status_type elf32_arm_final_link_relocate
4921 (reloc_howto_type *, bfd *, bfd *, asection *, bfd_byte *,
4922 Elf_Internal_Rela *, bfd_vma, struct bfd_link_info *, asection *,
4923 const char *, unsigned char, enum arm_st_branch_type,
4924 struct elf_link_hash_entry *, bool *, char **);
4925
4926 static unsigned int
4927 arm_stub_required_alignment (enum elf32_arm_stub_type stub_type)
4928 {
4929 switch (stub_type)
4930 {
4931 case arm_stub_a8_veneer_b_cond:
4932 case arm_stub_a8_veneer_b:
4933 case arm_stub_a8_veneer_bl:
4934 return 2;
4935
4936 case arm_stub_long_branch_any_any:
4937 case arm_stub_long_branch_v4t_arm_thumb:
4938 case arm_stub_long_branch_thumb_only:
4939 case arm_stub_long_branch_thumb2_only:
4940 case arm_stub_long_branch_thumb2_only_pure:
4941 case arm_stub_long_branch_v4t_thumb_thumb:
4942 case arm_stub_long_branch_v4t_thumb_arm:
4943 case arm_stub_short_branch_v4t_thumb_arm:
4944 case arm_stub_long_branch_any_arm_pic:
4945 case arm_stub_long_branch_any_thumb_pic:
4946 case arm_stub_long_branch_v4t_thumb_thumb_pic:
4947 case arm_stub_long_branch_v4t_arm_thumb_pic:
4948 case arm_stub_long_branch_v4t_thumb_arm_pic:
4949 case arm_stub_long_branch_thumb_only_pic:
4950 case arm_stub_long_branch_any_tls_pic:
4951 case arm_stub_long_branch_v4t_thumb_tls_pic:
4952 case arm_stub_cmse_branch_thumb_only:
4953 case arm_stub_a8_veneer_blx:
4954 return 4;
4955
4956 case arm_stub_long_branch_arm_nacl:
4957 case arm_stub_long_branch_arm_nacl_pic:
4958 return 16;
4959
4960 default:
4961 abort (); /* Should be unreachable. */
4962 }
4963 }
4964
4965 /* Returns whether stubs of type STUB_TYPE take over the symbol they are
4966 veneering (TRUE) or have their own symbol (FALSE). */
4967
4968 static bool
4969 arm_stub_sym_claimed (enum elf32_arm_stub_type stub_type)
4970 {
4971 if (stub_type >= max_stub_type)
4972 abort (); /* Should be unreachable. */
4973
4974 switch (stub_type)
4975 {
4976 case arm_stub_cmse_branch_thumb_only:
4977 return true;
4978
4979 default:
4980 return false;
4981 }
4982
4983 abort (); /* Should be unreachable. */
4984 }
4985
4986 /* Returns the padding needed for the dedicated section used stubs of type
4987 STUB_TYPE. */
4988
4989 static int
4990 arm_dedicated_stub_section_padding (enum elf32_arm_stub_type stub_type)
4991 {
4992 if (stub_type >= max_stub_type)
4993 abort (); /* Should be unreachable. */
4994
4995 switch (stub_type)
4996 {
4997 case arm_stub_cmse_branch_thumb_only:
4998 return 32;
4999
5000 default:
5001 return 0;
5002 }
5003
5004 abort (); /* Should be unreachable. */
5005 }
5006
5007 /* If veneers of type STUB_TYPE should go in a dedicated output section,
5008 returns the address of the hash table field in HTAB holding the offset at
5009 which new veneers should be layed out in the stub section. */
5010
5011 static bfd_vma*
5012 arm_new_stubs_start_offset_ptr (struct elf32_arm_link_hash_table *htab,
5013 enum elf32_arm_stub_type stub_type)
5014 {
5015 switch (stub_type)
5016 {
5017 case arm_stub_cmse_branch_thumb_only:
5018 return &htab->new_cmse_stub_offset;
5019
5020 default:
5021 BFD_ASSERT (!arm_dedicated_stub_output_section_required (stub_type));
5022 return NULL;
5023 }
5024 }
5025
5026 static bool
5027 arm_build_one_stub (struct bfd_hash_entry *gen_entry,
5028 void * in_arg)
5029 {
5030 #define MAXRELOCS 3
5031 bool removed_sg_veneer;
5032 struct elf32_arm_stub_hash_entry *stub_entry;
5033 struct elf32_arm_link_hash_table *globals;
5034 struct bfd_link_info *info;
5035 asection *stub_sec;
5036 bfd *stub_bfd;
5037 bfd_byte *loc;
5038 bfd_vma sym_value;
5039 int template_size;
5040 int size;
5041 const insn_sequence *template_sequence;
5042 int i;
5043 int stub_reloc_idx[MAXRELOCS] = {-1, -1};
5044 int stub_reloc_offset[MAXRELOCS] = {0, 0};
5045 int nrelocs = 0;
5046 int just_allocated = 0;
5047
5048 /* Massage our args to the form they really have. */
5049 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5050 info = (struct bfd_link_info *) in_arg;
5051
5052 /* Fail if the target section could not be assigned to an output
5053 section. The user should fix his linker script. */
5054 if (stub_entry->target_section->output_section == NULL
5055 && info->non_contiguous_regions)
5056 info->callbacks->einfo (_("%F%P: Could not assign `%pA' to an output section. "
5057 "Retry without --enable-non-contiguous-regions.\n"),
5058 stub_entry->target_section);
5059
5060 globals = elf32_arm_hash_table (info);
5061 if (globals == NULL)
5062 return false;
5063
5064 stub_sec = stub_entry->stub_sec;
5065
5066 if ((globals->fix_cortex_a8 < 0)
5067 != (arm_stub_required_alignment (stub_entry->stub_type) == 2))
5068 /* We have to do less-strictly-aligned fixes last. */
5069 return true;
5070
5071 /* Assign a slot at the end of section if none assigned yet. */
5072 if (stub_entry->stub_offset == (bfd_vma) -1)
5073 {
5074 stub_entry->stub_offset = stub_sec->size;
5075 just_allocated = 1;
5076 }
5077 loc = stub_sec->contents + stub_entry->stub_offset;
5078
5079 stub_bfd = stub_sec->owner;
5080
5081 /* This is the address of the stub destination. */
5082 sym_value = (stub_entry->target_value
5083 + stub_entry->target_section->output_offset
5084 + stub_entry->target_section->output_section->vma);
5085
5086 template_sequence = stub_entry->stub_template;
5087 template_size = stub_entry->stub_template_size;
5088
5089 size = 0;
5090 for (i = 0; i < template_size; i++)
5091 {
5092 switch (template_sequence[i].type)
5093 {
5094 case THUMB16_TYPE:
5095 {
5096 bfd_vma data = (bfd_vma) template_sequence[i].data;
5097 if (template_sequence[i].reloc_addend != 0)
5098 {
5099 /* We've borrowed the reloc_addend field to mean we should
5100 insert a condition code into this (Thumb-1 branch)
5101 instruction. See THUMB16_BCOND_INSN. */
5102 BFD_ASSERT ((data & 0xff00) == 0xd000);
5103 data |= ((stub_entry->orig_insn >> 22) & 0xf) << 8;
5104 }
5105 bfd_put_16 (stub_bfd, data, loc + size);
5106 size += 2;
5107 }
5108 break;
5109
5110 case THUMB32_TYPE:
5111 bfd_put_16 (stub_bfd,
5112 (template_sequence[i].data >> 16) & 0xffff,
5113 loc + size);
5114 bfd_put_16 (stub_bfd, template_sequence[i].data & 0xffff,
5115 loc + size + 2);
5116 if (template_sequence[i].r_type != R_ARM_NONE)
5117 {
5118 stub_reloc_idx[nrelocs] = i;
5119 stub_reloc_offset[nrelocs++] = size;
5120 }
5121 size += 4;
5122 break;
5123
5124 case ARM_TYPE:
5125 bfd_put_32 (stub_bfd, template_sequence[i].data,
5126 loc + size);
5127 /* Handle cases where the target is encoded within the
5128 instruction. */
5129 if (template_sequence[i].r_type == R_ARM_JUMP24)
5130 {
5131 stub_reloc_idx[nrelocs] = i;
5132 stub_reloc_offset[nrelocs++] = size;
5133 }
5134 size += 4;
5135 break;
5136
5137 case DATA_TYPE:
5138 bfd_put_32 (stub_bfd, template_sequence[i].data, loc + size);
5139 stub_reloc_idx[nrelocs] = i;
5140 stub_reloc_offset[nrelocs++] = size;
5141 size += 4;
5142 break;
5143
5144 default:
5145 BFD_FAIL ();
5146 return false;
5147 }
5148 }
5149
5150 if (just_allocated)
5151 stub_sec->size += size;
5152
5153 /* Stub size has already been computed in arm_size_one_stub. Check
5154 consistency. */
5155 BFD_ASSERT (size == stub_entry->stub_size);
5156
5157 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
5158 if (stub_entry->branch_type == ST_BRANCH_TO_THUMB)
5159 sym_value |= 1;
5160
5161 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5162 to relocate in each stub. */
5163 removed_sg_veneer =
5164 (size == 0 && stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
5165 BFD_ASSERT (removed_sg_veneer || (nrelocs != 0 && nrelocs <= MAXRELOCS));
5166
5167 for (i = 0; i < nrelocs; i++)
5168 {
5169 Elf_Internal_Rela rel;
5170 bool unresolved_reloc;
5171 char *error_message;
5172 bfd_vma points_to =
5173 sym_value + template_sequence[stub_reloc_idx[i]].reloc_addend;
5174
5175 rel.r_offset = stub_entry->stub_offset + stub_reloc_offset[i];
5176 rel.r_info = ELF32_R_INFO (0,
5177 template_sequence[stub_reloc_idx[i]].r_type);
5178 rel.r_addend = 0;
5179
5180 if (stub_entry->stub_type == arm_stub_a8_veneer_b_cond && i == 0)
5181 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5182 template should refer back to the instruction after the original
5183 branch. We use target_section as Cortex-A8 erratum workaround stubs
5184 are only generated when both source and target are in the same
5185 section. */
5186 points_to = stub_entry->target_section->output_section->vma
5187 + stub_entry->target_section->output_offset
5188 + stub_entry->source_value;
5189
5190 elf32_arm_final_link_relocate (elf32_arm_howto_from_type
5191 (template_sequence[stub_reloc_idx[i]].r_type),
5192 stub_bfd, info->output_bfd, stub_sec, stub_sec->contents, &rel,
5193 points_to, info, stub_entry->target_section, "", STT_FUNC,
5194 stub_entry->branch_type,
5195 (struct elf_link_hash_entry *) stub_entry->h, &unresolved_reloc,
5196 &error_message);
5197 }
5198
5199 return true;
5200 #undef MAXRELOCS
5201 }
5202
5203 /* Calculate the template, template size and instruction size for a stub.
5204 Return value is the instruction size. */
5205
5206 static unsigned int
5207 find_stub_size_and_template (enum elf32_arm_stub_type stub_type,
5208 const insn_sequence **stub_template,
5209 int *stub_template_size)
5210 {
5211 const insn_sequence *template_sequence = NULL;
5212 int template_size = 0, i;
5213 unsigned int size;
5214
5215 template_sequence = stub_definitions[stub_type].template_sequence;
5216 if (stub_template)
5217 *stub_template = template_sequence;
5218
5219 template_size = stub_definitions[stub_type].template_size;
5220 if (stub_template_size)
5221 *stub_template_size = template_size;
5222
5223 size = 0;
5224 for (i = 0; i < template_size; i++)
5225 {
5226 switch (template_sequence[i].type)
5227 {
5228 case THUMB16_TYPE:
5229 size += 2;
5230 break;
5231
5232 case ARM_TYPE:
5233 case THUMB32_TYPE:
5234 case DATA_TYPE:
5235 size += 4;
5236 break;
5237
5238 default:
5239 BFD_FAIL ();
5240 return 0;
5241 }
5242 }
5243
5244 return size;
5245 }
5246
5247 /* As above, but don't actually build the stub. Just bump offset so
5248 we know stub section sizes. */
5249
5250 static bool
5251 arm_size_one_stub (struct bfd_hash_entry *gen_entry,
5252 void *in_arg ATTRIBUTE_UNUSED)
5253 {
5254 struct elf32_arm_stub_hash_entry *stub_entry;
5255 const insn_sequence *template_sequence;
5256 int template_size, size;
5257
5258 /* Massage our args to the form they really have. */
5259 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
5260
5261 BFD_ASSERT ((stub_entry->stub_type > arm_stub_none)
5262 && stub_entry->stub_type < ARRAY_SIZE (stub_definitions));
5263
5264 size = find_stub_size_and_template (stub_entry->stub_type, &template_sequence,
5265 &template_size);
5266
5267 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5268 if (stub_entry->stub_template_size)
5269 {
5270 stub_entry->stub_size = size;
5271 stub_entry->stub_template = template_sequence;
5272 stub_entry->stub_template_size = template_size;
5273 }
5274
5275 /* Already accounted for. */
5276 if (stub_entry->stub_offset != (bfd_vma) -1)
5277 return true;
5278
5279 size = (size + 7) & ~7;
5280 stub_entry->stub_sec->size += size;
5281
5282 return true;
5283 }
5284
5285 /* External entry points for sizing and building linker stubs. */
5286
5287 /* Set up various things so that we can make a list of input sections
5288 for each output section included in the link. Returns -1 on error,
5289 0 when no stubs will be needed, and 1 on success. */
5290
5291 int
5292 elf32_arm_setup_section_lists (bfd *output_bfd,
5293 struct bfd_link_info *info)
5294 {
5295 bfd *input_bfd;
5296 unsigned int bfd_count;
5297 unsigned int top_id, top_index;
5298 asection *section;
5299 asection **input_list, **list;
5300 size_t amt;
5301 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5302
5303 if (htab == NULL)
5304 return 0;
5305
5306 /* Count the number of input BFDs and find the top input section id. */
5307 for (input_bfd = info->input_bfds, bfd_count = 0, top_id = 0;
5308 input_bfd != NULL;
5309 input_bfd = input_bfd->link.next)
5310 {
5311 bfd_count += 1;
5312 for (section = input_bfd->sections;
5313 section != NULL;
5314 section = section->next)
5315 {
5316 if (top_id < section->id)
5317 top_id = section->id;
5318 }
5319 }
5320 htab->bfd_count = bfd_count;
5321
5322 amt = sizeof (struct map_stub) * (top_id + 1);
5323 htab->stub_group = (struct map_stub *) bfd_zmalloc (amt);
5324 if (htab->stub_group == NULL)
5325 return -1;
5326 htab->top_id = top_id;
5327
5328 /* We can't use output_bfd->section_count here to find the top output
5329 section index as some sections may have been removed, and
5330 _bfd_strip_section_from_output doesn't renumber the indices. */
5331 for (section = output_bfd->sections, top_index = 0;
5332 section != NULL;
5333 section = section->next)
5334 {
5335 if (top_index < section->index)
5336 top_index = section->index;
5337 }
5338
5339 htab->top_index = top_index;
5340 amt = sizeof (asection *) * (top_index + 1);
5341 input_list = (asection **) bfd_malloc (amt);
5342 htab->input_list = input_list;
5343 if (input_list == NULL)
5344 return -1;
5345
5346 /* For sections we aren't interested in, mark their entries with a
5347 value we can check later. */
5348 list = input_list + top_index;
5349 do
5350 *list = bfd_abs_section_ptr;
5351 while (list-- != input_list);
5352
5353 for (section = output_bfd->sections;
5354 section != NULL;
5355 section = section->next)
5356 {
5357 if ((section->flags & SEC_CODE) != 0)
5358 input_list[section->index] = NULL;
5359 }
5360
5361 return 1;
5362 }
5363
5364 /* The linker repeatedly calls this function for each input section,
5365 in the order that input sections are linked into output sections.
5366 Build lists of input sections to determine groupings between which
5367 we may insert linker stubs. */
5368
5369 void
5370 elf32_arm_next_input_section (struct bfd_link_info *info,
5371 asection *isec)
5372 {
5373 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5374
5375 if (htab == NULL)
5376 return;
5377
5378 if (isec->output_section->index <= htab->top_index)
5379 {
5380 asection **list = htab->input_list + isec->output_section->index;
5381
5382 if (*list != bfd_abs_section_ptr && (isec->flags & SEC_CODE) != 0)
5383 {
5384 /* Steal the link_sec pointer for our list. */
5385 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5386 /* This happens to make the list in reverse order,
5387 which we reverse later. */
5388 PREV_SEC (isec) = *list;
5389 *list = isec;
5390 }
5391 }
5392 }
5393
5394 /* See whether we can group stub sections together. Grouping stub
5395 sections may result in fewer stubs. More importantly, we need to
5396 put all .init* and .fini* stubs at the end of the .init or
5397 .fini output sections respectively, because glibc splits the
5398 _init and _fini functions into multiple parts. Putting a stub in
5399 the middle of a function is not a good idea. */
5400
5401 static void
5402 group_sections (struct elf32_arm_link_hash_table *htab,
5403 bfd_size_type stub_group_size,
5404 bool stubs_always_after_branch)
5405 {
5406 asection **list = htab->input_list;
5407
5408 do
5409 {
5410 asection *tail = *list;
5411 asection *head;
5412
5413 if (tail == bfd_abs_section_ptr)
5414 continue;
5415
5416 /* Reverse the list: we must avoid placing stubs at the
5417 beginning of the section because the beginning of the text
5418 section may be required for an interrupt vector in bare metal
5419 code. */
5420 #define NEXT_SEC PREV_SEC
5421 head = NULL;
5422 while (tail != NULL)
5423 {
5424 /* Pop from tail. */
5425 asection *item = tail;
5426 tail = PREV_SEC (item);
5427
5428 /* Push on head. */
5429 NEXT_SEC (item) = head;
5430 head = item;
5431 }
5432
5433 while (head != NULL)
5434 {
5435 asection *curr;
5436 asection *next;
5437 bfd_vma stub_group_start = head->output_offset;
5438 bfd_vma end_of_next;
5439
5440 curr = head;
5441 while (NEXT_SEC (curr) != NULL)
5442 {
5443 next = NEXT_SEC (curr);
5444 end_of_next = next->output_offset + next->size;
5445 if (end_of_next - stub_group_start >= stub_group_size)
5446 /* End of NEXT is too far from start, so stop. */
5447 break;
5448 /* Add NEXT to the group. */
5449 curr = next;
5450 }
5451
5452 /* OK, the size from the start to the start of CURR is less
5453 than stub_group_size and thus can be handled by one stub
5454 section. (Or the head section is itself larger than
5455 stub_group_size, in which case we may be toast.)
5456 We should really be keeping track of the total size of
5457 stubs added here, as stubs contribute to the final output
5458 section size. */
5459 do
5460 {
5461 next = NEXT_SEC (head);
5462 /* Set up this stub group. */
5463 htab->stub_group[head->id].link_sec = curr;
5464 }
5465 while (head != curr && (head = next) != NULL);
5466
5467 /* But wait, there's more! Input sections up to stub_group_size
5468 bytes after the stub section can be handled by it too. */
5469 if (!stubs_always_after_branch)
5470 {
5471 stub_group_start = curr->output_offset + curr->size;
5472
5473 while (next != NULL)
5474 {
5475 end_of_next = next->output_offset + next->size;
5476 if (end_of_next - stub_group_start >= stub_group_size)
5477 /* End of NEXT is too far from stubs, so stop. */
5478 break;
5479 /* Add NEXT to the stub group. */
5480 head = next;
5481 next = NEXT_SEC (head);
5482 htab->stub_group[head->id].link_sec = curr;
5483 }
5484 }
5485 head = next;
5486 }
5487 }
5488 while (list++ != htab->input_list + htab->top_index);
5489
5490 free (htab->input_list);
5491 #undef PREV_SEC
5492 #undef NEXT_SEC
5493 }
5494
5495 /* Comparison function for sorting/searching relocations relating to Cortex-A8
5496 erratum fix. */
5497
5498 static int
5499 a8_reloc_compare (const void *a, const void *b)
5500 {
5501 const struct a8_erratum_reloc *ra = (const struct a8_erratum_reloc *) a;
5502 const struct a8_erratum_reloc *rb = (const struct a8_erratum_reloc *) b;
5503
5504 if (ra->from < rb->from)
5505 return -1;
5506 else if (ra->from > rb->from)
5507 return 1;
5508 else
5509 return 0;
5510 }
5511
5512 static struct elf_link_hash_entry *find_thumb_glue (struct bfd_link_info *,
5513 const char *, char **);
5514
5515 /* Helper function to scan code for sequences which might trigger the Cortex-A8
5516 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
5517 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
5518 otherwise. */
5519
5520 static bool
5521 cortex_a8_erratum_scan (bfd *input_bfd,
5522 struct bfd_link_info *info,
5523 struct a8_erratum_fix **a8_fixes_p,
5524 unsigned int *num_a8_fixes_p,
5525 unsigned int *a8_fix_table_size_p,
5526 struct a8_erratum_reloc *a8_relocs,
5527 unsigned int num_a8_relocs,
5528 unsigned prev_num_a8_fixes,
5529 bool *stub_changed_p)
5530 {
5531 asection *section;
5532 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
5533 struct a8_erratum_fix *a8_fixes = *a8_fixes_p;
5534 unsigned int num_a8_fixes = *num_a8_fixes_p;
5535 unsigned int a8_fix_table_size = *a8_fix_table_size_p;
5536
5537 if (htab == NULL)
5538 return false;
5539
5540 for (section = input_bfd->sections;
5541 section != NULL;
5542 section = section->next)
5543 {
5544 bfd_byte *contents = NULL;
5545 struct _arm_elf_section_data *sec_data;
5546 unsigned int span;
5547 bfd_vma base_vma;
5548
5549 if (elf_section_type (section) != SHT_PROGBITS
5550 || (elf_section_flags (section) & SHF_EXECINSTR) == 0
5551 || (section->flags & SEC_EXCLUDE) != 0
5552 || (section->sec_info_type == SEC_INFO_TYPE_JUST_SYMS)
5553 || (section->output_section == bfd_abs_section_ptr))
5554 continue;
5555
5556 base_vma = section->output_section->vma + section->output_offset;
5557
5558 if (elf_section_data (section)->this_hdr.contents != NULL)
5559 contents = elf_section_data (section)->this_hdr.contents;
5560 else if (! bfd_malloc_and_get_section (input_bfd, section, &contents))
5561 return true;
5562
5563 sec_data = elf32_arm_section_data (section);
5564
5565 for (span = 0; span < sec_data->mapcount; span++)
5566 {
5567 unsigned int span_start = sec_data->map[span].vma;
5568 unsigned int span_end = (span == sec_data->mapcount - 1)
5569 ? section->size : sec_data->map[span + 1].vma;
5570 unsigned int i;
5571 char span_type = sec_data->map[span].type;
5572 bool last_was_32bit = false, last_was_branch = false;
5573
5574 if (span_type != 't')
5575 continue;
5576
5577 /* Span is entirely within a single 4KB region: skip scanning. */
5578 if (((base_vma + span_start) & ~0xfff)
5579 == ((base_vma + span_end) & ~0xfff))
5580 continue;
5581
5582 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5583
5584 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5585 * The branch target is in the same 4KB region as the
5586 first half of the branch.
5587 * The instruction before the branch is a 32-bit
5588 length non-branch instruction. */
5589 for (i = span_start; i < span_end;)
5590 {
5591 unsigned int insn = bfd_getl16 (&contents[i]);
5592 bool insn_32bit = false, is_blx = false, is_b = false;
5593 bool is_bl = false, is_bcc = false, is_32bit_branch;
5594
5595 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
5596 insn_32bit = true;
5597
5598 if (insn_32bit)
5599 {
5600 /* Load the rest of the insn (in manual-friendly order). */
5601 insn = (insn << 16) | bfd_getl16 (&contents[i + 2]);
5602
5603 /* Encoding T4: B<c>.W. */
5604 is_b = (insn & 0xf800d000) == 0xf0009000;
5605 /* Encoding T1: BL<c>.W. */
5606 is_bl = (insn & 0xf800d000) == 0xf000d000;
5607 /* Encoding T2: BLX<c>.W. */
5608 is_blx = (insn & 0xf800d000) == 0xf000c000;
5609 /* Encoding T3: B<c>.W (not permitted in IT block). */
5610 is_bcc = (insn & 0xf800d000) == 0xf0008000
5611 && (insn & 0x07f00000) != 0x03800000;
5612 }
5613
5614 is_32bit_branch = is_b || is_bl || is_blx || is_bcc;
5615
5616 if (((base_vma + i) & 0xfff) == 0xffe
5617 && insn_32bit
5618 && is_32bit_branch
5619 && last_was_32bit
5620 && ! last_was_branch)
5621 {
5622 bfd_signed_vma offset = 0;
5623 bool force_target_arm = false;
5624 bool force_target_thumb = false;
5625 bfd_vma target;
5626 enum elf32_arm_stub_type stub_type = arm_stub_none;
5627 struct a8_erratum_reloc key, *found;
5628 bool use_plt = false;
5629
5630 key.from = base_vma + i;
5631 found = (struct a8_erratum_reloc *)
5632 bsearch (&key, a8_relocs, num_a8_relocs,
5633 sizeof (struct a8_erratum_reloc),
5634 &a8_reloc_compare);
5635
5636 if (found)
5637 {
5638 char *error_message = NULL;
5639 struct elf_link_hash_entry *entry;
5640
5641 /* We don't care about the error returned from this
5642 function, only if there is glue or not. */
5643 entry = find_thumb_glue (info, found->sym_name,
5644 &error_message);
5645
5646 if (entry)
5647 found->non_a8_stub = true;
5648
5649 /* Keep a simpler condition, for the sake of clarity. */
5650 if (htab->root.splt != NULL && found->hash != NULL
5651 && found->hash->root.plt.offset != (bfd_vma) -1)
5652 use_plt = true;
5653
5654 if (found->r_type == R_ARM_THM_CALL)
5655 {
5656 if (found->branch_type == ST_BRANCH_TO_ARM
5657 || use_plt)
5658 force_target_arm = true;
5659 else
5660 force_target_thumb = true;
5661 }
5662 }
5663
5664 /* Check if we have an offending branch instruction. */
5665
5666 if (found && found->non_a8_stub)
5667 /* We've already made a stub for this instruction, e.g.
5668 it's a long branch or a Thumb->ARM stub. Assume that
5669 stub will suffice to work around the A8 erratum (see
5670 setting of always_after_branch above). */
5671 ;
5672 else if (is_bcc)
5673 {
5674 offset = (insn & 0x7ff) << 1;
5675 offset |= (insn & 0x3f0000) >> 4;
5676 offset |= (insn & 0x2000) ? 0x40000 : 0;
5677 offset |= (insn & 0x800) ? 0x80000 : 0;
5678 offset |= (insn & 0x4000000) ? 0x100000 : 0;
5679 if (offset & 0x100000)
5680 offset |= ~ ((bfd_signed_vma) 0xfffff);
5681 stub_type = arm_stub_a8_veneer_b_cond;
5682 }
5683 else if (is_b || is_bl || is_blx)
5684 {
5685 int s = (insn & 0x4000000) != 0;
5686 int j1 = (insn & 0x2000) != 0;
5687 int j2 = (insn & 0x800) != 0;
5688 int i1 = !(j1 ^ s);
5689 int i2 = !(j2 ^ s);
5690
5691 offset = (insn & 0x7ff) << 1;
5692 offset |= (insn & 0x3ff0000) >> 4;
5693 offset |= i2 << 22;
5694 offset |= i1 << 23;
5695 offset |= s << 24;
5696 if (offset & 0x1000000)
5697 offset |= ~ ((bfd_signed_vma) 0xffffff);
5698
5699 if (is_blx)
5700 offset &= ~ ((bfd_signed_vma) 3);
5701
5702 stub_type = is_blx ? arm_stub_a8_veneer_blx :
5703 is_bl ? arm_stub_a8_veneer_bl : arm_stub_a8_veneer_b;
5704 }
5705
5706 if (stub_type != arm_stub_none)
5707 {
5708 bfd_vma pc_for_insn = base_vma + i + 4;
5709
5710 /* The original instruction is a BL, but the target is
5711 an ARM instruction. If we were not making a stub,
5712 the BL would have been converted to a BLX. Use the
5713 BLX stub instead in that case. */
5714 if (htab->use_blx && force_target_arm
5715 && stub_type == arm_stub_a8_veneer_bl)
5716 {
5717 stub_type = arm_stub_a8_veneer_blx;
5718 is_blx = true;
5719 is_bl = false;
5720 }
5721 /* Conversely, if the original instruction was
5722 BLX but the target is Thumb mode, use the BL
5723 stub. */
5724 else if (force_target_thumb
5725 && stub_type == arm_stub_a8_veneer_blx)
5726 {
5727 stub_type = arm_stub_a8_veneer_bl;
5728 is_blx = false;
5729 is_bl = true;
5730 }
5731
5732 if (is_blx)
5733 pc_for_insn &= ~ ((bfd_vma) 3);
5734
5735 /* If we found a relocation, use the proper destination,
5736 not the offset in the (unrelocated) instruction.
5737 Note this is always done if we switched the stub type
5738 above. */
5739 if (found)
5740 offset =
5741 (bfd_signed_vma) (found->destination - pc_for_insn);
5742
5743 /* If the stub will use a Thumb-mode branch to a
5744 PLT target, redirect it to the preceding Thumb
5745 entry point. */
5746 if (stub_type != arm_stub_a8_veneer_blx && use_plt)
5747 offset -= PLT_THUMB_STUB_SIZE;
5748
5749 target = pc_for_insn + offset;
5750
5751 /* The BLX stub is ARM-mode code. Adjust the offset to
5752 take the different PC value (+8 instead of +4) into
5753 account. */
5754 if (stub_type == arm_stub_a8_veneer_blx)
5755 offset += 4;
5756
5757 if (((base_vma + i) & ~0xfff) == (target & ~0xfff))
5758 {
5759 char *stub_name = NULL;
5760
5761 if (num_a8_fixes == a8_fix_table_size)
5762 {
5763 a8_fix_table_size *= 2;
5764 a8_fixes = (struct a8_erratum_fix *)
5765 bfd_realloc (a8_fixes,
5766 sizeof (struct a8_erratum_fix)
5767 * a8_fix_table_size);
5768 }
5769
5770 if (num_a8_fixes < prev_num_a8_fixes)
5771 {
5772 /* If we're doing a subsequent scan,
5773 check if we've found the same fix as
5774 before, and try and reuse the stub
5775 name. */
5776 stub_name = a8_fixes[num_a8_fixes].stub_name;
5777 if ((a8_fixes[num_a8_fixes].section != section)
5778 || (a8_fixes[num_a8_fixes].offset != i))
5779 {
5780 free (stub_name);
5781 stub_name = NULL;
5782 *stub_changed_p = true;
5783 }
5784 }
5785
5786 if (!stub_name)
5787 {
5788 stub_name = (char *) bfd_malloc (8 + 1 + 8 + 1);
5789 if (stub_name != NULL)
5790 sprintf (stub_name, "%x:%x", section->id, i);
5791 }
5792
5793 a8_fixes[num_a8_fixes].input_bfd = input_bfd;
5794 a8_fixes[num_a8_fixes].section = section;
5795 a8_fixes[num_a8_fixes].offset = i;
5796 a8_fixes[num_a8_fixes].target_offset =
5797 target - base_vma;
5798 a8_fixes[num_a8_fixes].orig_insn = insn;
5799 a8_fixes[num_a8_fixes].stub_name = stub_name;
5800 a8_fixes[num_a8_fixes].stub_type = stub_type;
5801 a8_fixes[num_a8_fixes].branch_type =
5802 is_blx ? ST_BRANCH_TO_ARM : ST_BRANCH_TO_THUMB;
5803
5804 num_a8_fixes++;
5805 }
5806 }
5807 }
5808
5809 i += insn_32bit ? 4 : 2;
5810 last_was_32bit = insn_32bit;
5811 last_was_branch = is_32bit_branch;
5812 }
5813 }
5814
5815 if (elf_section_data (section)->this_hdr.contents == NULL)
5816 free (contents);
5817 }
5818
5819 *a8_fixes_p = a8_fixes;
5820 *num_a8_fixes_p = num_a8_fixes;
5821 *a8_fix_table_size_p = a8_fix_table_size;
5822
5823 return false;
5824 }
5825
5826 /* Create or update a stub entry depending on whether the stub can already be
5827 found in HTAB. The stub is identified by:
5828 - its type STUB_TYPE
5829 - its source branch (note that several can share the same stub) whose
5830 section and relocation (if any) are given by SECTION and IRELA
5831 respectively
5832 - its target symbol whose input section, hash, name, value and branch type
5833 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5834 respectively
5835
5836 If found, the value of the stub's target symbol is updated from SYM_VALUE
5837 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5838 TRUE and the stub entry is initialized.
5839
5840 Returns the stub that was created or updated, or NULL if an error
5841 occurred. */
5842
5843 static struct elf32_arm_stub_hash_entry *
5844 elf32_arm_create_stub (struct elf32_arm_link_hash_table *htab,
5845 enum elf32_arm_stub_type stub_type, asection *section,
5846 Elf_Internal_Rela *irela, asection *sym_sec,
5847 struct elf32_arm_link_hash_entry *hash, char *sym_name,
5848 bfd_vma sym_value, enum arm_st_branch_type branch_type,
5849 bool *new_stub)
5850 {
5851 const asection *id_sec;
5852 char *stub_name;
5853 struct elf32_arm_stub_hash_entry *stub_entry;
5854 unsigned int r_type;
5855 bool sym_claimed = arm_stub_sym_claimed (stub_type);
5856
5857 BFD_ASSERT (stub_type != arm_stub_none);
5858 *new_stub = false;
5859
5860 if (sym_claimed)
5861 stub_name = sym_name;
5862 else
5863 {
5864 BFD_ASSERT (irela);
5865 BFD_ASSERT (section);
5866 BFD_ASSERT (section->id <= htab->top_id);
5867
5868 /* Support for grouping stub sections. */
5869 id_sec = htab->stub_group[section->id].link_sec;
5870
5871 /* Get the name of this stub. */
5872 stub_name = elf32_arm_stub_name (id_sec, sym_sec, hash, irela,
5873 stub_type);
5874 if (!stub_name)
5875 return NULL;
5876 }
5877
5878 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name, false,
5879 false);
5880 /* The proper stub has already been created, just update its value. */
5881 if (stub_entry != NULL)
5882 {
5883 if (!sym_claimed)
5884 free (stub_name);
5885 stub_entry->target_value = sym_value;
5886 return stub_entry;
5887 }
5888
5889 stub_entry = elf32_arm_add_stub (stub_name, section, htab, stub_type);
5890 if (stub_entry == NULL)
5891 {
5892 if (!sym_claimed)
5893 free (stub_name);
5894 return NULL;
5895 }
5896
5897 stub_entry->target_value = sym_value;
5898 stub_entry->target_section = sym_sec;
5899 stub_entry->stub_type = stub_type;
5900 stub_entry->h = hash;
5901 stub_entry->branch_type = branch_type;
5902
5903 if (sym_claimed)
5904 stub_entry->output_name = sym_name;
5905 else
5906 {
5907 if (sym_name == NULL)
5908 sym_name = "unnamed";
5909 stub_entry->output_name = (char *)
5910 bfd_alloc (htab->stub_bfd, sizeof (THUMB2ARM_GLUE_ENTRY_NAME)
5911 + strlen (sym_name));
5912 if (stub_entry->output_name == NULL)
5913 {
5914 free (stub_name);
5915 return NULL;
5916 }
5917
5918 /* For historical reasons, use the existing names for ARM-to-Thumb and
5919 Thumb-to-ARM stubs. */
5920 r_type = ELF32_R_TYPE (irela->r_info);
5921 if ((r_type == (unsigned int) R_ARM_THM_CALL
5922 || r_type == (unsigned int) R_ARM_THM_JUMP24
5923 || r_type == (unsigned int) R_ARM_THM_JUMP19)
5924 && branch_type == ST_BRANCH_TO_ARM)
5925 sprintf (stub_entry->output_name, THUMB2ARM_GLUE_ENTRY_NAME, sym_name);
5926 else if ((r_type == (unsigned int) R_ARM_CALL
5927 || r_type == (unsigned int) R_ARM_JUMP24)
5928 && branch_type == ST_BRANCH_TO_THUMB)
5929 sprintf (stub_entry->output_name, ARM2THUMB_GLUE_ENTRY_NAME, sym_name);
5930 else
5931 sprintf (stub_entry->output_name, STUB_ENTRY_NAME, sym_name);
5932 }
5933
5934 *new_stub = true;
5935 return stub_entry;
5936 }
5937
5938 /* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5939 gateway veneer to transition from non secure to secure state and create them
5940 accordingly.
5941
5942 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5943 defines the conditions that govern Secure Gateway veneer creation for a
5944 given symbol <SYM> as follows:
5945 - it has function type
5946 - it has non local binding
5947 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5948 same type, binding and value as <SYM> (called normal symbol).
5949 An entry function can handle secure state transition itself in which case
5950 its special symbol would have a different value from the normal symbol.
5951
5952 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5953 entry mapping while HTAB gives the name to hash entry mapping.
5954 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5955 created.
5956
5957 The return value gives whether a stub failed to be allocated. */
5958
5959 static bool
5960 cmse_scan (bfd *input_bfd, struct elf32_arm_link_hash_table *htab,
5961 obj_attribute *out_attr, struct elf_link_hash_entry **sym_hashes,
5962 int *cmse_stub_created)
5963 {
5964 const struct elf_backend_data *bed;
5965 Elf_Internal_Shdr *symtab_hdr;
5966 unsigned i, j, sym_count, ext_start;
5967 Elf_Internal_Sym *cmse_sym, *local_syms;
5968 struct elf32_arm_link_hash_entry *hash, *cmse_hash = NULL;
5969 enum arm_st_branch_type branch_type;
5970 char *sym_name, *lsym_name;
5971 bfd_vma sym_value;
5972 asection *section;
5973 struct elf32_arm_stub_hash_entry *stub_entry;
5974 bool is_v8m, new_stub, cmse_invalid, ret = true;
5975
5976 bed = get_elf_backend_data (input_bfd);
5977 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
5978 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
5979 ext_start = symtab_hdr->sh_info;
5980 is_v8m = (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
5981 && out_attr[Tag_CPU_arch_profile].i == 'M');
5982
5983 local_syms = (Elf_Internal_Sym *) symtab_hdr->contents;
5984 if (local_syms == NULL)
5985 local_syms = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
5986 symtab_hdr->sh_info, 0, NULL, NULL,
5987 NULL);
5988 if (symtab_hdr->sh_info && local_syms == NULL)
5989 return false;
5990
5991 /* Scan symbols. */
5992 for (i = 0; i < sym_count; i++)
5993 {
5994 cmse_invalid = false;
5995
5996 if (i < ext_start)
5997 {
5998 cmse_sym = &local_syms[i];
5999 sym_name = bfd_elf_string_from_elf_section (input_bfd,
6000 symtab_hdr->sh_link,
6001 cmse_sym->st_name);
6002 if (!sym_name || !startswith (sym_name, CMSE_PREFIX))
6003 continue;
6004
6005 /* Special symbol with local binding. */
6006 cmse_invalid = true;
6007 }
6008 else
6009 {
6010 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
6011 if (cmse_hash == NULL)
6012 continue;
6013
6014 sym_name = (char *) cmse_hash->root.root.root.string;
6015 if (!startswith (sym_name, CMSE_PREFIX))
6016 continue;
6017
6018 /* Special symbol has incorrect binding or type. */
6019 if ((cmse_hash->root.root.type != bfd_link_hash_defined
6020 && cmse_hash->root.root.type != bfd_link_hash_defweak)
6021 || cmse_hash->root.type != STT_FUNC)
6022 cmse_invalid = true;
6023 }
6024
6025 if (!is_v8m)
6026 {
6027 _bfd_error_handler (_("%pB: special symbol `%s' only allowed for "
6028 "ARMv8-M architecture or later"),
6029 input_bfd, sym_name);
6030 is_v8m = true; /* Avoid multiple warning. */
6031 ret = false;
6032 }
6033
6034 if (cmse_invalid)
6035 {
6036 _bfd_error_handler (_("%pB: invalid special symbol `%s'; it must be"
6037 " a global or weak function symbol"),
6038 input_bfd, sym_name);
6039 ret = false;
6040 if (i < ext_start)
6041 continue;
6042 }
6043
6044 sym_name += strlen (CMSE_PREFIX);
6045 hash = (struct elf32_arm_link_hash_entry *)
6046 elf_link_hash_lookup (&(htab)->root, sym_name, false, false, true);
6047
6048 /* No associated normal symbol or it is neither global nor weak. */
6049 if (!hash
6050 || (hash->root.root.type != bfd_link_hash_defined
6051 && hash->root.root.type != bfd_link_hash_defweak)
6052 || hash->root.type != STT_FUNC)
6053 {
6054 /* Initialize here to avoid warning about use of possibly
6055 uninitialized variable. */
6056 j = 0;
6057
6058 if (!hash)
6059 {
6060 /* Searching for a normal symbol with local binding. */
6061 for (; j < ext_start; j++)
6062 {
6063 lsym_name =
6064 bfd_elf_string_from_elf_section (input_bfd,
6065 symtab_hdr->sh_link,
6066 local_syms[j].st_name);
6067 if (!strcmp (sym_name, lsym_name))
6068 break;
6069 }
6070 }
6071
6072 if (hash || j < ext_start)
6073 {
6074 _bfd_error_handler
6075 (_("%pB: invalid standard symbol `%s'; it must be "
6076 "a global or weak function symbol"),
6077 input_bfd, sym_name);
6078 }
6079 else
6080 _bfd_error_handler
6081 (_("%pB: absent standard symbol `%s'"), input_bfd, sym_name);
6082 ret = false;
6083 if (!hash)
6084 continue;
6085 }
6086
6087 sym_value = hash->root.root.u.def.value;
6088 section = hash->root.root.u.def.section;
6089
6090 if (cmse_hash->root.root.u.def.section != section)
6091 {
6092 _bfd_error_handler
6093 (_("%pB: `%s' and its special symbol are in different sections"),
6094 input_bfd, sym_name);
6095 ret = false;
6096 }
6097 if (cmse_hash->root.root.u.def.value != sym_value)
6098 continue; /* Ignore: could be an entry function starting with SG. */
6099
6100 /* If this section is a link-once section that will be discarded, then
6101 don't create any stubs. */
6102 if (section->output_section == NULL)
6103 {
6104 _bfd_error_handler
6105 (_("%pB: entry function `%s' not output"), input_bfd, sym_name);
6106 continue;
6107 }
6108
6109 if (hash->root.size == 0)
6110 {
6111 _bfd_error_handler
6112 (_("%pB: entry function `%s' is empty"), input_bfd, sym_name);
6113 ret = false;
6114 }
6115
6116 if (!ret)
6117 continue;
6118 branch_type = ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
6119 stub_entry
6120 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6121 NULL, NULL, section, hash, sym_name,
6122 sym_value, branch_type, &new_stub);
6123
6124 if (stub_entry == NULL)
6125 ret = false;
6126 else
6127 {
6128 BFD_ASSERT (new_stub);
6129 (*cmse_stub_created)++;
6130 }
6131 }
6132
6133 if (!symtab_hdr->contents)
6134 free (local_syms);
6135 return ret;
6136 }
6137
6138 /* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6139 code entry function, ie can be called from non secure code without using a
6140 veneer. */
6141
6142 static bool
6143 cmse_entry_fct_p (struct elf32_arm_link_hash_entry *hash)
6144 {
6145 bfd_byte contents[4];
6146 uint32_t first_insn;
6147 asection *section;
6148 file_ptr offset;
6149 bfd *abfd;
6150
6151 /* Defined symbol of function type. */
6152 if (hash->root.root.type != bfd_link_hash_defined
6153 && hash->root.root.type != bfd_link_hash_defweak)
6154 return false;
6155 if (hash->root.type != STT_FUNC)
6156 return false;
6157
6158 /* Read first instruction. */
6159 section = hash->root.root.u.def.section;
6160 abfd = section->owner;
6161 offset = hash->root.root.u.def.value - section->vma;
6162 if (!bfd_get_section_contents (abfd, section, contents, offset,
6163 sizeof (contents)))
6164 return false;
6165
6166 first_insn = bfd_get_32 (abfd, contents);
6167
6168 /* Starts by SG instruction. */
6169 return first_insn == 0xe97fe97f;
6170 }
6171
6172 /* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6173 secure gateway veneers (ie. the veneers was not in the input import library)
6174 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6175
6176 static bool
6177 arm_list_new_cmse_stub (struct bfd_hash_entry *gen_entry, void *gen_info)
6178 {
6179 struct elf32_arm_stub_hash_entry *stub_entry;
6180 struct bfd_link_info *info;
6181
6182 /* Massage our args to the form they really have. */
6183 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
6184 info = (struct bfd_link_info *) gen_info;
6185
6186 if (info->out_implib_bfd)
6187 return true;
6188
6189 if (stub_entry->stub_type != arm_stub_cmse_branch_thumb_only)
6190 return true;
6191
6192 if (stub_entry->stub_offset == (bfd_vma) -1)
6193 _bfd_error_handler (" %s", stub_entry->output_name);
6194
6195 return true;
6196 }
6197
6198 /* Set offset of each secure gateway veneers so that its address remain
6199 identical to the one in the input import library referred by
6200 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6201 (present in input import library but absent from the executable being
6202 linked) or if new veneers appeared and there is no output import library
6203 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6204 number of secure gateway veneers found in the input import library.
6205
6206 The function returns whether an error occurred. If no error occurred,
6207 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6208 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6209 veneer observed set for new veneers to be layed out after. */
6210
6211 static bool
6212 set_cmse_veneer_addr_from_implib (struct bfd_link_info *info,
6213 struct elf32_arm_link_hash_table *htab,
6214 int *cmse_stub_created)
6215 {
6216 long symsize;
6217 char *sym_name;
6218 flagword flags;
6219 long i, symcount;
6220 bfd *in_implib_bfd;
6221 asection *stub_out_sec;
6222 bool ret = true;
6223 Elf_Internal_Sym *intsym;
6224 const char *out_sec_name;
6225 bfd_size_type cmse_stub_size;
6226 asymbol **sympp = NULL, *sym;
6227 struct elf32_arm_link_hash_entry *hash;
6228 const insn_sequence *cmse_stub_template;
6229 struct elf32_arm_stub_hash_entry *stub_entry;
6230 int cmse_stub_template_size, new_cmse_stubs_created = *cmse_stub_created;
6231 bfd_vma veneer_value, stub_offset, next_cmse_stub_offset;
6232 bfd_vma cmse_stub_array_start = (bfd_vma) -1, cmse_stub_sec_vma = 0;
6233
6234 /* No input secure gateway import library. */
6235 if (!htab->in_implib_bfd)
6236 return true;
6237
6238 in_implib_bfd = htab->in_implib_bfd;
6239 if (!htab->cmse_implib)
6240 {
6241 _bfd_error_handler (_("%pB: --in-implib only supported for Secure "
6242 "Gateway import libraries"), in_implib_bfd);
6243 return false;
6244 }
6245
6246 /* Get symbol table size. */
6247 symsize = bfd_get_symtab_upper_bound (in_implib_bfd);
6248 if (symsize < 0)
6249 return false;
6250
6251 /* Read in the input secure gateway import library's symbol table. */
6252 sympp = (asymbol **) bfd_malloc (symsize);
6253 if (sympp == NULL)
6254 return false;
6255
6256 symcount = bfd_canonicalize_symtab (in_implib_bfd, sympp);
6257 if (symcount < 0)
6258 {
6259 ret = false;
6260 goto free_sym_buf;
6261 }
6262
6263 htab->new_cmse_stub_offset = 0;
6264 cmse_stub_size =
6265 find_stub_size_and_template (arm_stub_cmse_branch_thumb_only,
6266 &cmse_stub_template,
6267 &cmse_stub_template_size);
6268 out_sec_name =
6269 arm_dedicated_stub_output_section_name (arm_stub_cmse_branch_thumb_only);
6270 stub_out_sec =
6271 bfd_get_section_by_name (htab->obfd, out_sec_name);
6272 if (stub_out_sec != NULL)
6273 cmse_stub_sec_vma = stub_out_sec->vma;
6274
6275 /* Set addresses of veneers mentionned in input secure gateway import
6276 library's symbol table. */
6277 for (i = 0; i < symcount; i++)
6278 {
6279 sym = sympp[i];
6280 flags = sym->flags;
6281 sym_name = (char *) bfd_asymbol_name (sym);
6282 intsym = &((elf_symbol_type *) sym)->internal_elf_sym;
6283
6284 if (sym->section != bfd_abs_section_ptr
6285 || !(flags & (BSF_GLOBAL | BSF_WEAK))
6286 || (flags & BSF_FUNCTION) != BSF_FUNCTION
6287 || (ARM_GET_SYM_BRANCH_TYPE (intsym->st_target_internal)
6288 != ST_BRANCH_TO_THUMB))
6289 {
6290 _bfd_error_handler (_("%pB: invalid import library entry: `%s'; "
6291 "symbol should be absolute, global and "
6292 "refer to Thumb functions"),
6293 in_implib_bfd, sym_name);
6294 ret = false;
6295 continue;
6296 }
6297
6298 veneer_value = bfd_asymbol_value (sym);
6299 stub_offset = veneer_value - cmse_stub_sec_vma;
6300 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, sym_name,
6301 false, false);
6302 hash = (struct elf32_arm_link_hash_entry *)
6303 elf_link_hash_lookup (&(htab)->root, sym_name, false, false, true);
6304
6305 /* Stub entry should have been created by cmse_scan or the symbol be of
6306 a secure function callable from non secure code. */
6307 if (!stub_entry && !hash)
6308 {
6309 bool new_stub;
6310
6311 _bfd_error_handler
6312 (_("entry function `%s' disappeared from secure code"), sym_name);
6313 hash = (struct elf32_arm_link_hash_entry *)
6314 elf_link_hash_lookup (&(htab)->root, sym_name, true, true, true);
6315 stub_entry
6316 = elf32_arm_create_stub (htab, arm_stub_cmse_branch_thumb_only,
6317 NULL, NULL, bfd_abs_section_ptr, hash,
6318 sym_name, veneer_value,
6319 ST_BRANCH_TO_THUMB, &new_stub);
6320 if (stub_entry == NULL)
6321 ret = false;
6322 else
6323 {
6324 BFD_ASSERT (new_stub);
6325 new_cmse_stubs_created++;
6326 (*cmse_stub_created)++;
6327 }
6328 stub_entry->stub_template_size = stub_entry->stub_size = 0;
6329 stub_entry->stub_offset = stub_offset;
6330 }
6331 /* Symbol found is not callable from non secure code. */
6332 else if (!stub_entry)
6333 {
6334 if (!cmse_entry_fct_p (hash))
6335 {
6336 _bfd_error_handler (_("`%s' refers to a non entry function"),
6337 sym_name);
6338 ret = false;
6339 }
6340 continue;
6341 }
6342 else
6343 {
6344 /* Only stubs for SG veneers should have been created. */
6345 BFD_ASSERT (stub_entry->stub_type == arm_stub_cmse_branch_thumb_only);
6346
6347 /* Check visibility hasn't changed. */
6348 if (!!(flags & BSF_GLOBAL)
6349 != (hash->root.root.type == bfd_link_hash_defined))
6350 _bfd_error_handler
6351 (_("%pB: visibility of symbol `%s' has changed"), in_implib_bfd,
6352 sym_name);
6353
6354 stub_entry->stub_offset = stub_offset;
6355 }
6356
6357 /* Size should match that of a SG veneer. */
6358 if (intsym->st_size != cmse_stub_size)
6359 {
6360 _bfd_error_handler (_("%pB: incorrect size for symbol `%s'"),
6361 in_implib_bfd, sym_name);
6362 ret = false;
6363 }
6364
6365 /* Previous veneer address is before current SG veneer section. */
6366 if (veneer_value < cmse_stub_sec_vma)
6367 {
6368 /* Avoid offset underflow. */
6369 if (stub_entry)
6370 stub_entry->stub_offset = 0;
6371 stub_offset = 0;
6372 ret = false;
6373 }
6374
6375 /* Complain if stub offset not a multiple of stub size. */
6376 if (stub_offset % cmse_stub_size)
6377 {
6378 _bfd_error_handler
6379 (_("offset of veneer for entry function `%s' not a multiple of "
6380 "its size"), sym_name);
6381 ret = false;
6382 }
6383
6384 if (!ret)
6385 continue;
6386
6387 new_cmse_stubs_created--;
6388 if (veneer_value < cmse_stub_array_start)
6389 cmse_stub_array_start = veneer_value;
6390 next_cmse_stub_offset = stub_offset + ((cmse_stub_size + 7) & ~7);
6391 if (next_cmse_stub_offset > htab->new_cmse_stub_offset)
6392 htab->new_cmse_stub_offset = next_cmse_stub_offset;
6393 }
6394
6395 if (!info->out_implib_bfd && new_cmse_stubs_created != 0)
6396 {
6397 BFD_ASSERT (new_cmse_stubs_created > 0);
6398 _bfd_error_handler
6399 (_("new entry function(s) introduced but no output import library "
6400 "specified:"));
6401 bfd_hash_traverse (&htab->stub_hash_table, arm_list_new_cmse_stub, info);
6402 }
6403
6404 if (cmse_stub_array_start != cmse_stub_sec_vma)
6405 {
6406 _bfd_error_handler
6407 (_("start address of `%s' is different from previous link"),
6408 out_sec_name);
6409 ret = false;
6410 }
6411
6412 free_sym_buf:
6413 free (sympp);
6414 return ret;
6415 }
6416
6417 /* Determine and set the size of the stub section for a final link.
6418
6419 The basic idea here is to examine all the relocations looking for
6420 PC-relative calls to a target that is unreachable with a "bl"
6421 instruction. */
6422
6423 bool
6424 elf32_arm_size_stubs (bfd *output_bfd,
6425 bfd *stub_bfd,
6426 struct bfd_link_info *info,
6427 bfd_signed_vma group_size,
6428 asection * (*add_stub_section) (const char *, asection *,
6429 asection *,
6430 unsigned int),
6431 void (*layout_sections_again) (void))
6432 {
6433 bool ret = true;
6434 obj_attribute *out_attr;
6435 int cmse_stub_created = 0;
6436 bfd_size_type stub_group_size;
6437 bool m_profile, stubs_always_after_branch, first_veneer_scan = true;
6438 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
6439 struct a8_erratum_fix *a8_fixes = NULL;
6440 unsigned int num_a8_fixes = 0, a8_fix_table_size = 10;
6441 struct a8_erratum_reloc *a8_relocs = NULL;
6442 unsigned int num_a8_relocs = 0, a8_reloc_table_size = 10, i;
6443
6444 if (htab == NULL)
6445 return false;
6446
6447 if (htab->fix_cortex_a8)
6448 {
6449 a8_fixes = (struct a8_erratum_fix *)
6450 bfd_zmalloc (sizeof (struct a8_erratum_fix) * a8_fix_table_size);
6451 a8_relocs = (struct a8_erratum_reloc *)
6452 bfd_zmalloc (sizeof (struct a8_erratum_reloc) * a8_reloc_table_size);
6453 }
6454
6455 /* Propagate mach to stub bfd, because it may not have been
6456 finalized when we created stub_bfd. */
6457 bfd_set_arch_mach (stub_bfd, bfd_get_arch (output_bfd),
6458 bfd_get_mach (output_bfd));
6459
6460 /* Stash our params away. */
6461 htab->stub_bfd = stub_bfd;
6462 htab->add_stub_section = add_stub_section;
6463 htab->layout_sections_again = layout_sections_again;
6464 stubs_always_after_branch = group_size < 0;
6465
6466 out_attr = elf_known_obj_attributes_proc (output_bfd);
6467 m_profile = out_attr[Tag_CPU_arch_profile].i == 'M';
6468
6469 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6470 as the first half of a 32-bit branch straddling two 4K pages. This is a
6471 crude way of enforcing that. */
6472 if (htab->fix_cortex_a8)
6473 stubs_always_after_branch = 1;
6474
6475 if (group_size < 0)
6476 stub_group_size = -group_size;
6477 else
6478 stub_group_size = group_size;
6479
6480 if (stub_group_size == 1)
6481 {
6482 /* Default values. */
6483 /* Thumb branch range is +-4MB has to be used as the default
6484 maximum size (a given section can contain both ARM and Thumb
6485 code, so the worst case has to be taken into account).
6486
6487 This value is 24K less than that, which allows for 2025
6488 12-byte stubs. If we exceed that, then we will fail to link.
6489 The user will have to relink with an explicit group size
6490 option. */
6491 stub_group_size = 4170000;
6492 }
6493
6494 group_sections (htab, stub_group_size, stubs_always_after_branch);
6495
6496 /* If we're applying the cortex A8 fix, we need to determine the
6497 program header size now, because we cannot change it later --
6498 that could alter section placements. Notice the A8 erratum fix
6499 ends up requiring the section addresses to remain unchanged
6500 modulo the page size. That's something we cannot represent
6501 inside BFD, and we don't want to force the section alignment to
6502 be the page size. */
6503 if (htab->fix_cortex_a8)
6504 (*htab->layout_sections_again) ();
6505
6506 while (1)
6507 {
6508 bfd *input_bfd;
6509 unsigned int bfd_indx;
6510 asection *stub_sec;
6511 enum elf32_arm_stub_type stub_type;
6512 bool stub_changed = false;
6513 unsigned prev_num_a8_fixes = num_a8_fixes;
6514
6515 num_a8_fixes = 0;
6516 for (input_bfd = info->input_bfds, bfd_indx = 0;
6517 input_bfd != NULL;
6518 input_bfd = input_bfd->link.next, bfd_indx++)
6519 {
6520 Elf_Internal_Shdr *symtab_hdr;
6521 asection *section;
6522 Elf_Internal_Sym *local_syms = NULL;
6523
6524 if (!is_arm_elf (input_bfd))
6525 continue;
6526 if ((input_bfd->flags & DYNAMIC) != 0
6527 && (elf_sym_hashes (input_bfd) == NULL
6528 || (elf_dyn_lib_class (input_bfd) & DYN_AS_NEEDED) != 0))
6529 continue;
6530
6531 num_a8_relocs = 0;
6532
6533 /* We'll need the symbol table in a second. */
6534 symtab_hdr = &elf_tdata (input_bfd)->symtab_hdr;
6535 if (symtab_hdr->sh_info == 0)
6536 continue;
6537
6538 /* Limit scan of symbols to object file whose profile is
6539 Microcontroller to not hinder performance in the general case. */
6540 if (m_profile && first_veneer_scan)
6541 {
6542 struct elf_link_hash_entry **sym_hashes;
6543
6544 sym_hashes = elf_sym_hashes (input_bfd);
6545 if (!cmse_scan (input_bfd, htab, out_attr, sym_hashes,
6546 &cmse_stub_created))
6547 goto error_ret_free_local;
6548
6549 if (cmse_stub_created != 0)
6550 stub_changed = true;
6551 }
6552
6553 /* Walk over each section attached to the input bfd. */
6554 for (section = input_bfd->sections;
6555 section != NULL;
6556 section = section->next)
6557 {
6558 Elf_Internal_Rela *internal_relocs, *irelaend, *irela;
6559
6560 /* If there aren't any relocs, then there's nothing more
6561 to do. */
6562 if ((section->flags & SEC_RELOC) == 0
6563 || section->reloc_count == 0
6564 || (section->flags & SEC_CODE) == 0)
6565 continue;
6566
6567 /* If this section is a link-once section that will be
6568 discarded, then don't create any stubs. */
6569 if (section->output_section == NULL
6570 || section->output_section->owner != output_bfd)
6571 continue;
6572
6573 /* Get the relocs. */
6574 internal_relocs
6575 = _bfd_elf_link_read_relocs (input_bfd, section, NULL,
6576 NULL, info->keep_memory);
6577 if (internal_relocs == NULL)
6578 goto error_ret_free_local;
6579
6580 /* Now examine each relocation. */
6581 irela = internal_relocs;
6582 irelaend = irela + section->reloc_count;
6583 for (; irela < irelaend; irela++)
6584 {
6585 unsigned int r_type, r_indx;
6586 asection *sym_sec;
6587 bfd_vma sym_value;
6588 bfd_vma destination;
6589 struct elf32_arm_link_hash_entry *hash;
6590 const char *sym_name;
6591 unsigned char st_type;
6592 enum arm_st_branch_type branch_type;
6593 bool created_stub = false;
6594
6595 r_type = ELF32_R_TYPE (irela->r_info);
6596 r_indx = ELF32_R_SYM (irela->r_info);
6597
6598 if (r_type >= (unsigned int) R_ARM_max)
6599 {
6600 bfd_set_error (bfd_error_bad_value);
6601 error_ret_free_internal:
6602 if (elf_section_data (section)->relocs == NULL)
6603 free (internal_relocs);
6604 /* Fall through. */
6605 error_ret_free_local:
6606 if (symtab_hdr->contents != (unsigned char *) local_syms)
6607 free (local_syms);
6608 return false;
6609 }
6610
6611 hash = NULL;
6612 if (r_indx >= symtab_hdr->sh_info)
6613 hash = elf32_arm_hash_entry
6614 (elf_sym_hashes (input_bfd)
6615 [r_indx - symtab_hdr->sh_info]);
6616
6617 /* Only look for stubs on branch instructions, or
6618 non-relaxed TLSCALL */
6619 if ((r_type != (unsigned int) R_ARM_CALL)
6620 && (r_type != (unsigned int) R_ARM_THM_CALL)
6621 && (r_type != (unsigned int) R_ARM_JUMP24)
6622 && (r_type != (unsigned int) R_ARM_THM_JUMP19)
6623 && (r_type != (unsigned int) R_ARM_THM_XPC22)
6624 && (r_type != (unsigned int) R_ARM_THM_JUMP24)
6625 && (r_type != (unsigned int) R_ARM_PLT32)
6626 && !((r_type == (unsigned int) R_ARM_TLS_CALL
6627 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6628 && r_type == (elf32_arm_tls_transition
6629 (info, r_type,
6630 (struct elf_link_hash_entry *) hash))
6631 && ((hash ? hash->tls_type
6632 : (elf32_arm_local_got_tls_type
6633 (input_bfd)[r_indx]))
6634 & GOT_TLS_GDESC) != 0))
6635 continue;
6636
6637 /* Now determine the call target, its name, value,
6638 section. */
6639 sym_sec = NULL;
6640 sym_value = 0;
6641 destination = 0;
6642 sym_name = NULL;
6643
6644 if (r_type == (unsigned int) R_ARM_TLS_CALL
6645 || r_type == (unsigned int) R_ARM_THM_TLS_CALL)
6646 {
6647 /* A non-relaxed TLS call. The target is the
6648 plt-resident trampoline and nothing to do
6649 with the symbol. */
6650 BFD_ASSERT (htab->tls_trampoline > 0);
6651 sym_sec = htab->root.splt;
6652 sym_value = htab->tls_trampoline;
6653 hash = 0;
6654 st_type = STT_FUNC;
6655 branch_type = ST_BRANCH_TO_ARM;
6656 }
6657 else if (!hash)
6658 {
6659 /* It's a local symbol. */
6660 Elf_Internal_Sym *sym;
6661
6662 if (local_syms == NULL)
6663 {
6664 local_syms
6665 = (Elf_Internal_Sym *) symtab_hdr->contents;
6666 if (local_syms == NULL)
6667 local_syms
6668 = bfd_elf_get_elf_syms (input_bfd, symtab_hdr,
6669 symtab_hdr->sh_info, 0,
6670 NULL, NULL, NULL);
6671 if (local_syms == NULL)
6672 goto error_ret_free_internal;
6673 }
6674
6675 sym = local_syms + r_indx;
6676 if (sym->st_shndx == SHN_UNDEF)
6677 sym_sec = bfd_und_section_ptr;
6678 else if (sym->st_shndx == SHN_ABS)
6679 sym_sec = bfd_abs_section_ptr;
6680 else if (sym->st_shndx == SHN_COMMON)
6681 sym_sec = bfd_com_section_ptr;
6682 else
6683 sym_sec =
6684 bfd_section_from_elf_index (input_bfd, sym->st_shndx);
6685
6686 if (!sym_sec)
6687 /* This is an undefined symbol. It can never
6688 be resolved. */
6689 continue;
6690
6691 if (ELF_ST_TYPE (sym->st_info) != STT_SECTION)
6692 sym_value = sym->st_value;
6693 destination = (sym_value + irela->r_addend
6694 + sym_sec->output_offset
6695 + sym_sec->output_section->vma);
6696 st_type = ELF_ST_TYPE (sym->st_info);
6697 branch_type =
6698 ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
6699 sym_name
6700 = bfd_elf_string_from_elf_section (input_bfd,
6701 symtab_hdr->sh_link,
6702 sym->st_name);
6703 }
6704 else
6705 {
6706 /* It's an external symbol. */
6707 while (hash->root.root.type == bfd_link_hash_indirect
6708 || hash->root.root.type == bfd_link_hash_warning)
6709 hash = ((struct elf32_arm_link_hash_entry *)
6710 hash->root.root.u.i.link);
6711
6712 if (hash->root.root.type == bfd_link_hash_defined
6713 || hash->root.root.type == bfd_link_hash_defweak)
6714 {
6715 sym_sec = hash->root.root.u.def.section;
6716 sym_value = hash->root.root.u.def.value;
6717
6718 struct elf32_arm_link_hash_table *globals =
6719 elf32_arm_hash_table (info);
6720
6721 /* For a destination in a shared library,
6722 use the PLT stub as target address to
6723 decide whether a branch stub is
6724 needed. */
6725 if (globals != NULL
6726 && globals->root.splt != NULL
6727 && hash != NULL
6728 && hash->root.plt.offset != (bfd_vma) -1)
6729 {
6730 sym_sec = globals->root.splt;
6731 sym_value = hash->root.plt.offset;
6732 if (sym_sec->output_section != NULL)
6733 destination = (sym_value
6734 + sym_sec->output_offset
6735 + sym_sec->output_section->vma);
6736 }
6737 else if (sym_sec->output_section != NULL)
6738 destination = (sym_value + irela->r_addend
6739 + sym_sec->output_offset
6740 + sym_sec->output_section->vma);
6741 }
6742 else if ((hash->root.root.type == bfd_link_hash_undefined)
6743 || (hash->root.root.type == bfd_link_hash_undefweak))
6744 {
6745 /* For a shared library, use the PLT stub as
6746 target address to decide whether a long
6747 branch stub is needed.
6748 For absolute code, they cannot be handled. */
6749 struct elf32_arm_link_hash_table *globals =
6750 elf32_arm_hash_table (info);
6751
6752 if (globals != NULL
6753 && globals->root.splt != NULL
6754 && hash != NULL
6755 && hash->root.plt.offset != (bfd_vma) -1)
6756 {
6757 sym_sec = globals->root.splt;
6758 sym_value = hash->root.plt.offset;
6759 if (sym_sec->output_section != NULL)
6760 destination = (sym_value
6761 + sym_sec->output_offset
6762 + sym_sec->output_section->vma);
6763 }
6764 else
6765 continue;
6766 }
6767 else
6768 {
6769 bfd_set_error (bfd_error_bad_value);
6770 goto error_ret_free_internal;
6771 }
6772 st_type = hash->root.type;
6773 branch_type =
6774 ARM_GET_SYM_BRANCH_TYPE (hash->root.target_internal);
6775 sym_name = hash->root.root.root.string;
6776 }
6777
6778 do
6779 {
6780 bool new_stub;
6781 struct elf32_arm_stub_hash_entry *stub_entry;
6782
6783 /* Determine what (if any) linker stub is needed. */
6784 stub_type = arm_type_of_stub (info, section, irela,
6785 st_type, &branch_type,
6786 hash, destination, sym_sec,
6787 input_bfd, sym_name);
6788 if (stub_type == arm_stub_none)
6789 break;
6790
6791 /* We've either created a stub for this reloc already,
6792 or we are about to. */
6793 stub_entry =
6794 elf32_arm_create_stub (htab, stub_type, section, irela,
6795 sym_sec, hash,
6796 (char *) sym_name, sym_value,
6797 branch_type, &new_stub);
6798
6799 created_stub = stub_entry != NULL;
6800 if (!created_stub)
6801 goto error_ret_free_internal;
6802 else if (!new_stub)
6803 break;
6804 else
6805 stub_changed = true;
6806 }
6807 while (0);
6808
6809 /* Look for relocations which might trigger Cortex-A8
6810 erratum. */
6811 if (htab->fix_cortex_a8
6812 && (r_type == (unsigned int) R_ARM_THM_JUMP24
6813 || r_type == (unsigned int) R_ARM_THM_JUMP19
6814 || r_type == (unsigned int) R_ARM_THM_CALL
6815 || r_type == (unsigned int) R_ARM_THM_XPC22))
6816 {
6817 bfd_vma from = section->output_section->vma
6818 + section->output_offset
6819 + irela->r_offset;
6820
6821 if ((from & 0xfff) == 0xffe)
6822 {
6823 /* Found a candidate. Note we haven't checked the
6824 destination is within 4K here: if we do so (and
6825 don't create an entry in a8_relocs) we can't tell
6826 that a branch should have been relocated when
6827 scanning later. */
6828 if (num_a8_relocs == a8_reloc_table_size)
6829 {
6830 a8_reloc_table_size *= 2;
6831 a8_relocs = (struct a8_erratum_reloc *)
6832 bfd_realloc (a8_relocs,
6833 sizeof (struct a8_erratum_reloc)
6834 * a8_reloc_table_size);
6835 }
6836
6837 a8_relocs[num_a8_relocs].from = from;
6838 a8_relocs[num_a8_relocs].destination = destination;
6839 a8_relocs[num_a8_relocs].r_type = r_type;
6840 a8_relocs[num_a8_relocs].branch_type = branch_type;
6841 a8_relocs[num_a8_relocs].sym_name = sym_name;
6842 a8_relocs[num_a8_relocs].non_a8_stub = created_stub;
6843 a8_relocs[num_a8_relocs].hash = hash;
6844
6845 num_a8_relocs++;
6846 }
6847 }
6848 }
6849
6850 /* We're done with the internal relocs, free them. */
6851 if (elf_section_data (section)->relocs == NULL)
6852 free (internal_relocs);
6853 }
6854
6855 if (htab->fix_cortex_a8)
6856 {
6857 /* Sort relocs which might apply to Cortex-A8 erratum. */
6858 qsort (a8_relocs, num_a8_relocs,
6859 sizeof (struct a8_erratum_reloc),
6860 &a8_reloc_compare);
6861
6862 /* Scan for branches which might trigger Cortex-A8 erratum. */
6863 if (cortex_a8_erratum_scan (input_bfd, info, &a8_fixes,
6864 &num_a8_fixes, &a8_fix_table_size,
6865 a8_relocs, num_a8_relocs,
6866 prev_num_a8_fixes, &stub_changed)
6867 != 0)
6868 goto error_ret_free_local;
6869 }
6870
6871 if (local_syms != NULL
6872 && symtab_hdr->contents != (unsigned char *) local_syms)
6873 {
6874 if (!info->keep_memory)
6875 free (local_syms);
6876 else
6877 symtab_hdr->contents = (unsigned char *) local_syms;
6878 }
6879 }
6880
6881 if (first_veneer_scan
6882 && !set_cmse_veneer_addr_from_implib (info, htab,
6883 &cmse_stub_created))
6884 ret = false;
6885
6886 if (prev_num_a8_fixes != num_a8_fixes)
6887 stub_changed = true;
6888
6889 if (!stub_changed)
6890 break;
6891
6892 /* OK, we've added some stubs. Find out the new size of the
6893 stub sections. */
6894 for (stub_sec = htab->stub_bfd->sections;
6895 stub_sec != NULL;
6896 stub_sec = stub_sec->next)
6897 {
6898 /* Ignore non-stub sections. */
6899 if (!strstr (stub_sec->name, STUB_SUFFIX))
6900 continue;
6901
6902 stub_sec->size = 0;
6903 }
6904
6905 /* Add new SG veneers after those already in the input import
6906 library. */
6907 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6908 stub_type++)
6909 {
6910 bfd_vma *start_offset_p;
6911 asection **stub_sec_p;
6912
6913 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
6914 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6915 if (start_offset_p == NULL)
6916 continue;
6917
6918 BFD_ASSERT (stub_sec_p != NULL);
6919 if (*stub_sec_p != NULL)
6920 (*stub_sec_p)->size = *start_offset_p;
6921 }
6922
6923 /* Compute stub section size, considering padding. */
6924 bfd_hash_traverse (&htab->stub_hash_table, arm_size_one_stub, htab);
6925 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type;
6926 stub_type++)
6927 {
6928 int size, padding;
6929 asection **stub_sec_p;
6930
6931 padding = arm_dedicated_stub_section_padding (stub_type);
6932 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
6933 /* Skip if no stub input section or no stub section padding
6934 required. */
6935 if ((stub_sec_p != NULL && *stub_sec_p == NULL) || padding == 0)
6936 continue;
6937 /* Stub section padding required but no dedicated section. */
6938 BFD_ASSERT (stub_sec_p);
6939
6940 size = (*stub_sec_p)->size;
6941 size = (size + padding - 1) & ~(padding - 1);
6942 (*stub_sec_p)->size = size;
6943 }
6944
6945 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6946 if (htab->fix_cortex_a8)
6947 for (i = 0; i < num_a8_fixes; i++)
6948 {
6949 stub_sec = elf32_arm_create_or_find_stub_sec (NULL,
6950 a8_fixes[i].section, htab, a8_fixes[i].stub_type);
6951
6952 if (stub_sec == NULL)
6953 return false;
6954
6955 stub_sec->size
6956 += find_stub_size_and_template (a8_fixes[i].stub_type, NULL,
6957 NULL);
6958 }
6959
6960
6961 /* Ask the linker to do its stuff. */
6962 (*htab->layout_sections_again) ();
6963 first_veneer_scan = false;
6964 }
6965
6966 /* Add stubs for Cortex-A8 erratum fixes now. */
6967 if (htab->fix_cortex_a8)
6968 {
6969 for (i = 0; i < num_a8_fixes; i++)
6970 {
6971 struct elf32_arm_stub_hash_entry *stub_entry;
6972 char *stub_name = a8_fixes[i].stub_name;
6973 asection *section = a8_fixes[i].section;
6974 unsigned int section_id = a8_fixes[i].section->id;
6975 asection *link_sec = htab->stub_group[section_id].link_sec;
6976 asection *stub_sec = htab->stub_group[section_id].stub_sec;
6977 const insn_sequence *template_sequence;
6978 int template_size, size = 0;
6979
6980 stub_entry = arm_stub_hash_lookup (&htab->stub_hash_table, stub_name,
6981 true, false);
6982 if (stub_entry == NULL)
6983 {
6984 _bfd_error_handler (_("%pB: cannot create stub entry %s"),
6985 section->owner, stub_name);
6986 return false;
6987 }
6988
6989 stub_entry->stub_sec = stub_sec;
6990 stub_entry->stub_offset = (bfd_vma) -1;
6991 stub_entry->id_sec = link_sec;
6992 stub_entry->stub_type = a8_fixes[i].stub_type;
6993 stub_entry->source_value = a8_fixes[i].offset;
6994 stub_entry->target_section = a8_fixes[i].section;
6995 stub_entry->target_value = a8_fixes[i].target_offset;
6996 stub_entry->orig_insn = a8_fixes[i].orig_insn;
6997 stub_entry->branch_type = a8_fixes[i].branch_type;
6998
6999 size = find_stub_size_and_template (a8_fixes[i].stub_type,
7000 &template_sequence,
7001 &template_size);
7002
7003 stub_entry->stub_size = size;
7004 stub_entry->stub_template = template_sequence;
7005 stub_entry->stub_template_size = template_size;
7006 }
7007
7008 /* Stash the Cortex-A8 erratum fix array for use later in
7009 elf32_arm_write_section(). */
7010 htab->a8_erratum_fixes = a8_fixes;
7011 htab->num_a8_erratum_fixes = num_a8_fixes;
7012 }
7013 else
7014 {
7015 htab->a8_erratum_fixes = NULL;
7016 htab->num_a8_erratum_fixes = 0;
7017 }
7018 return ret;
7019 }
7020
7021 /* Build all the stubs associated with the current output file. The
7022 stubs are kept in a hash table attached to the main linker hash
7023 table. We also set up the .plt entries for statically linked PIC
7024 functions here. This function is called via arm_elf_finish in the
7025 linker. */
7026
7027 bool
7028 elf32_arm_build_stubs (struct bfd_link_info *info)
7029 {
7030 asection *stub_sec;
7031 struct bfd_hash_table *table;
7032 enum elf32_arm_stub_type stub_type;
7033 struct elf32_arm_link_hash_table *htab;
7034
7035 htab = elf32_arm_hash_table (info);
7036 if (htab == NULL)
7037 return false;
7038
7039 for (stub_sec = htab->stub_bfd->sections;
7040 stub_sec != NULL;
7041 stub_sec = stub_sec->next)
7042 {
7043 bfd_size_type size;
7044
7045 /* Ignore non-stub sections. */
7046 if (!strstr (stub_sec->name, STUB_SUFFIX))
7047 continue;
7048
7049 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
7050 must at least be done for stub section requiring padding and for SG
7051 veneers to ensure that a non secure code branching to a removed SG
7052 veneer causes an error. */
7053 size = stub_sec->size;
7054 stub_sec->contents = (unsigned char *) bfd_zalloc (htab->stub_bfd, size);
7055 if (stub_sec->contents == NULL && size != 0)
7056 return false;
7057
7058 stub_sec->size = 0;
7059 }
7060
7061 /* Add new SG veneers after those already in the input import library. */
7062 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7063 {
7064 bfd_vma *start_offset_p;
7065 asection **stub_sec_p;
7066
7067 start_offset_p = arm_new_stubs_start_offset_ptr (htab, stub_type);
7068 stub_sec_p = arm_dedicated_stub_input_section_ptr (htab, stub_type);
7069 if (start_offset_p == NULL)
7070 continue;
7071
7072 BFD_ASSERT (stub_sec_p != NULL);
7073 if (*stub_sec_p != NULL)
7074 (*stub_sec_p)->size = *start_offset_p;
7075 }
7076
7077 /* Build the stubs as directed by the stub hash table. */
7078 table = &htab->stub_hash_table;
7079 bfd_hash_traverse (table, arm_build_one_stub, info);
7080 if (htab->fix_cortex_a8)
7081 {
7082 /* Place the cortex a8 stubs last. */
7083 htab->fix_cortex_a8 = -1;
7084 bfd_hash_traverse (table, arm_build_one_stub, info);
7085 }
7086
7087 return true;
7088 }
7089
7090 /* Locate the Thumb encoded calling stub for NAME. */
7091
7092 static struct elf_link_hash_entry *
7093 find_thumb_glue (struct bfd_link_info *link_info,
7094 const char *name,
7095 char **error_message)
7096 {
7097 char *tmp_name;
7098 struct elf_link_hash_entry *hash;
7099 struct elf32_arm_link_hash_table *hash_table;
7100
7101 /* We need a pointer to the armelf specific hash table. */
7102 hash_table = elf32_arm_hash_table (link_info);
7103 if (hash_table == NULL)
7104 return NULL;
7105
7106 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
7107 + strlen (THUMB2ARM_GLUE_ENTRY_NAME) + 1);
7108
7109 BFD_ASSERT (tmp_name);
7110
7111 sprintf (tmp_name, THUMB2ARM_GLUE_ENTRY_NAME, name);
7112
7113 hash = elf_link_hash_lookup
7114 (&(hash_table)->root, tmp_name, false, false, true);
7115
7116 if (hash == NULL
7117 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7118 "Thumb", tmp_name, name) == -1)
7119 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
7120
7121 free (tmp_name);
7122
7123 return hash;
7124 }
7125
7126 /* Locate the ARM encoded calling stub for NAME. */
7127
7128 static struct elf_link_hash_entry *
7129 find_arm_glue (struct bfd_link_info *link_info,
7130 const char *name,
7131 char **error_message)
7132 {
7133 char *tmp_name;
7134 struct elf_link_hash_entry *myh;
7135 struct elf32_arm_link_hash_table *hash_table;
7136
7137 /* We need a pointer to the elfarm specific hash table. */
7138 hash_table = elf32_arm_hash_table (link_info);
7139 if (hash_table == NULL)
7140 return NULL;
7141
7142 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
7143 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
7144 BFD_ASSERT (tmp_name);
7145
7146 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7147
7148 myh = elf_link_hash_lookup
7149 (&(hash_table)->root, tmp_name, false, false, true);
7150
7151 if (myh == NULL
7152 && asprintf (error_message, _("unable to find %s glue '%s' for '%s'"),
7153 "ARM", tmp_name, name) == -1)
7154 *error_message = (char *) bfd_errmsg (bfd_error_system_call);
7155
7156 free (tmp_name);
7157
7158 return myh;
7159 }
7160
7161 /* ARM->Thumb glue (static images):
7162
7163 .arm
7164 __func_from_arm:
7165 ldr r12, __func_addr
7166 bx r12
7167 __func_addr:
7168 .word func @ behave as if you saw a ARM_32 reloc.
7169
7170 (v5t static images)
7171 .arm
7172 __func_from_arm:
7173 ldr pc, __func_addr
7174 __func_addr:
7175 .word func @ behave as if you saw a ARM_32 reloc.
7176
7177 (relocatable images)
7178 .arm
7179 __func_from_arm:
7180 ldr r12, __func_offset
7181 add r12, r12, pc
7182 bx r12
7183 __func_offset:
7184 .word func - . */
7185
7186 #define ARM2THUMB_STATIC_GLUE_SIZE 12
7187 static const insn32 a2t1_ldr_insn = 0xe59fc000;
7188 static const insn32 a2t2_bx_r12_insn = 0xe12fff1c;
7189 static const insn32 a2t3_func_addr_insn = 0x00000001;
7190
7191 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7192 static const insn32 a2t1v5_ldr_insn = 0xe51ff004;
7193 static const insn32 a2t2v5_func_addr_insn = 0x00000001;
7194
7195 #define ARM2THUMB_PIC_GLUE_SIZE 16
7196 static const insn32 a2t1p_ldr_insn = 0xe59fc004;
7197 static const insn32 a2t2p_add_pc_insn = 0xe08cc00f;
7198 static const insn32 a2t3p_bx_r12_insn = 0xe12fff1c;
7199
7200 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
7201
7202 .thumb .thumb
7203 .align 2 .align 2
7204 __func_from_thumb: __func_from_thumb:
7205 bx pc push {r6, lr}
7206 nop ldr r6, __func_addr
7207 .arm mov lr, pc
7208 b func bx r6
7209 .arm
7210 ;; back_to_thumb
7211 ldmia r13! {r6, lr}
7212 bx lr
7213 __func_addr:
7214 .word func */
7215
7216 #define THUMB2ARM_GLUE_SIZE 8
7217 static const insn16 t2a1_bx_pc_insn = 0x4778;
7218 static const insn16 t2a2_noop_insn = 0x46c0;
7219 static const insn32 t2a3_b_insn = 0xea000000;
7220
7221 #define VFP11_ERRATUM_VENEER_SIZE 8
7222 #define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7223 #define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
7224
7225 #define ARM_BX_VENEER_SIZE 12
7226 static const insn32 armbx1_tst_insn = 0xe3100001;
7227 static const insn32 armbx2_moveq_insn = 0x01a0f000;
7228 static const insn32 armbx3_bx_insn = 0xe12fff10;
7229
7230 #ifndef ELFARM_NABI_C_INCLUDED
7231 static void
7232 arm_allocate_glue_section_space (bfd * abfd, bfd_size_type size, const char * name)
7233 {
7234 asection * s;
7235 bfd_byte * contents;
7236
7237 if (size == 0)
7238 {
7239 /* Do not include empty glue sections in the output. */
7240 if (abfd != NULL)
7241 {
7242 s = bfd_get_linker_section (abfd, name);
7243 if (s != NULL)
7244 s->flags |= SEC_EXCLUDE;
7245 }
7246 return;
7247 }
7248
7249 BFD_ASSERT (abfd != NULL);
7250
7251 s = bfd_get_linker_section (abfd, name);
7252 BFD_ASSERT (s != NULL);
7253
7254 contents = (bfd_byte *) bfd_zalloc (abfd, size);
7255
7256 BFD_ASSERT (s->size == size);
7257 s->contents = contents;
7258 }
7259
7260 bool
7261 bfd_elf32_arm_allocate_interworking_sections (struct bfd_link_info * info)
7262 {
7263 struct elf32_arm_link_hash_table * globals;
7264
7265 globals = elf32_arm_hash_table (info);
7266 BFD_ASSERT (globals != NULL);
7267
7268 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7269 globals->arm_glue_size,
7270 ARM2THUMB_GLUE_SECTION_NAME);
7271
7272 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7273 globals->thumb_glue_size,
7274 THUMB2ARM_GLUE_SECTION_NAME);
7275
7276 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7277 globals->vfp11_erratum_glue_size,
7278 VFP11_ERRATUM_VENEER_SECTION_NAME);
7279
7280 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7281 globals->stm32l4xx_erratum_glue_size,
7282 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7283
7284 arm_allocate_glue_section_space (globals->bfd_of_glue_owner,
7285 globals->bx_glue_size,
7286 ARM_BX_GLUE_SECTION_NAME);
7287
7288 return true;
7289 }
7290
7291 /* Allocate space and symbols for calling a Thumb function from Arm mode.
7292 returns the symbol identifying the stub. */
7293
7294 static struct elf_link_hash_entry *
7295 record_arm_to_thumb_glue (struct bfd_link_info * link_info,
7296 struct elf_link_hash_entry * h)
7297 {
7298 const char * name = h->root.root.string;
7299 asection * s;
7300 char * tmp_name;
7301 struct elf_link_hash_entry * myh;
7302 struct bfd_link_hash_entry * bh;
7303 struct elf32_arm_link_hash_table * globals;
7304 bfd_vma val;
7305 bfd_size_type size;
7306
7307 globals = elf32_arm_hash_table (link_info);
7308 BFD_ASSERT (globals != NULL);
7309 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7310
7311 s = bfd_get_linker_section
7312 (globals->bfd_of_glue_owner, ARM2THUMB_GLUE_SECTION_NAME);
7313
7314 BFD_ASSERT (s != NULL);
7315
7316 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen (name)
7317 + strlen (ARM2THUMB_GLUE_ENTRY_NAME) + 1);
7318 BFD_ASSERT (tmp_name);
7319
7320 sprintf (tmp_name, ARM2THUMB_GLUE_ENTRY_NAME, name);
7321
7322 myh = elf_link_hash_lookup
7323 (&(globals)->root, tmp_name, false, false, true);
7324
7325 if (myh != NULL)
7326 {
7327 /* We've already seen this guy. */
7328 free (tmp_name);
7329 return myh;
7330 }
7331
7332 /* The only trick here is using hash_table->arm_glue_size as the value.
7333 Even though the section isn't allocated yet, this is where we will be
7334 putting it. The +1 on the value marks that the stub has not been
7335 output yet - not that it is a Thumb function. */
7336 bh = NULL;
7337 val = globals->arm_glue_size + 1;
7338 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7339 tmp_name, BSF_GLOBAL, s, val,
7340 NULL, true, false, &bh);
7341
7342 myh = (struct elf_link_hash_entry *) bh;
7343 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7344 myh->forced_local = 1;
7345
7346 free (tmp_name);
7347
7348 if (bfd_link_pic (link_info)
7349 || globals->root.is_relocatable_executable
7350 || globals->pic_veneer)
7351 size = ARM2THUMB_PIC_GLUE_SIZE;
7352 else if (globals->use_blx)
7353 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
7354 else
7355 size = ARM2THUMB_STATIC_GLUE_SIZE;
7356
7357 s->size += size;
7358 globals->arm_glue_size += size;
7359
7360 return myh;
7361 }
7362
7363 /* Allocate space for ARMv4 BX veneers. */
7364
7365 static void
7366 record_arm_bx_glue (struct bfd_link_info * link_info, int reg)
7367 {
7368 asection * s;
7369 struct elf32_arm_link_hash_table *globals;
7370 char *tmp_name;
7371 struct elf_link_hash_entry *myh;
7372 struct bfd_link_hash_entry *bh;
7373 bfd_vma val;
7374
7375 /* BX PC does not need a veneer. */
7376 if (reg == 15)
7377 return;
7378
7379 globals = elf32_arm_hash_table (link_info);
7380 BFD_ASSERT (globals != NULL);
7381 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
7382
7383 /* Check if this veneer has already been allocated. */
7384 if (globals->bx_glue_offset[reg])
7385 return;
7386
7387 s = bfd_get_linker_section
7388 (globals->bfd_of_glue_owner, ARM_BX_GLUE_SECTION_NAME);
7389
7390 BFD_ASSERT (s != NULL);
7391
7392 /* Add symbol for veneer. */
7393 tmp_name = (char *)
7394 bfd_malloc ((bfd_size_type) strlen (ARM_BX_GLUE_ENTRY_NAME) + 1);
7395 BFD_ASSERT (tmp_name);
7396
7397 sprintf (tmp_name, ARM_BX_GLUE_ENTRY_NAME, reg);
7398
7399 myh = elf_link_hash_lookup
7400 (&(globals)->root, tmp_name, false, false, false);
7401
7402 BFD_ASSERT (myh == NULL);
7403
7404 bh = NULL;
7405 val = globals->bx_glue_size;
7406 _bfd_generic_link_add_one_symbol (link_info, globals->bfd_of_glue_owner,
7407 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7408 NULL, true, false, &bh);
7409
7410 myh = (struct elf_link_hash_entry *) bh;
7411 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7412 myh->forced_local = 1;
7413
7414 s->size += ARM_BX_VENEER_SIZE;
7415 globals->bx_glue_offset[reg] = globals->bx_glue_size | 2;
7416 globals->bx_glue_size += ARM_BX_VENEER_SIZE;
7417 }
7418
7419
7420 /* Add an entry to the code/data map for section SEC. */
7421
7422 static void
7423 elf32_arm_section_map_add (asection *sec, char type, bfd_vma vma)
7424 {
7425 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
7426 unsigned int newidx;
7427
7428 if (sec_data->map == NULL)
7429 {
7430 sec_data->map = (elf32_arm_section_map *)
7431 bfd_malloc (sizeof (elf32_arm_section_map));
7432 sec_data->mapcount = 0;
7433 sec_data->mapsize = 1;
7434 }
7435
7436 newidx = sec_data->mapcount++;
7437
7438 if (sec_data->mapcount > sec_data->mapsize)
7439 {
7440 sec_data->mapsize *= 2;
7441 sec_data->map = (elf32_arm_section_map *)
7442 bfd_realloc_or_free (sec_data->map, sec_data->mapsize
7443 * sizeof (elf32_arm_section_map));
7444 }
7445
7446 if (sec_data->map)
7447 {
7448 sec_data->map[newidx].vma = vma;
7449 sec_data->map[newidx].type = type;
7450 }
7451 }
7452
7453
7454 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7455 veneers are handled for now. */
7456
7457 static bfd_vma
7458 record_vfp11_erratum_veneer (struct bfd_link_info *link_info,
7459 elf32_vfp11_erratum_list *branch,
7460 bfd *branch_bfd,
7461 asection *branch_sec,
7462 unsigned int offset)
7463 {
7464 asection *s;
7465 struct elf32_arm_link_hash_table *hash_table;
7466 char *tmp_name;
7467 struct elf_link_hash_entry *myh;
7468 struct bfd_link_hash_entry *bh;
7469 bfd_vma val;
7470 struct _arm_elf_section_data *sec_data;
7471 elf32_vfp11_erratum_list *newerr;
7472
7473 hash_table = elf32_arm_hash_table (link_info);
7474 BFD_ASSERT (hash_table != NULL);
7475 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7476
7477 s = bfd_get_linker_section
7478 (hash_table->bfd_of_glue_owner, VFP11_ERRATUM_VENEER_SECTION_NAME);
7479
7480 sec_data = elf32_arm_section_data (s);
7481
7482 BFD_ASSERT (s != NULL);
7483
7484 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7485 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
7486 BFD_ASSERT (tmp_name);
7487
7488 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
7489 hash_table->num_vfp11_fixes);
7490
7491 myh = elf_link_hash_lookup
7492 (&(hash_table)->root, tmp_name, false, false, false);
7493
7494 BFD_ASSERT (myh == NULL);
7495
7496 bh = NULL;
7497 val = hash_table->vfp11_erratum_glue_size;
7498 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7499 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7500 NULL, true, false, &bh);
7501
7502 myh = (struct elf_link_hash_entry *) bh;
7503 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7504 myh->forced_local = 1;
7505
7506 /* Link veneer back to calling location. */
7507 sec_data->erratumcount += 1;
7508 newerr = (elf32_vfp11_erratum_list *)
7509 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
7510
7511 newerr->type = VFP11_ERRATUM_ARM_VENEER;
7512 newerr->vma = -1;
7513 newerr->u.v.branch = branch;
7514 newerr->u.v.id = hash_table->num_vfp11_fixes;
7515 branch->u.b.veneer = newerr;
7516
7517 newerr->next = sec_data->erratumlist;
7518 sec_data->erratumlist = newerr;
7519
7520 /* A symbol for the return from the veneer. */
7521 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
7522 hash_table->num_vfp11_fixes);
7523
7524 myh = elf_link_hash_lookup
7525 (&(hash_table)->root, tmp_name, false, false, false);
7526
7527 if (myh != NULL)
7528 abort ();
7529
7530 bh = NULL;
7531 val = offset + 4;
7532 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7533 branch_sec, val, NULL, true, false, &bh);
7534
7535 myh = (struct elf_link_hash_entry *) bh;
7536 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7537 myh->forced_local = 1;
7538
7539 free (tmp_name);
7540
7541 /* Generate a mapping symbol for the veneer section, and explicitly add an
7542 entry for that symbol to the code/data map for the section. */
7543 if (hash_table->vfp11_erratum_glue_size == 0)
7544 {
7545 bh = NULL;
7546 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
7547 ever requires this erratum fix. */
7548 _bfd_generic_link_add_one_symbol (link_info,
7549 hash_table->bfd_of_glue_owner, "$a",
7550 BSF_LOCAL, s, 0, NULL,
7551 true, false, &bh);
7552
7553 myh = (struct elf_link_hash_entry *) bh;
7554 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7555 myh->forced_local = 1;
7556
7557 /* The elf32_arm_init_maps function only cares about symbols from input
7558 BFDs. We must make a note of this generated mapping symbol
7559 ourselves so that code byteswapping works properly in
7560 elf32_arm_write_section. */
7561 elf32_arm_section_map_add (s, 'a', 0);
7562 }
7563
7564 s->size += VFP11_ERRATUM_VENEER_SIZE;
7565 hash_table->vfp11_erratum_glue_size += VFP11_ERRATUM_VENEER_SIZE;
7566 hash_table->num_vfp11_fixes++;
7567
7568 /* The offset of the veneer. */
7569 return val;
7570 }
7571
7572 /* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7573 veneers need to be handled because used only in Cortex-M. */
7574
7575 static bfd_vma
7576 record_stm32l4xx_erratum_veneer (struct bfd_link_info *link_info,
7577 elf32_stm32l4xx_erratum_list *branch,
7578 bfd *branch_bfd,
7579 asection *branch_sec,
7580 unsigned int offset,
7581 bfd_size_type veneer_size)
7582 {
7583 asection *s;
7584 struct elf32_arm_link_hash_table *hash_table;
7585 char *tmp_name;
7586 struct elf_link_hash_entry *myh;
7587 struct bfd_link_hash_entry *bh;
7588 bfd_vma val;
7589 struct _arm_elf_section_data *sec_data;
7590 elf32_stm32l4xx_erratum_list *newerr;
7591
7592 hash_table = elf32_arm_hash_table (link_info);
7593 BFD_ASSERT (hash_table != NULL);
7594 BFD_ASSERT (hash_table->bfd_of_glue_owner != NULL);
7595
7596 s = bfd_get_linker_section
7597 (hash_table->bfd_of_glue_owner, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7598
7599 BFD_ASSERT (s != NULL);
7600
7601 sec_data = elf32_arm_section_data (s);
7602
7603 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
7604 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
7605 BFD_ASSERT (tmp_name);
7606
7607 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
7608 hash_table->num_stm32l4xx_fixes);
7609
7610 myh = elf_link_hash_lookup
7611 (&(hash_table)->root, tmp_name, false, false, false);
7612
7613 BFD_ASSERT (myh == NULL);
7614
7615 bh = NULL;
7616 val = hash_table->stm32l4xx_erratum_glue_size;
7617 _bfd_generic_link_add_one_symbol (link_info, hash_table->bfd_of_glue_owner,
7618 tmp_name, BSF_FUNCTION | BSF_LOCAL, s, val,
7619 NULL, true, false, &bh);
7620
7621 myh = (struct elf_link_hash_entry *) bh;
7622 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7623 myh->forced_local = 1;
7624
7625 /* Link veneer back to calling location. */
7626 sec_data->stm32l4xx_erratumcount += 1;
7627 newerr = (elf32_stm32l4xx_erratum_list *)
7628 bfd_zmalloc (sizeof (elf32_stm32l4xx_erratum_list));
7629
7630 newerr->type = STM32L4XX_ERRATUM_VENEER;
7631 newerr->vma = -1;
7632 newerr->u.v.branch = branch;
7633 newerr->u.v.id = hash_table->num_stm32l4xx_fixes;
7634 branch->u.b.veneer = newerr;
7635
7636 newerr->next = sec_data->stm32l4xx_erratumlist;
7637 sec_data->stm32l4xx_erratumlist = newerr;
7638
7639 /* A symbol for the return from the veneer. */
7640 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
7641 hash_table->num_stm32l4xx_fixes);
7642
7643 myh = elf_link_hash_lookup
7644 (&(hash_table)->root, tmp_name, false, false, false);
7645
7646 if (myh != NULL)
7647 abort ();
7648
7649 bh = NULL;
7650 val = offset + 4;
7651 _bfd_generic_link_add_one_symbol (link_info, branch_bfd, tmp_name, BSF_LOCAL,
7652 branch_sec, val, NULL, true, false, &bh);
7653
7654 myh = (struct elf_link_hash_entry *) bh;
7655 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
7656 myh->forced_local = 1;
7657
7658 free (tmp_name);
7659
7660 /* Generate a mapping symbol for the veneer section, and explicitly add an
7661 entry for that symbol to the code/data map for the section. */
7662 if (hash_table->stm32l4xx_erratum_glue_size == 0)
7663 {
7664 bh = NULL;
7665 /* Creates a THUMB symbol since there is no other choice. */
7666 _bfd_generic_link_add_one_symbol (link_info,
7667 hash_table->bfd_of_glue_owner, "$t",
7668 BSF_LOCAL, s, 0, NULL,
7669 true, false, &bh);
7670
7671 myh = (struct elf_link_hash_entry *) bh;
7672 myh->type = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
7673 myh->forced_local = 1;
7674
7675 /* The elf32_arm_init_maps function only cares about symbols from input
7676 BFDs. We must make a note of this generated mapping symbol
7677 ourselves so that code byteswapping works properly in
7678 elf32_arm_write_section. */
7679 elf32_arm_section_map_add (s, 't', 0);
7680 }
7681
7682 s->size += veneer_size;
7683 hash_table->stm32l4xx_erratum_glue_size += veneer_size;
7684 hash_table->num_stm32l4xx_fixes++;
7685
7686 /* The offset of the veneer. */
7687 return val;
7688 }
7689
7690 #define ARM_GLUE_SECTION_FLAGS \
7691 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7692 | SEC_READONLY | SEC_LINKER_CREATED)
7693
7694 /* Create a fake section for use by the ARM backend of the linker. */
7695
7696 static bool
7697 arm_make_glue_section (bfd * abfd, const char * name)
7698 {
7699 asection * sec;
7700
7701 sec = bfd_get_linker_section (abfd, name);
7702 if (sec != NULL)
7703 /* Already made. */
7704 return true;
7705
7706 sec = bfd_make_section_anyway_with_flags (abfd, name, ARM_GLUE_SECTION_FLAGS);
7707
7708 if (sec == NULL
7709 || !bfd_set_section_alignment (sec, 2))
7710 return false;
7711
7712 /* Set the gc mark to prevent the section from being removed by garbage
7713 collection, despite the fact that no relocs refer to this section. */
7714 sec->gc_mark = 1;
7715
7716 return true;
7717 }
7718
7719 /* Set size of .plt entries. This function is called from the
7720 linker scripts in ld/emultempl/{armelf}.em. */
7721
7722 void
7723 bfd_elf32_arm_use_long_plt (void)
7724 {
7725 elf32_arm_use_long_plt_entry = true;
7726 }
7727
7728 /* Add the glue sections to ABFD. This function is called from the
7729 linker scripts in ld/emultempl/{armelf}.em. */
7730
7731 bool
7732 bfd_elf32_arm_add_glue_sections_to_bfd (bfd *abfd,
7733 struct bfd_link_info *info)
7734 {
7735 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
7736 bool dostm32l4xx = globals
7737 && globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE;
7738 bool addglue;
7739
7740 /* If we are only performing a partial
7741 link do not bother adding the glue. */
7742 if (bfd_link_relocatable (info))
7743 return true;
7744
7745 addglue = arm_make_glue_section (abfd, ARM2THUMB_GLUE_SECTION_NAME)
7746 && arm_make_glue_section (abfd, THUMB2ARM_GLUE_SECTION_NAME)
7747 && arm_make_glue_section (abfd, VFP11_ERRATUM_VENEER_SECTION_NAME)
7748 && arm_make_glue_section (abfd, ARM_BX_GLUE_SECTION_NAME);
7749
7750 if (!dostm32l4xx)
7751 return addglue;
7752
7753 return addglue
7754 && arm_make_glue_section (abfd, STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7755 }
7756
7757 /* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7758 ensures they are not marked for deletion by
7759 strip_excluded_output_sections () when veneers are going to be created
7760 later. Not doing so would trigger assert on empty section size in
7761 lang_size_sections_1 (). */
7762
7763 void
7764 bfd_elf32_arm_keep_private_stub_output_sections (struct bfd_link_info *info)
7765 {
7766 enum elf32_arm_stub_type stub_type;
7767
7768 /* If we are only performing a partial
7769 link do not bother adding the glue. */
7770 if (bfd_link_relocatable (info))
7771 return;
7772
7773 for (stub_type = arm_stub_none + 1; stub_type < max_stub_type; stub_type++)
7774 {
7775 asection *out_sec;
7776 const char *out_sec_name;
7777
7778 if (!arm_dedicated_stub_output_section_required (stub_type))
7779 continue;
7780
7781 out_sec_name = arm_dedicated_stub_output_section_name (stub_type);
7782 out_sec = bfd_get_section_by_name (info->output_bfd, out_sec_name);
7783 if (out_sec != NULL)
7784 out_sec->flags |= SEC_KEEP;
7785 }
7786 }
7787
7788 /* Select a BFD to be used to hold the sections used by the glue code.
7789 This function is called from the linker scripts in ld/emultempl/
7790 {armelf/pe}.em. */
7791
7792 bool
7793 bfd_elf32_arm_get_bfd_for_interworking (bfd *abfd, struct bfd_link_info *info)
7794 {
7795 struct elf32_arm_link_hash_table *globals;
7796
7797 /* If we are only performing a partial link
7798 do not bother getting a bfd to hold the glue. */
7799 if (bfd_link_relocatable (info))
7800 return true;
7801
7802 /* Make sure we don't attach the glue sections to a dynamic object. */
7803 BFD_ASSERT (!(abfd->flags & DYNAMIC));
7804
7805 globals = elf32_arm_hash_table (info);
7806 BFD_ASSERT (globals != NULL);
7807
7808 if (globals->bfd_of_glue_owner != NULL)
7809 return true;
7810
7811 /* Save the bfd for later use. */
7812 globals->bfd_of_glue_owner = abfd;
7813
7814 return true;
7815 }
7816
7817 static void
7818 check_use_blx (struct elf32_arm_link_hash_table *globals)
7819 {
7820 int cpu_arch;
7821
7822 cpu_arch = bfd_elf_get_obj_attr_int (globals->obfd, OBJ_ATTR_PROC,
7823 Tag_CPU_arch);
7824
7825 if (globals->fix_arm1176)
7826 {
7827 if (cpu_arch == TAG_CPU_ARCH_V6T2 || cpu_arch > TAG_CPU_ARCH_V6K)
7828 globals->use_blx = 1;
7829 }
7830 else
7831 {
7832 if (cpu_arch > TAG_CPU_ARCH_V4T)
7833 globals->use_blx = 1;
7834 }
7835 }
7836
7837 bool
7838 bfd_elf32_arm_process_before_allocation (bfd *abfd,
7839 struct bfd_link_info *link_info)
7840 {
7841 Elf_Internal_Shdr *symtab_hdr;
7842 Elf_Internal_Rela *internal_relocs = NULL;
7843 Elf_Internal_Rela *irel, *irelend;
7844 bfd_byte *contents = NULL;
7845
7846 asection *sec;
7847 struct elf32_arm_link_hash_table *globals;
7848
7849 /* If we are only performing a partial link do not bother
7850 to construct any glue. */
7851 if (bfd_link_relocatable (link_info))
7852 return true;
7853
7854 /* Here we have a bfd that is to be included on the link. We have a
7855 hook to do reloc rummaging, before section sizes are nailed down. */
7856 globals = elf32_arm_hash_table (link_info);
7857 BFD_ASSERT (globals != NULL);
7858
7859 check_use_blx (globals);
7860
7861 if (globals->byteswap_code && !bfd_big_endian (abfd))
7862 {
7863 _bfd_error_handler (_("%pB: BE8 images only valid in big-endian mode"),
7864 abfd);
7865 return false;
7866 }
7867
7868 /* PR 5398: If we have not decided to include any loadable sections in
7869 the output then we will not have a glue owner bfd. This is OK, it
7870 just means that there is nothing else for us to do here. */
7871 if (globals->bfd_of_glue_owner == NULL)
7872 return true;
7873
7874 /* Rummage around all the relocs and map the glue vectors. */
7875 sec = abfd->sections;
7876
7877 if (sec == NULL)
7878 return true;
7879
7880 for (; sec != NULL; sec = sec->next)
7881 {
7882 if (sec->reloc_count == 0)
7883 continue;
7884
7885 if ((sec->flags & SEC_EXCLUDE) != 0
7886 || (sec->flags & SEC_HAS_CONTENTS) == 0)
7887 continue;
7888
7889 symtab_hdr = & elf_symtab_hdr (abfd);
7890
7891 /* Load the relocs. */
7892 internal_relocs
7893 = _bfd_elf_link_read_relocs (abfd, sec, NULL, NULL, false);
7894
7895 if (internal_relocs == NULL)
7896 goto error_return;
7897
7898 irelend = internal_relocs + sec->reloc_count;
7899 for (irel = internal_relocs; irel < irelend; irel++)
7900 {
7901 long r_type;
7902 unsigned long r_index;
7903
7904 struct elf_link_hash_entry *h;
7905
7906 r_type = ELF32_R_TYPE (irel->r_info);
7907 r_index = ELF32_R_SYM (irel->r_info);
7908
7909 /* These are the only relocation types we care about. */
7910 if ( r_type != R_ARM_PC24
7911 && (r_type != R_ARM_V4BX || globals->fix_v4bx < 2))
7912 continue;
7913
7914 /* Get the section contents if we haven't done so already. */
7915 if (contents == NULL)
7916 {
7917 /* Get cached copy if it exists. */
7918 if (elf_section_data (sec)->this_hdr.contents != NULL)
7919 contents = elf_section_data (sec)->this_hdr.contents;
7920 else
7921 {
7922 /* Go get them off disk. */
7923 if (! bfd_malloc_and_get_section (abfd, sec, &contents))
7924 goto error_return;
7925 }
7926 }
7927
7928 if (r_type == R_ARM_V4BX)
7929 {
7930 int reg;
7931
7932 reg = bfd_get_32 (abfd, contents + irel->r_offset) & 0xf;
7933 record_arm_bx_glue (link_info, reg);
7934 continue;
7935 }
7936
7937 /* If the relocation is not against a symbol it cannot concern us. */
7938 h = NULL;
7939
7940 /* We don't care about local symbols. */
7941 if (r_index < symtab_hdr->sh_info)
7942 continue;
7943
7944 /* This is an external symbol. */
7945 r_index -= symtab_hdr->sh_info;
7946 h = (struct elf_link_hash_entry *)
7947 elf_sym_hashes (abfd)[r_index];
7948
7949 /* If the relocation is against a static symbol it must be within
7950 the current section and so cannot be a cross ARM/Thumb relocation. */
7951 if (h == NULL)
7952 continue;
7953
7954 /* If the call will go through a PLT entry then we do not need
7955 glue. */
7956 if (globals->root.splt != NULL && h->plt.offset != (bfd_vma) -1)
7957 continue;
7958
7959 switch (r_type)
7960 {
7961 case R_ARM_PC24:
7962 /* This one is a call from arm code. We need to look up
7963 the target of the call. If it is a thumb target, we
7964 insert glue. */
7965 if (ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
7966 == ST_BRANCH_TO_THUMB)
7967 record_arm_to_thumb_glue (link_info, h);
7968 break;
7969
7970 default:
7971 abort ();
7972 }
7973 }
7974
7975 if (elf_section_data (sec)->this_hdr.contents != contents)
7976 free (contents);
7977 contents = NULL;
7978
7979 if (elf_section_data (sec)->relocs != internal_relocs)
7980 free (internal_relocs);
7981 internal_relocs = NULL;
7982 }
7983
7984 return true;
7985
7986 error_return:
7987 if (elf_section_data (sec)->this_hdr.contents != contents)
7988 free (contents);
7989 if (elf_section_data (sec)->relocs != internal_relocs)
7990 free (internal_relocs);
7991
7992 return false;
7993 }
7994 #endif
7995
7996
7997 /* Initialise maps of ARM/Thumb/data for input BFDs. */
7998
7999 void
8000 bfd_elf32_arm_init_maps (bfd *abfd)
8001 {
8002 Elf_Internal_Sym *isymbuf;
8003 Elf_Internal_Shdr *hdr;
8004 unsigned int i, localsyms;
8005
8006 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8007 if (! is_arm_elf (abfd))
8008 return;
8009
8010 if ((abfd->flags & DYNAMIC) != 0)
8011 return;
8012
8013 hdr = & elf_symtab_hdr (abfd);
8014 localsyms = hdr->sh_info;
8015
8016 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8017 should contain the number of local symbols, which should come before any
8018 global symbols. Mapping symbols are always local. */
8019 isymbuf = bfd_elf_get_elf_syms (abfd, hdr, localsyms, 0, NULL, NULL,
8020 NULL);
8021
8022 /* No internal symbols read? Skip this BFD. */
8023 if (isymbuf == NULL)
8024 return;
8025
8026 for (i = 0; i < localsyms; i++)
8027 {
8028 Elf_Internal_Sym *isym = &isymbuf[i];
8029 asection *sec = bfd_section_from_elf_index (abfd, isym->st_shndx);
8030 const char *name;
8031
8032 if (sec != NULL
8033 && ELF_ST_BIND (isym->st_info) == STB_LOCAL)
8034 {
8035 name = bfd_elf_string_from_elf_section (abfd,
8036 hdr->sh_link, isym->st_name);
8037
8038 if (bfd_is_arm_special_symbol_name (name,
8039 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
8040 elf32_arm_section_map_add (sec, name[1], isym->st_value);
8041 }
8042 }
8043 }
8044
8045
8046 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8047 say what they wanted. */
8048
8049 void
8050 bfd_elf32_arm_set_cortex_a8_fix (bfd *obfd, struct bfd_link_info *link_info)
8051 {
8052 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8053 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8054
8055 if (globals == NULL)
8056 return;
8057
8058 if (globals->fix_cortex_a8 == -1)
8059 {
8060 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8061 if (out_attr[Tag_CPU_arch].i == TAG_CPU_ARCH_V7
8062 && (out_attr[Tag_CPU_arch_profile].i == 'A'
8063 || out_attr[Tag_CPU_arch_profile].i == 0))
8064 globals->fix_cortex_a8 = 1;
8065 else
8066 globals->fix_cortex_a8 = 0;
8067 }
8068 }
8069
8070
8071 void
8072 bfd_elf32_arm_set_vfp11_fix (bfd *obfd, struct bfd_link_info *link_info)
8073 {
8074 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8075 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8076
8077 if (globals == NULL)
8078 return;
8079 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8080 if (out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V7)
8081 {
8082 switch (globals->vfp11_fix)
8083 {
8084 case BFD_ARM_VFP11_FIX_DEFAULT:
8085 case BFD_ARM_VFP11_FIX_NONE:
8086 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8087 break;
8088
8089 default:
8090 /* Give a warning, but do as the user requests anyway. */
8091 _bfd_error_handler (_("%pB: warning: selected VFP11 erratum "
8092 "workaround is not necessary for target architecture"), obfd);
8093 }
8094 }
8095 else if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_DEFAULT)
8096 /* For earlier architectures, we might need the workaround, but do not
8097 enable it by default. If users is running with broken hardware, they
8098 must enable the erratum fix explicitly. */
8099 globals->vfp11_fix = BFD_ARM_VFP11_FIX_NONE;
8100 }
8101
8102 void
8103 bfd_elf32_arm_set_stm32l4xx_fix (bfd *obfd, struct bfd_link_info *link_info)
8104 {
8105 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8106 obj_attribute *out_attr = elf_known_obj_attributes_proc (obfd);
8107
8108 if (globals == NULL)
8109 return;
8110
8111 /* We assume only Cortex-M4 may require the fix. */
8112 if (out_attr[Tag_CPU_arch].i != TAG_CPU_ARCH_V7E_M
8113 || out_attr[Tag_CPU_arch_profile].i != 'M')
8114 {
8115 if (globals->stm32l4xx_fix != BFD_ARM_STM32L4XX_FIX_NONE)
8116 /* Give a warning, but do as the user requests anyway. */
8117 _bfd_error_handler
8118 (_("%pB: warning: selected STM32L4XX erratum "
8119 "workaround is not necessary for target architecture"), obfd);
8120 }
8121 }
8122
8123 enum bfd_arm_vfp11_pipe
8124 {
8125 VFP11_FMAC,
8126 VFP11_LS,
8127 VFP11_DS,
8128 VFP11_BAD
8129 };
8130
8131 /* Return a VFP register number. This is encoded as RX:X for single-precision
8132 registers, or X:RX for double-precision registers, where RX is the group of
8133 four bits in the instruction encoding and X is the single extension bit.
8134 RX and X fields are specified using their lowest (starting) bit. The return
8135 value is:
8136
8137 0...31: single-precision registers s0...s31
8138 32...63: double-precision registers d0...d31.
8139
8140 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8141 encounter VFP3 instructions, so we allow the full range for DP registers. */
8142
8143 static unsigned int
8144 bfd_arm_vfp11_regno (unsigned int insn, bool is_double, unsigned int rx,
8145 unsigned int x)
8146 {
8147 if (is_double)
8148 return (((insn >> rx) & 0xf) | (((insn >> x) & 1) << 4)) + 32;
8149 else
8150 return (((insn >> rx) & 0xf) << 1) | ((insn >> x) & 1);
8151 }
8152
8153 /* Set bits in *WMASK according to a register number REG as encoded by
8154 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8155
8156 static void
8157 bfd_arm_vfp11_write_mask (unsigned int *wmask, unsigned int reg)
8158 {
8159 if (reg < 32)
8160 *wmask |= 1 << reg;
8161 else if (reg < 48)
8162 *wmask |= 3 << ((reg - 32) * 2);
8163 }
8164
8165 /* Return TRUE if WMASK overwrites anything in REGS. */
8166
8167 static bool
8168 bfd_arm_vfp11_antidependency (unsigned int wmask, int *regs, int numregs)
8169 {
8170 int i;
8171
8172 for (i = 0; i < numregs; i++)
8173 {
8174 unsigned int reg = regs[i];
8175
8176 if (reg < 32 && (wmask & (1 << reg)) != 0)
8177 return true;
8178
8179 reg -= 32;
8180
8181 if (reg >= 16)
8182 continue;
8183
8184 if ((wmask & (3 << (reg * 2))) != 0)
8185 return true;
8186 }
8187
8188 return false;
8189 }
8190
8191 /* In this function, we're interested in two things: finding input registers
8192 for VFP data-processing instructions, and finding the set of registers which
8193 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8194 hold the written set, so FLDM etc. are easy to deal with (we're only
8195 interested in 32 SP registers or 16 dp registers, due to the VFP version
8196 implemented by the chip in question). DP registers are marked by setting
8197 both SP registers in the write mask). */
8198
8199 static enum bfd_arm_vfp11_pipe
8200 bfd_arm_vfp11_insn_decode (unsigned int insn, unsigned int *destmask, int *regs,
8201 int *numregs)
8202 {
8203 enum bfd_arm_vfp11_pipe vpipe = VFP11_BAD;
8204 bool is_double = ((insn & 0xf00) == 0xb00) ? 1 : 0;
8205
8206 if ((insn & 0x0f000e10) == 0x0e000a00) /* A data-processing insn. */
8207 {
8208 unsigned int pqrs;
8209 unsigned int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8210 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8211
8212 pqrs = ((insn & 0x00800000) >> 20)
8213 | ((insn & 0x00300000) >> 19)
8214 | ((insn & 0x00000040) >> 6);
8215
8216 switch (pqrs)
8217 {
8218 case 0: /* fmac[sd]. */
8219 case 1: /* fnmac[sd]. */
8220 case 2: /* fmsc[sd]. */
8221 case 3: /* fnmsc[sd]. */
8222 vpipe = VFP11_FMAC;
8223 bfd_arm_vfp11_write_mask (destmask, fd);
8224 regs[0] = fd;
8225 regs[1] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8226 regs[2] = fm;
8227 *numregs = 3;
8228 break;
8229
8230 case 4: /* fmul[sd]. */
8231 case 5: /* fnmul[sd]. */
8232 case 6: /* fadd[sd]. */
8233 case 7: /* fsub[sd]. */
8234 vpipe = VFP11_FMAC;
8235 goto vfp_binop;
8236
8237 case 8: /* fdiv[sd]. */
8238 vpipe = VFP11_DS;
8239 vfp_binop:
8240 bfd_arm_vfp11_write_mask (destmask, fd);
8241 regs[0] = bfd_arm_vfp11_regno (insn, is_double, 16, 7); /* Fn. */
8242 regs[1] = fm;
8243 *numregs = 2;
8244 break;
8245
8246 case 15: /* extended opcode. */
8247 {
8248 unsigned int extn = ((insn >> 15) & 0x1e)
8249 | ((insn >> 7) & 1);
8250
8251 switch (extn)
8252 {
8253 case 0: /* fcpy[sd]. */
8254 case 1: /* fabs[sd]. */
8255 case 2: /* fneg[sd]. */
8256 case 8: /* fcmp[sd]. */
8257 case 9: /* fcmpe[sd]. */
8258 case 10: /* fcmpz[sd]. */
8259 case 11: /* fcmpez[sd]. */
8260 case 16: /* fuito[sd]. */
8261 case 17: /* fsito[sd]. */
8262 case 24: /* ftoui[sd]. */
8263 case 25: /* ftouiz[sd]. */
8264 case 26: /* ftosi[sd]. */
8265 case 27: /* ftosiz[sd]. */
8266 /* These instructions will not bounce due to underflow. */
8267 *numregs = 0;
8268 vpipe = VFP11_FMAC;
8269 break;
8270
8271 case 3: /* fsqrt[sd]. */
8272 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8273 registers to cause the erratum in previous instructions. */
8274 bfd_arm_vfp11_write_mask (destmask, fd);
8275 vpipe = VFP11_DS;
8276 break;
8277
8278 case 15: /* fcvt{ds,sd}. */
8279 {
8280 int rnum = 0;
8281
8282 bfd_arm_vfp11_write_mask (destmask, fd);
8283
8284 /* Only FCVTSD can underflow. */
8285 if ((insn & 0x100) != 0)
8286 regs[rnum++] = fm;
8287
8288 *numregs = rnum;
8289
8290 vpipe = VFP11_FMAC;
8291 }
8292 break;
8293
8294 default:
8295 return VFP11_BAD;
8296 }
8297 }
8298 break;
8299
8300 default:
8301 return VFP11_BAD;
8302 }
8303 }
8304 /* Two-register transfer. */
8305 else if ((insn & 0x0fe00ed0) == 0x0c400a10)
8306 {
8307 unsigned int fm = bfd_arm_vfp11_regno (insn, is_double, 0, 5);
8308
8309 if ((insn & 0x100000) == 0)
8310 {
8311 if (is_double)
8312 bfd_arm_vfp11_write_mask (destmask, fm);
8313 else
8314 {
8315 bfd_arm_vfp11_write_mask (destmask, fm);
8316 bfd_arm_vfp11_write_mask (destmask, fm + 1);
8317 }
8318 }
8319
8320 vpipe = VFP11_LS;
8321 }
8322 else if ((insn & 0x0e100e00) == 0x0c100a00) /* A load insn. */
8323 {
8324 int fd = bfd_arm_vfp11_regno (insn, is_double, 12, 22);
8325 unsigned int puw = ((insn >> 21) & 0x1) | (((insn >> 23) & 3) << 1);
8326
8327 switch (puw)
8328 {
8329 case 0: /* Two-reg transfer. We should catch these above. */
8330 abort ();
8331
8332 case 2: /* fldm[sdx]. */
8333 case 3:
8334 case 5:
8335 {
8336 unsigned int i, offset = insn & 0xff;
8337
8338 if (is_double)
8339 offset >>= 1;
8340
8341 for (i = fd; i < fd + offset; i++)
8342 bfd_arm_vfp11_write_mask (destmask, i);
8343 }
8344 break;
8345
8346 case 4: /* fld[sd]. */
8347 case 6:
8348 bfd_arm_vfp11_write_mask (destmask, fd);
8349 break;
8350
8351 default:
8352 return VFP11_BAD;
8353 }
8354
8355 vpipe = VFP11_LS;
8356 }
8357 /* Single-register transfer. Note L==0. */
8358 else if ((insn & 0x0f100e10) == 0x0e000a10)
8359 {
8360 unsigned int opcode = (insn >> 21) & 7;
8361 unsigned int fn = bfd_arm_vfp11_regno (insn, is_double, 16, 7);
8362
8363 switch (opcode)
8364 {
8365 case 0: /* fmsr/fmdlr. */
8366 case 1: /* fmdhr. */
8367 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8368 destination register. I don't know if this is exactly right,
8369 but it is the conservative choice. */
8370 bfd_arm_vfp11_write_mask (destmask, fn);
8371 break;
8372
8373 case 7: /* fmxr. */
8374 break;
8375 }
8376
8377 vpipe = VFP11_LS;
8378 }
8379
8380 return vpipe;
8381 }
8382
8383
8384 static int elf32_arm_compare_mapping (const void * a, const void * b);
8385
8386
8387 /* Look for potentially-troublesome code sequences which might trigger the
8388 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8389 (available from ARM) for details of the erratum. A short version is
8390 described in ld.texinfo. */
8391
8392 bool
8393 bfd_elf32_arm_vfp11_erratum_scan (bfd *abfd, struct bfd_link_info *link_info)
8394 {
8395 asection *sec;
8396 bfd_byte *contents = NULL;
8397 int state = 0;
8398 int regs[3], numregs = 0;
8399 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8400 int use_vector = (globals->vfp11_fix == BFD_ARM_VFP11_FIX_VECTOR);
8401
8402 if (globals == NULL)
8403 return false;
8404
8405 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8406 The states transition as follows:
8407
8408 0 -> 1 (vector) or 0 -> 2 (scalar)
8409 A VFP FMAC-pipeline instruction has been seen. Fill
8410 regs[0]..regs[numregs-1] with its input operands. Remember this
8411 instruction in 'first_fmac'.
8412
8413 1 -> 2
8414 Any instruction, except for a VFP instruction which overwrites
8415 regs[*].
8416
8417 1 -> 3 [ -> 0 ] or
8418 2 -> 3 [ -> 0 ]
8419 A VFP instruction has been seen which overwrites any of regs[*].
8420 We must make a veneer! Reset state to 0 before examining next
8421 instruction.
8422
8423 2 -> 0
8424 If we fail to match anything in state 2, reset to state 0 and reset
8425 the instruction pointer to the instruction after 'first_fmac'.
8426
8427 If the VFP11 vector mode is in use, there must be at least two unrelated
8428 instructions between anti-dependent VFP11 instructions to properly avoid
8429 triggering the erratum, hence the use of the extra state 1. */
8430
8431 /* If we are only performing a partial link do not bother
8432 to construct any glue. */
8433 if (bfd_link_relocatable (link_info))
8434 return true;
8435
8436 /* Skip if this bfd does not correspond to an ELF image. */
8437 if (! is_arm_elf (abfd))
8438 return true;
8439
8440 /* We should have chosen a fix type by the time we get here. */
8441 BFD_ASSERT (globals->vfp11_fix != BFD_ARM_VFP11_FIX_DEFAULT);
8442
8443 if (globals->vfp11_fix == BFD_ARM_VFP11_FIX_NONE)
8444 return true;
8445
8446 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8447 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8448 return true;
8449
8450 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8451 {
8452 unsigned int i, span, first_fmac = 0, veneer_of_insn = 0;
8453 struct _arm_elf_section_data *sec_data;
8454
8455 /* If we don't have executable progbits, we're not interested in this
8456 section. Also skip if section is to be excluded. */
8457 if (elf_section_type (sec) != SHT_PROGBITS
8458 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8459 || (sec->flags & SEC_EXCLUDE) != 0
8460 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8461 || sec->output_section == bfd_abs_section_ptr
8462 || strcmp (sec->name, VFP11_ERRATUM_VENEER_SECTION_NAME) == 0)
8463 continue;
8464
8465 sec_data = elf32_arm_section_data (sec);
8466
8467 if (sec_data->mapcount == 0)
8468 continue;
8469
8470 if (elf_section_data (sec)->this_hdr.contents != NULL)
8471 contents = elf_section_data (sec)->this_hdr.contents;
8472 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8473 goto error_return;
8474
8475 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8476 elf32_arm_compare_mapping);
8477
8478 for (span = 0; span < sec_data->mapcount; span++)
8479 {
8480 unsigned int span_start = sec_data->map[span].vma;
8481 unsigned int span_end = (span == sec_data->mapcount - 1)
8482 ? sec->size : sec_data->map[span + 1].vma;
8483 char span_type = sec_data->map[span].type;
8484
8485 /* FIXME: Only ARM mode is supported at present. We may need to
8486 support Thumb-2 mode also at some point. */
8487 if (span_type != 'a')
8488 continue;
8489
8490 for (i = span_start; i < span_end;)
8491 {
8492 unsigned int next_i = i + 4;
8493 unsigned int insn = bfd_big_endian (abfd)
8494 ? (((unsigned) contents[i] << 24)
8495 | (contents[i + 1] << 16)
8496 | (contents[i + 2] << 8)
8497 | contents[i + 3])
8498 : (((unsigned) contents[i + 3] << 24)
8499 | (contents[i + 2] << 16)
8500 | (contents[i + 1] << 8)
8501 | contents[i]);
8502 unsigned int writemask = 0;
8503 enum bfd_arm_vfp11_pipe vpipe;
8504
8505 switch (state)
8506 {
8507 case 0:
8508 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask, regs,
8509 &numregs);
8510 /* I'm assuming the VFP11 erratum can trigger with denorm
8511 operands on either the FMAC or the DS pipeline. This might
8512 lead to slightly overenthusiastic veneer insertion. */
8513 if (vpipe == VFP11_FMAC || vpipe == VFP11_DS)
8514 {
8515 state = use_vector ? 1 : 2;
8516 first_fmac = i;
8517 veneer_of_insn = insn;
8518 }
8519 break;
8520
8521 case 1:
8522 {
8523 int other_regs[3], other_numregs;
8524 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
8525 other_regs,
8526 &other_numregs);
8527 if (vpipe != VFP11_BAD
8528 && bfd_arm_vfp11_antidependency (writemask, regs,
8529 numregs))
8530 state = 3;
8531 else
8532 state = 2;
8533 }
8534 break;
8535
8536 case 2:
8537 {
8538 int other_regs[3], other_numregs;
8539 vpipe = bfd_arm_vfp11_insn_decode (insn, &writemask,
8540 other_regs,
8541 &other_numregs);
8542 if (vpipe != VFP11_BAD
8543 && bfd_arm_vfp11_antidependency (writemask, regs,
8544 numregs))
8545 state = 3;
8546 else
8547 {
8548 state = 0;
8549 next_i = first_fmac + 4;
8550 }
8551 }
8552 break;
8553
8554 case 3:
8555 abort (); /* Should be unreachable. */
8556 }
8557
8558 if (state == 3)
8559 {
8560 elf32_vfp11_erratum_list *newerr =(elf32_vfp11_erratum_list *)
8561 bfd_zmalloc (sizeof (elf32_vfp11_erratum_list));
8562
8563 elf32_arm_section_data (sec)->erratumcount += 1;
8564
8565 newerr->u.b.vfp_insn = veneer_of_insn;
8566
8567 switch (span_type)
8568 {
8569 case 'a':
8570 newerr->type = VFP11_ERRATUM_BRANCH_TO_ARM_VENEER;
8571 break;
8572
8573 default:
8574 abort ();
8575 }
8576
8577 record_vfp11_erratum_veneer (link_info, newerr, abfd, sec,
8578 first_fmac);
8579
8580 newerr->vma = -1;
8581
8582 newerr->next = sec_data->erratumlist;
8583 sec_data->erratumlist = newerr;
8584
8585 state = 0;
8586 }
8587
8588 i = next_i;
8589 }
8590 }
8591
8592 if (elf_section_data (sec)->this_hdr.contents != contents)
8593 free (contents);
8594 contents = NULL;
8595 }
8596
8597 return true;
8598
8599 error_return:
8600 if (elf_section_data (sec)->this_hdr.contents != contents)
8601 free (contents);
8602
8603 return false;
8604 }
8605
8606 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8607 after sections have been laid out, using specially-named symbols. */
8608
8609 void
8610 bfd_elf32_arm_vfp11_fix_veneer_locations (bfd *abfd,
8611 struct bfd_link_info *link_info)
8612 {
8613 asection *sec;
8614 struct elf32_arm_link_hash_table *globals;
8615 char *tmp_name;
8616
8617 if (bfd_link_relocatable (link_info))
8618 return;
8619
8620 /* Skip if this bfd does not correspond to an ELF image. */
8621 if (! is_arm_elf (abfd))
8622 return;
8623
8624 globals = elf32_arm_hash_table (link_info);
8625 if (globals == NULL)
8626 return;
8627
8628 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8629 (VFP11_ERRATUM_VENEER_ENTRY_NAME) + 10);
8630 BFD_ASSERT (tmp_name);
8631
8632 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8633 {
8634 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8635 elf32_vfp11_erratum_list *errnode = sec_data->erratumlist;
8636
8637 for (; errnode != NULL; errnode = errnode->next)
8638 {
8639 struct elf_link_hash_entry *myh;
8640 bfd_vma vma;
8641
8642 switch (errnode->type)
8643 {
8644 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
8645 case VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER:
8646 /* Find veneer symbol. */
8647 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME,
8648 errnode->u.b.veneer->u.v.id);
8649
8650 myh = elf_link_hash_lookup
8651 (&(globals)->root, tmp_name, false, false, true);
8652
8653 if (myh == NULL)
8654 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8655 abfd, "VFP11", tmp_name);
8656
8657 vma = myh->root.u.def.section->output_section->vma
8658 + myh->root.u.def.section->output_offset
8659 + myh->root.u.def.value;
8660
8661 errnode->u.b.veneer->vma = vma;
8662 break;
8663
8664 case VFP11_ERRATUM_ARM_VENEER:
8665 case VFP11_ERRATUM_THUMB_VENEER:
8666 /* Find return location. */
8667 sprintf (tmp_name, VFP11_ERRATUM_VENEER_ENTRY_NAME "_r",
8668 errnode->u.v.id);
8669
8670 myh = elf_link_hash_lookup
8671 (&(globals)->root, tmp_name, false, false, true);
8672
8673 if (myh == NULL)
8674 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8675 abfd, "VFP11", tmp_name);
8676
8677 vma = myh->root.u.def.section->output_section->vma
8678 + myh->root.u.def.section->output_offset
8679 + myh->root.u.def.value;
8680
8681 errnode->u.v.branch->vma = vma;
8682 break;
8683
8684 default:
8685 abort ();
8686 }
8687 }
8688 }
8689
8690 free (tmp_name);
8691 }
8692
8693 /* Find virtual-memory addresses for STM32L4XX erratum veneers and
8694 return locations after sections have been laid out, using
8695 specially-named symbols. */
8696
8697 void
8698 bfd_elf32_arm_stm32l4xx_fix_veneer_locations (bfd *abfd,
8699 struct bfd_link_info *link_info)
8700 {
8701 asection *sec;
8702 struct elf32_arm_link_hash_table *globals;
8703 char *tmp_name;
8704
8705 if (bfd_link_relocatable (link_info))
8706 return;
8707
8708 /* Skip if this bfd does not correspond to an ELF image. */
8709 if (! is_arm_elf (abfd))
8710 return;
8711
8712 globals = elf32_arm_hash_table (link_info);
8713 if (globals == NULL)
8714 return;
8715
8716 tmp_name = (char *) bfd_malloc ((bfd_size_type) strlen
8717 (STM32L4XX_ERRATUM_VENEER_ENTRY_NAME) + 10);
8718 BFD_ASSERT (tmp_name);
8719
8720 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8721 {
8722 struct _arm_elf_section_data *sec_data = elf32_arm_section_data (sec);
8723 elf32_stm32l4xx_erratum_list *errnode = sec_data->stm32l4xx_erratumlist;
8724
8725 for (; errnode != NULL; errnode = errnode->next)
8726 {
8727 struct elf_link_hash_entry *myh;
8728 bfd_vma vma;
8729
8730 switch (errnode->type)
8731 {
8732 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
8733 /* Find veneer symbol. */
8734 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME,
8735 errnode->u.b.veneer->u.v.id);
8736
8737 myh = elf_link_hash_lookup
8738 (&(globals)->root, tmp_name, false, false, true);
8739
8740 if (myh == NULL)
8741 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8742 abfd, "STM32L4XX", tmp_name);
8743
8744 vma = myh->root.u.def.section->output_section->vma
8745 + myh->root.u.def.section->output_offset
8746 + myh->root.u.def.value;
8747
8748 errnode->u.b.veneer->vma = vma;
8749 break;
8750
8751 case STM32L4XX_ERRATUM_VENEER:
8752 /* Find return location. */
8753 sprintf (tmp_name, STM32L4XX_ERRATUM_VENEER_ENTRY_NAME "_r",
8754 errnode->u.v.id);
8755
8756 myh = elf_link_hash_lookup
8757 (&(globals)->root, tmp_name, false, false, true);
8758
8759 if (myh == NULL)
8760 _bfd_error_handler (_("%pB: unable to find %s veneer `%s'"),
8761 abfd, "STM32L4XX", tmp_name);
8762
8763 vma = myh->root.u.def.section->output_section->vma
8764 + myh->root.u.def.section->output_offset
8765 + myh->root.u.def.value;
8766
8767 errnode->u.v.branch->vma = vma;
8768 break;
8769
8770 default:
8771 abort ();
8772 }
8773 }
8774 }
8775
8776 free (tmp_name);
8777 }
8778
8779 static inline bool
8780 is_thumb2_ldmia (const insn32 insn)
8781 {
8782 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8783 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8784 return (insn & 0xffd02000) == 0xe8900000;
8785 }
8786
8787 static inline bool
8788 is_thumb2_ldmdb (const insn32 insn)
8789 {
8790 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8791 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8792 return (insn & 0xffd02000) == 0xe9100000;
8793 }
8794
8795 static inline bool
8796 is_thumb2_vldm (const insn32 insn)
8797 {
8798 /* A6.5 Extension register load or store instruction
8799 A7.7.229
8800 We look for SP 32-bit and DP 64-bit registers.
8801 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8802 <list> is consecutive 64-bit registers
8803 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
8804 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8805 <list> is consecutive 32-bit registers
8806 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8807 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8808 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8809 return
8810 (((insn & 0xfe100f00) == 0xec100b00) ||
8811 ((insn & 0xfe100f00) == 0xec100a00))
8812 && /* (IA without !). */
8813 (((((insn << 7) >> 28) & 0xd) == 0x4)
8814 /* (IA with !), includes VPOP (when reg number is SP). */
8815 || ((((insn << 7) >> 28) & 0xd) == 0x5)
8816 /* (DB with !). */
8817 || ((((insn << 7) >> 28) & 0xd) == 0x9));
8818 }
8819
8820 /* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8821 VLDM opcode and:
8822 - computes the number and the mode of memory accesses
8823 - decides if the replacement should be done:
8824 . replaces only if > 8-word accesses
8825 . or (testing purposes only) replaces all accesses. */
8826
8827 static bool
8828 stm32l4xx_need_create_replacing_stub (const insn32 insn,
8829 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8830 {
8831 int nb_words = 0;
8832
8833 /* The field encoding the register list is the same for both LDMIA
8834 and LDMDB encodings. */
8835 if (is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn))
8836 nb_words = elf32_arm_popcount (insn & 0x0000ffff);
8837 else if (is_thumb2_vldm (insn))
8838 nb_words = (insn & 0xff);
8839
8840 /* DEFAULT mode accounts for the real bug condition situation,
8841 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8842 return (stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_DEFAULT
8843 ? nb_words > 8
8844 : stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_ALL);
8845 }
8846
8847 /* Look for potentially-troublesome code sequences which might trigger
8848 the STM STM32L4XX erratum. */
8849
8850 bool
8851 bfd_elf32_arm_stm32l4xx_erratum_scan (bfd *abfd,
8852 struct bfd_link_info *link_info)
8853 {
8854 asection *sec;
8855 bfd_byte *contents = NULL;
8856 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
8857
8858 if (globals == NULL)
8859 return false;
8860
8861 /* If we are only performing a partial link do not bother
8862 to construct any glue. */
8863 if (bfd_link_relocatable (link_info))
8864 return true;
8865
8866 /* Skip if this bfd does not correspond to an ELF image. */
8867 if (! is_arm_elf (abfd))
8868 return true;
8869
8870 if (globals->stm32l4xx_fix == BFD_ARM_STM32L4XX_FIX_NONE)
8871 return true;
8872
8873 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8874 if ((abfd->flags & (EXEC_P | DYNAMIC)) != 0)
8875 return true;
8876
8877 for (sec = abfd->sections; sec != NULL; sec = sec->next)
8878 {
8879 unsigned int i, span;
8880 struct _arm_elf_section_data *sec_data;
8881
8882 /* If we don't have executable progbits, we're not interested in this
8883 section. Also skip if section is to be excluded. */
8884 if (elf_section_type (sec) != SHT_PROGBITS
8885 || (elf_section_flags (sec) & SHF_EXECINSTR) == 0
8886 || (sec->flags & SEC_EXCLUDE) != 0
8887 || sec->sec_info_type == SEC_INFO_TYPE_JUST_SYMS
8888 || sec->output_section == bfd_abs_section_ptr
8889 || strcmp (sec->name, STM32L4XX_ERRATUM_VENEER_SECTION_NAME) == 0)
8890 continue;
8891
8892 sec_data = elf32_arm_section_data (sec);
8893
8894 if (sec_data->mapcount == 0)
8895 continue;
8896
8897 if (elf_section_data (sec)->this_hdr.contents != NULL)
8898 contents = elf_section_data (sec)->this_hdr.contents;
8899 else if (! bfd_malloc_and_get_section (abfd, sec, &contents))
8900 goto error_return;
8901
8902 qsort (sec_data->map, sec_data->mapcount, sizeof (elf32_arm_section_map),
8903 elf32_arm_compare_mapping);
8904
8905 for (span = 0; span < sec_data->mapcount; span++)
8906 {
8907 unsigned int span_start = sec_data->map[span].vma;
8908 unsigned int span_end = (span == sec_data->mapcount - 1)
8909 ? sec->size : sec_data->map[span + 1].vma;
8910 char span_type = sec_data->map[span].type;
8911 int itblock_current_pos = 0;
8912
8913 /* Only Thumb2 mode need be supported with this CM4 specific
8914 code, we should not encounter any arm mode eg span_type
8915 != 'a'. */
8916 if (span_type != 't')
8917 continue;
8918
8919 for (i = span_start; i < span_end;)
8920 {
8921 unsigned int insn = bfd_get_16 (abfd, &contents[i]);
8922 bool insn_32bit = false;
8923 bool is_ldm = false;
8924 bool is_vldm = false;
8925 bool is_not_last_in_it_block = false;
8926
8927 /* The first 16-bits of all 32-bit thumb2 instructions start
8928 with opcode[15..13]=0b111 and the encoded op1 can be anything
8929 except opcode[12..11]!=0b00.
8930 See 32-bit Thumb instruction encoding. */
8931 if ((insn & 0xe000) == 0xe000 && (insn & 0x1800) != 0x0000)
8932 insn_32bit = true;
8933
8934 /* Compute the predicate that tells if the instruction
8935 is concerned by the IT block
8936 - Creates an error if there is a ldm that is not
8937 last in the IT block thus cannot be replaced
8938 - Otherwise we can create a branch at the end of the
8939 IT block, it will be controlled naturally by IT
8940 with the proper pseudo-predicate
8941 - So the only interesting predicate is the one that
8942 tells that we are not on the last item of an IT
8943 block. */
8944 if (itblock_current_pos != 0)
8945 is_not_last_in_it_block = !!--itblock_current_pos;
8946
8947 if (insn_32bit)
8948 {
8949 /* Load the rest of the insn (in manual-friendly order). */
8950 insn = (insn << 16) | bfd_get_16 (abfd, &contents[i + 2]);
8951 is_ldm = is_thumb2_ldmia (insn) || is_thumb2_ldmdb (insn);
8952 is_vldm = is_thumb2_vldm (insn);
8953
8954 /* Veneers are created for (v)ldm depending on
8955 option flags and memory accesses conditions; but
8956 if the instruction is not the last instruction of
8957 an IT block, we cannot create a jump there, so we
8958 bail out. */
8959 if ((is_ldm || is_vldm)
8960 && stm32l4xx_need_create_replacing_stub
8961 (insn, globals->stm32l4xx_fix))
8962 {
8963 if (is_not_last_in_it_block)
8964 {
8965 _bfd_error_handler
8966 /* xgettext:c-format */
8967 (_("%pB(%pA+%#x): error: multiple load detected"
8968 " in non-last IT block instruction:"
8969 " STM32L4XX veneer cannot be generated; "
8970 "use gcc option -mrestrict-it to generate"
8971 " only one instruction per IT block"),
8972 abfd, sec, i);
8973 }
8974 else
8975 {
8976 elf32_stm32l4xx_erratum_list *newerr =
8977 (elf32_stm32l4xx_erratum_list *)
8978 bfd_zmalloc
8979 (sizeof (elf32_stm32l4xx_erratum_list));
8980
8981 elf32_arm_section_data (sec)
8982 ->stm32l4xx_erratumcount += 1;
8983 newerr->u.b.insn = insn;
8984 /* We create only thumb branches. */
8985 newerr->type =
8986 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8987 record_stm32l4xx_erratum_veneer
8988 (link_info, newerr, abfd, sec,
8989 i,
8990 is_ldm ?
8991 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8992 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
8993 newerr->vma = -1;
8994 newerr->next = sec_data->stm32l4xx_erratumlist;
8995 sec_data->stm32l4xx_erratumlist = newerr;
8996 }
8997 }
8998 }
8999 else
9000 {
9001 /* A7.7.37 IT p208
9002 IT blocks are only encoded in T1
9003 Encoding T1: IT{x{y{z}}} <firstcond>
9004 1 0 1 1 - 1 1 1 1 - firstcond - mask
9005 if mask = '0000' then see 'related encodings'
9006 We don't deal with UNPREDICTABLE, just ignore these.
9007 There can be no nested IT blocks so an IT block
9008 is naturally a new one for which it is worth
9009 computing its size. */
9010 bool is_newitblock = ((insn & 0xff00) == 0xbf00)
9011 && ((insn & 0x000f) != 0x0000);
9012 /* If we have a new IT block we compute its size. */
9013 if (is_newitblock)
9014 {
9015 /* Compute the number of instructions controlled
9016 by the IT block, it will be used to decide
9017 whether we are inside an IT block or not. */
9018 unsigned int mask = insn & 0x000f;
9019 itblock_current_pos = 4 - ctz (mask);
9020 }
9021 }
9022
9023 i += insn_32bit ? 4 : 2;
9024 }
9025 }
9026
9027 if (elf_section_data (sec)->this_hdr.contents != contents)
9028 free (contents);
9029 contents = NULL;
9030 }
9031
9032 return true;
9033
9034 error_return:
9035 if (elf_section_data (sec)->this_hdr.contents != contents)
9036 free (contents);
9037
9038 return false;
9039 }
9040
9041 /* Set target relocation values needed during linking. */
9042
9043 void
9044 bfd_elf32_arm_set_target_params (struct bfd *output_bfd,
9045 struct bfd_link_info *link_info,
9046 struct elf32_arm_params *params)
9047 {
9048 struct elf32_arm_link_hash_table *globals;
9049
9050 globals = elf32_arm_hash_table (link_info);
9051 if (globals == NULL)
9052 return;
9053
9054 globals->target1_is_rel = params->target1_is_rel;
9055 if (globals->fdpic_p)
9056 globals->target2_reloc = R_ARM_GOT32;
9057 else if (strcmp (params->target2_type, "rel") == 0)
9058 globals->target2_reloc = R_ARM_REL32;
9059 else if (strcmp (params->target2_type, "abs") == 0)
9060 globals->target2_reloc = R_ARM_ABS32;
9061 else if (strcmp (params->target2_type, "got-rel") == 0)
9062 globals->target2_reloc = R_ARM_GOT_PREL;
9063 else
9064 {
9065 _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"),
9066 params->target2_type);
9067 }
9068 globals->fix_v4bx = params->fix_v4bx;
9069 globals->use_blx |= params->use_blx;
9070 globals->vfp11_fix = params->vfp11_denorm_fix;
9071 globals->stm32l4xx_fix = params->stm32l4xx_fix;
9072 if (globals->fdpic_p)
9073 globals->pic_veneer = 1;
9074 else
9075 globals->pic_veneer = params->pic_veneer;
9076 globals->fix_cortex_a8 = params->fix_cortex_a8;
9077 globals->fix_arm1176 = params->fix_arm1176;
9078 globals->cmse_implib = params->cmse_implib;
9079 globals->in_implib_bfd = params->in_implib_bfd;
9080
9081 BFD_ASSERT (is_arm_elf (output_bfd));
9082 elf_arm_tdata (output_bfd)->no_enum_size_warning
9083 = params->no_enum_size_warning;
9084 elf_arm_tdata (output_bfd)->no_wchar_size_warning
9085 = params->no_wchar_size_warning;
9086 }
9087
9088 /* Replace the target offset of a Thumb bl or b.w instruction. */
9089
9090 static void
9091 insert_thumb_branch (bfd *abfd, long int offset, bfd_byte *insn)
9092 {
9093 bfd_vma upper;
9094 bfd_vma lower;
9095 int reloc_sign;
9096
9097 BFD_ASSERT ((offset & 1) == 0);
9098
9099 upper = bfd_get_16 (abfd, insn);
9100 lower = bfd_get_16 (abfd, insn + 2);
9101 reloc_sign = (offset < 0) ? 1 : 0;
9102 upper = (upper & ~(bfd_vma) 0x7ff)
9103 | ((offset >> 12) & 0x3ff)
9104 | (reloc_sign << 10);
9105 lower = (lower & ~(bfd_vma) 0x2fff)
9106 | (((!((offset >> 23) & 1)) ^ reloc_sign) << 13)
9107 | (((!((offset >> 22) & 1)) ^ reloc_sign) << 11)
9108 | ((offset >> 1) & 0x7ff);
9109 bfd_put_16 (abfd, upper, insn);
9110 bfd_put_16 (abfd, lower, insn + 2);
9111 }
9112
9113 /* Thumb code calling an ARM function. */
9114
9115 static int
9116 elf32_thumb_to_arm_stub (struct bfd_link_info * info,
9117 const char * name,
9118 bfd * input_bfd,
9119 bfd * output_bfd,
9120 asection * input_section,
9121 bfd_byte * hit_data,
9122 asection * sym_sec,
9123 bfd_vma offset,
9124 bfd_signed_vma addend,
9125 bfd_vma val,
9126 char **error_message)
9127 {
9128 asection * s = 0;
9129 bfd_vma my_offset;
9130 long int ret_offset;
9131 struct elf_link_hash_entry * myh;
9132 struct elf32_arm_link_hash_table * globals;
9133
9134 myh = find_thumb_glue (info, name, error_message);
9135 if (myh == NULL)
9136 return false;
9137
9138 globals = elf32_arm_hash_table (info);
9139 BFD_ASSERT (globals != NULL);
9140 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9141
9142 my_offset = myh->root.u.def.value;
9143
9144 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9145 THUMB2ARM_GLUE_SECTION_NAME);
9146
9147 BFD_ASSERT (s != NULL);
9148 BFD_ASSERT (s->contents != NULL);
9149 BFD_ASSERT (s->output_section != NULL);
9150
9151 if ((my_offset & 0x01) == 0x01)
9152 {
9153 if (sym_sec != NULL
9154 && sym_sec->owner != NULL
9155 && !INTERWORK_FLAG (sym_sec->owner))
9156 {
9157 _bfd_error_handler
9158 (_("%pB(%s): warning: interworking not enabled;"
9159 " first occurrence: %pB: %s call to %s"),
9160 sym_sec->owner, name, input_bfd, "Thumb", "ARM");
9161
9162 return false;
9163 }
9164
9165 --my_offset;
9166 myh->root.u.def.value = my_offset;
9167
9168 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a1_bx_pc_insn,
9169 s->contents + my_offset);
9170
9171 put_thumb_insn (globals, output_bfd, (bfd_vma) t2a2_noop_insn,
9172 s->contents + my_offset + 2);
9173
9174 ret_offset =
9175 /* Address of destination of the stub. */
9176 ((bfd_signed_vma) val)
9177 - ((bfd_signed_vma)
9178 /* Offset from the start of the current section
9179 to the start of the stubs. */
9180 (s->output_offset
9181 /* Offset of the start of this stub from the start of the stubs. */
9182 + my_offset
9183 /* Address of the start of the current section. */
9184 + s->output_section->vma)
9185 /* The branch instruction is 4 bytes into the stub. */
9186 + 4
9187 /* ARM branches work from the pc of the instruction + 8. */
9188 + 8);
9189
9190 put_arm_insn (globals, output_bfd,
9191 (bfd_vma) t2a3_b_insn | ((ret_offset >> 2) & 0x00FFFFFF),
9192 s->contents + my_offset + 4);
9193 }
9194
9195 BFD_ASSERT (my_offset <= globals->thumb_glue_size);
9196
9197 /* Now go back and fix up the original BL insn to point to here. */
9198 ret_offset =
9199 /* Address of where the stub is located. */
9200 (s->output_section->vma + s->output_offset + my_offset)
9201 /* Address of where the BL is located. */
9202 - (input_section->output_section->vma + input_section->output_offset
9203 + offset)
9204 /* Addend in the relocation. */
9205 - addend
9206 /* Biassing for PC-relative addressing. */
9207 - 8;
9208
9209 insert_thumb_branch (input_bfd, ret_offset, hit_data - input_section->vma);
9210
9211 return true;
9212 }
9213
9214 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
9215
9216 static struct elf_link_hash_entry *
9217 elf32_arm_create_thumb_stub (struct bfd_link_info * info,
9218 const char * name,
9219 bfd * input_bfd,
9220 bfd * output_bfd,
9221 asection * sym_sec,
9222 bfd_vma val,
9223 asection * s,
9224 char ** error_message)
9225 {
9226 bfd_vma my_offset;
9227 long int ret_offset;
9228 struct elf_link_hash_entry * myh;
9229 struct elf32_arm_link_hash_table * globals;
9230
9231 myh = find_arm_glue (info, name, error_message);
9232 if (myh == NULL)
9233 return NULL;
9234
9235 globals = elf32_arm_hash_table (info);
9236 BFD_ASSERT (globals != NULL);
9237 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9238
9239 my_offset = myh->root.u.def.value;
9240
9241 if ((my_offset & 0x01) == 0x01)
9242 {
9243 if (sym_sec != NULL
9244 && sym_sec->owner != NULL
9245 && !INTERWORK_FLAG (sym_sec->owner))
9246 {
9247 _bfd_error_handler
9248 (_("%pB(%s): warning: interworking not enabled;"
9249 " first occurrence: %pB: %s call to %s"),
9250 sym_sec->owner, name, input_bfd, "ARM", "Thumb");
9251 }
9252
9253 --my_offset;
9254 myh->root.u.def.value = my_offset;
9255
9256 if (bfd_link_pic (info)
9257 || globals->root.is_relocatable_executable
9258 || globals->pic_veneer)
9259 {
9260 /* For relocatable objects we can't use absolute addresses,
9261 so construct the address from a relative offset. */
9262 /* TODO: If the offset is small it's probably worth
9263 constructing the address with adds. */
9264 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1p_ldr_insn,
9265 s->contents + my_offset);
9266 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2p_add_pc_insn,
9267 s->contents + my_offset + 4);
9268 put_arm_insn (globals, output_bfd, (bfd_vma) a2t3p_bx_r12_insn,
9269 s->contents + my_offset + 8);
9270 /* Adjust the offset by 4 for the position of the add,
9271 and 8 for the pipeline offset. */
9272 ret_offset = (val - (s->output_offset
9273 + s->output_section->vma
9274 + my_offset + 12))
9275 | 1;
9276 bfd_put_32 (output_bfd, ret_offset,
9277 s->contents + my_offset + 12);
9278 }
9279 else if (globals->use_blx)
9280 {
9281 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1v5_ldr_insn,
9282 s->contents + my_offset);
9283
9284 /* It's a thumb address. Add the low order bit. */
9285 bfd_put_32 (output_bfd, val | a2t2v5_func_addr_insn,
9286 s->contents + my_offset + 4);
9287 }
9288 else
9289 {
9290 put_arm_insn (globals, output_bfd, (bfd_vma) a2t1_ldr_insn,
9291 s->contents + my_offset);
9292
9293 put_arm_insn (globals, output_bfd, (bfd_vma) a2t2_bx_r12_insn,
9294 s->contents + my_offset + 4);
9295
9296 /* It's a thumb address. Add the low order bit. */
9297 bfd_put_32 (output_bfd, val | a2t3_func_addr_insn,
9298 s->contents + my_offset + 8);
9299
9300 my_offset += 12;
9301 }
9302 }
9303
9304 BFD_ASSERT (my_offset <= globals->arm_glue_size);
9305
9306 return myh;
9307 }
9308
9309 /* Arm code calling a Thumb function. */
9310
9311 static int
9312 elf32_arm_to_thumb_stub (struct bfd_link_info * info,
9313 const char * name,
9314 bfd * input_bfd,
9315 bfd * output_bfd,
9316 asection * input_section,
9317 bfd_byte * hit_data,
9318 asection * sym_sec,
9319 bfd_vma offset,
9320 bfd_signed_vma addend,
9321 bfd_vma val,
9322 char **error_message)
9323 {
9324 unsigned long int tmp;
9325 bfd_vma my_offset;
9326 asection * s;
9327 long int ret_offset;
9328 struct elf_link_hash_entry * myh;
9329 struct elf32_arm_link_hash_table * globals;
9330
9331 globals = elf32_arm_hash_table (info);
9332 BFD_ASSERT (globals != NULL);
9333 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9334
9335 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9336 ARM2THUMB_GLUE_SECTION_NAME);
9337 BFD_ASSERT (s != NULL);
9338 BFD_ASSERT (s->contents != NULL);
9339 BFD_ASSERT (s->output_section != NULL);
9340
9341 myh = elf32_arm_create_thumb_stub (info, name, input_bfd, output_bfd,
9342 sym_sec, val, s, error_message);
9343 if (!myh)
9344 return false;
9345
9346 my_offset = myh->root.u.def.value;
9347 tmp = bfd_get_32 (input_bfd, hit_data);
9348 tmp = tmp & 0xFF000000;
9349
9350 /* Somehow these are both 4 too far, so subtract 8. */
9351 ret_offset = (s->output_offset
9352 + my_offset
9353 + s->output_section->vma
9354 - (input_section->output_offset
9355 + input_section->output_section->vma
9356 + offset + addend)
9357 - 8);
9358
9359 tmp = tmp | ((ret_offset >> 2) & 0x00FFFFFF);
9360
9361 bfd_put_32 (output_bfd, (bfd_vma) tmp, hit_data - input_section->vma);
9362
9363 return true;
9364 }
9365
9366 /* Populate Arm stub for an exported Thumb function. */
9367
9368 static bool
9369 elf32_arm_to_thumb_export_stub (struct elf_link_hash_entry *h, void * inf)
9370 {
9371 struct bfd_link_info * info = (struct bfd_link_info *) inf;
9372 asection * s;
9373 struct elf_link_hash_entry * myh;
9374 struct elf32_arm_link_hash_entry *eh;
9375 struct elf32_arm_link_hash_table * globals;
9376 asection *sec;
9377 bfd_vma val;
9378 char *error_message;
9379
9380 eh = elf32_arm_hash_entry (h);
9381 /* Allocate stubs for exported Thumb functions on v4t. */
9382 if (eh->export_glue == NULL)
9383 return true;
9384
9385 globals = elf32_arm_hash_table (info);
9386 BFD_ASSERT (globals != NULL);
9387 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9388
9389 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9390 ARM2THUMB_GLUE_SECTION_NAME);
9391 BFD_ASSERT (s != NULL);
9392 BFD_ASSERT (s->contents != NULL);
9393 BFD_ASSERT (s->output_section != NULL);
9394
9395 sec = eh->export_glue->root.u.def.section;
9396
9397 BFD_ASSERT (sec->output_section != NULL);
9398
9399 val = eh->export_glue->root.u.def.value + sec->output_offset
9400 + sec->output_section->vma;
9401
9402 myh = elf32_arm_create_thumb_stub (info, h->root.root.string,
9403 h->root.u.def.section->owner,
9404 globals->obfd, sec, val, s,
9405 &error_message);
9406 BFD_ASSERT (myh);
9407 return true;
9408 }
9409
9410 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9411
9412 static bfd_vma
9413 elf32_arm_bx_glue (struct bfd_link_info * info, int reg)
9414 {
9415 bfd_byte *p;
9416 bfd_vma glue_addr;
9417 asection *s;
9418 struct elf32_arm_link_hash_table *globals;
9419
9420 globals = elf32_arm_hash_table (info);
9421 BFD_ASSERT (globals != NULL);
9422 BFD_ASSERT (globals->bfd_of_glue_owner != NULL);
9423
9424 s = bfd_get_linker_section (globals->bfd_of_glue_owner,
9425 ARM_BX_GLUE_SECTION_NAME);
9426 BFD_ASSERT (s != NULL);
9427 BFD_ASSERT (s->contents != NULL);
9428 BFD_ASSERT (s->output_section != NULL);
9429
9430 BFD_ASSERT (globals->bx_glue_offset[reg] & 2);
9431
9432 glue_addr = globals->bx_glue_offset[reg] & ~(bfd_vma)3;
9433
9434 if ((globals->bx_glue_offset[reg] & 1) == 0)
9435 {
9436 p = s->contents + glue_addr;
9437 bfd_put_32 (globals->obfd, armbx1_tst_insn + (reg << 16), p);
9438 bfd_put_32 (globals->obfd, armbx2_moveq_insn + reg, p + 4);
9439 bfd_put_32 (globals->obfd, armbx3_bx_insn + reg, p + 8);
9440 globals->bx_glue_offset[reg] |= 1;
9441 }
9442
9443 return glue_addr + s->output_section->vma + s->output_offset;
9444 }
9445
9446 /* Generate Arm stubs for exported Thumb symbols. */
9447 static void
9448 elf32_arm_begin_write_processing (bfd *abfd ATTRIBUTE_UNUSED,
9449 struct bfd_link_info *link_info)
9450 {
9451 struct elf32_arm_link_hash_table * globals;
9452
9453 if (link_info == NULL)
9454 /* Ignore this if we are not called by the ELF backend linker. */
9455 return;
9456
9457 globals = elf32_arm_hash_table (link_info);
9458 if (globals == NULL)
9459 return;
9460
9461 /* If blx is available then exported Thumb symbols are OK and there is
9462 nothing to do. */
9463 if (globals->use_blx)
9464 return;
9465
9466 elf_link_hash_traverse (&globals->root, elf32_arm_to_thumb_export_stub,
9467 link_info);
9468 }
9469
9470 /* Reserve space for COUNT dynamic relocations in relocation selection
9471 SRELOC. */
9472
9473 static void
9474 elf32_arm_allocate_dynrelocs (struct bfd_link_info *info, asection *sreloc,
9475 bfd_size_type count)
9476 {
9477 struct elf32_arm_link_hash_table *htab;
9478
9479 htab = elf32_arm_hash_table (info);
9480 BFD_ASSERT (htab->root.dynamic_sections_created);
9481 if (sreloc == NULL)
9482 abort ();
9483 sreloc->size += RELOC_SIZE (htab) * count;
9484 }
9485
9486 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9487 dynamic, the relocations should go in SRELOC, otherwise they should
9488 go in the special .rel.iplt section. */
9489
9490 static void
9491 elf32_arm_allocate_irelocs (struct bfd_link_info *info, asection *sreloc,
9492 bfd_size_type count)
9493 {
9494 struct elf32_arm_link_hash_table *htab;
9495
9496 htab = elf32_arm_hash_table (info);
9497 if (!htab->root.dynamic_sections_created)
9498 htab->root.irelplt->size += RELOC_SIZE (htab) * count;
9499 else
9500 {
9501 BFD_ASSERT (sreloc != NULL);
9502 sreloc->size += RELOC_SIZE (htab) * count;
9503 }
9504 }
9505
9506 /* Add relocation REL to the end of relocation section SRELOC. */
9507
9508 static void
9509 elf32_arm_add_dynreloc (bfd *output_bfd, struct bfd_link_info *info,
9510 asection *sreloc, Elf_Internal_Rela *rel)
9511 {
9512 bfd_byte *loc;
9513 struct elf32_arm_link_hash_table *htab;
9514
9515 htab = elf32_arm_hash_table (info);
9516 if (!htab->root.dynamic_sections_created
9517 && ELF32_R_TYPE (rel->r_info) == R_ARM_IRELATIVE)
9518 sreloc = htab->root.irelplt;
9519 if (sreloc == NULL)
9520 abort ();
9521 loc = sreloc->contents;
9522 loc += sreloc->reloc_count++ * RELOC_SIZE (htab);
9523 if (sreloc->reloc_count * RELOC_SIZE (htab) > sreloc->size)
9524 abort ();
9525 SWAP_RELOC_OUT (htab) (output_bfd, rel, loc);
9526 }
9527
9528 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9529 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9530 to .plt. */
9531
9532 static void
9533 elf32_arm_allocate_plt_entry (struct bfd_link_info *info,
9534 bool is_iplt_entry,
9535 union gotplt_union *root_plt,
9536 struct arm_plt_info *arm_plt)
9537 {
9538 struct elf32_arm_link_hash_table *htab;
9539 asection *splt;
9540 asection *sgotplt;
9541
9542 htab = elf32_arm_hash_table (info);
9543
9544 if (is_iplt_entry)
9545 {
9546 splt = htab->root.iplt;
9547 sgotplt = htab->root.igotplt;
9548
9549 /* NaCl uses a special first entry in .iplt too. */
9550 if (htab->root.target_os == is_nacl && splt->size == 0)
9551 splt->size += htab->plt_header_size;
9552
9553 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9554 elf32_arm_allocate_irelocs (info, htab->root.irelplt, 1);
9555 }
9556 else
9557 {
9558 splt = htab->root.splt;
9559 sgotplt = htab->root.sgotplt;
9560
9561 if (htab->fdpic_p)
9562 {
9563 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9564 /* For lazy binding, relocations will be put into .rel.plt, in
9565 .rel.got otherwise. */
9566 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9567 if (info->flags & DF_BIND_NOW)
9568 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
9569 else
9570 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9571 }
9572 else
9573 {
9574 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9575 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
9576 }
9577
9578 /* If this is the first .plt entry, make room for the special
9579 first entry. */
9580 if (splt->size == 0)
9581 splt->size += htab->plt_header_size;
9582
9583 htab->next_tls_desc_index++;
9584 }
9585
9586 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9587 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9588 splt->size += PLT_THUMB_STUB_SIZE;
9589 root_plt->offset = splt->size;
9590 splt->size += htab->plt_entry_size;
9591
9592 /* We also need to make an entry in the .got.plt section, which
9593 will be placed in the .got section by the linker script. */
9594 if (is_iplt_entry)
9595 arm_plt->got_offset = sgotplt->size;
9596 else
9597 arm_plt->got_offset = sgotplt->size - 8 * htab->num_tls_desc;
9598 if (htab->fdpic_p)
9599 /* Function descriptor takes 64 bits in GOT. */
9600 sgotplt->size += 8;
9601 else
9602 sgotplt->size += 4;
9603 }
9604
9605 static bfd_vma
9606 arm_movw_immediate (bfd_vma value)
9607 {
9608 return (value & 0x00000fff) | ((value & 0x0000f000) << 4);
9609 }
9610
9611 static bfd_vma
9612 arm_movt_immediate (bfd_vma value)
9613 {
9614 return ((value & 0x0fff0000) >> 16) | ((value & 0xf0000000) >> 12);
9615 }
9616
9617 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9618 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9619 Otherwise, DYNINDX is the index of the symbol in the dynamic
9620 symbol table and SYM_VALUE is undefined.
9621
9622 ROOT_PLT points to the offset of the PLT entry from the start of its
9623 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
9624 bookkeeping information.
9625
9626 Returns FALSE if there was a problem. */
9627
9628 static bool
9629 elf32_arm_populate_plt_entry (bfd *output_bfd, struct bfd_link_info *info,
9630 union gotplt_union *root_plt,
9631 struct arm_plt_info *arm_plt,
9632 int dynindx, bfd_vma sym_value)
9633 {
9634 struct elf32_arm_link_hash_table *htab;
9635 asection *sgot;
9636 asection *splt;
9637 asection *srel;
9638 bfd_byte *loc;
9639 bfd_vma plt_index;
9640 Elf_Internal_Rela rel;
9641 bfd_vma got_header_size;
9642
9643 htab = elf32_arm_hash_table (info);
9644
9645 /* Pick the appropriate sections and sizes. */
9646 if (dynindx == -1)
9647 {
9648 splt = htab->root.iplt;
9649 sgot = htab->root.igotplt;
9650 srel = htab->root.irelplt;
9651
9652 /* There are no reserved entries in .igot.plt, and no special
9653 first entry in .iplt. */
9654 got_header_size = 0;
9655 }
9656 else
9657 {
9658 splt = htab->root.splt;
9659 sgot = htab->root.sgotplt;
9660 srel = htab->root.srelplt;
9661
9662 got_header_size = get_elf_backend_data (output_bfd)->got_header_size;
9663 }
9664 BFD_ASSERT (splt != NULL && srel != NULL);
9665
9666 bfd_vma got_offset, got_address, plt_address;
9667 bfd_vma got_displacement, initial_got_entry;
9668 bfd_byte * ptr;
9669
9670 BFD_ASSERT (sgot != NULL);
9671
9672 /* Get the offset into the .(i)got.plt table of the entry that
9673 corresponds to this function. */
9674 got_offset = (arm_plt->got_offset & -2);
9675
9676 /* Get the index in the procedure linkage table which
9677 corresponds to this symbol. This is the index of this symbol
9678 in all the symbols for which we are making plt entries.
9679 After the reserved .got.plt entries, all symbols appear in
9680 the same order as in .plt. */
9681 if (htab->fdpic_p)
9682 /* Function descriptor takes 8 bytes. */
9683 plt_index = (got_offset - got_header_size) / 8;
9684 else
9685 plt_index = (got_offset - got_header_size) / 4;
9686
9687 /* Calculate the address of the GOT entry. */
9688 got_address = (sgot->output_section->vma
9689 + sgot->output_offset
9690 + got_offset);
9691
9692 /* ...and the address of the PLT entry. */
9693 plt_address = (splt->output_section->vma
9694 + splt->output_offset
9695 + root_plt->offset);
9696
9697 ptr = splt->contents + root_plt->offset;
9698 if (htab->root.target_os == is_vxworks && bfd_link_pic (info))
9699 {
9700 unsigned int i;
9701 bfd_vma val;
9702
9703 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9704 {
9705 val = elf32_arm_vxworks_shared_plt_entry[i];
9706 if (i == 2)
9707 val |= got_address - sgot->output_section->vma;
9708 if (i == 5)
9709 val |= plt_index * RELOC_SIZE (htab);
9710 if (i == 2 || i == 5)
9711 bfd_put_32 (output_bfd, val, ptr);
9712 else
9713 put_arm_insn (htab, output_bfd, val, ptr);
9714 }
9715 }
9716 else if (htab->root.target_os == is_vxworks)
9717 {
9718 unsigned int i;
9719 bfd_vma val;
9720
9721 for (i = 0; i != htab->plt_entry_size / 4; i++, ptr += 4)
9722 {
9723 val = elf32_arm_vxworks_exec_plt_entry[i];
9724 if (i == 2)
9725 val |= got_address;
9726 if (i == 4)
9727 val |= 0xffffff & -((root_plt->offset + i * 4 + 8) >> 2);
9728 if (i == 5)
9729 val |= plt_index * RELOC_SIZE (htab);
9730 if (i == 2 || i == 5)
9731 bfd_put_32 (output_bfd, val, ptr);
9732 else
9733 put_arm_insn (htab, output_bfd, val, ptr);
9734 }
9735
9736 loc = (htab->srelplt2->contents
9737 + (plt_index * 2 + 1) * RELOC_SIZE (htab));
9738
9739 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9740 referencing the GOT for this PLT entry. */
9741 rel.r_offset = plt_address + 8;
9742 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
9743 rel.r_addend = got_offset;
9744 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9745 loc += RELOC_SIZE (htab);
9746
9747 /* Create the R_ARM_ABS32 relocation referencing the
9748 beginning of the PLT for this GOT entry. */
9749 rel.r_offset = got_address;
9750 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
9751 rel.r_addend = 0;
9752 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9753 }
9754 else if (htab->root.target_os == is_nacl)
9755 {
9756 /* Calculate the displacement between the PLT slot and the
9757 common tail that's part of the special initial PLT slot. */
9758 int32_t tail_displacement
9759 = ((splt->output_section->vma + splt->output_offset
9760 + ARM_NACL_PLT_TAIL_OFFSET)
9761 - (plt_address + htab->plt_entry_size + 4));
9762 BFD_ASSERT ((tail_displacement & 3) == 0);
9763 tail_displacement >>= 2;
9764
9765 BFD_ASSERT ((tail_displacement & 0xff000000) == 0
9766 || (-tail_displacement & 0xff000000) == 0);
9767
9768 /* Calculate the displacement between the PLT slot and the entry
9769 in the GOT. The offset accounts for the value produced by
9770 adding to pc in the penultimate instruction of the PLT stub. */
9771 got_displacement = (got_address
9772 - (plt_address + htab->plt_entry_size));
9773
9774 /* NaCl does not support interworking at all. */
9775 BFD_ASSERT (!elf32_arm_plt_needs_thumb_stub_p (info, arm_plt));
9776
9777 put_arm_insn (htab, output_bfd,
9778 elf32_arm_nacl_plt_entry[0]
9779 | arm_movw_immediate (got_displacement),
9780 ptr + 0);
9781 put_arm_insn (htab, output_bfd,
9782 elf32_arm_nacl_plt_entry[1]
9783 | arm_movt_immediate (got_displacement),
9784 ptr + 4);
9785 put_arm_insn (htab, output_bfd,
9786 elf32_arm_nacl_plt_entry[2],
9787 ptr + 8);
9788 put_arm_insn (htab, output_bfd,
9789 elf32_arm_nacl_plt_entry[3]
9790 | (tail_displacement & 0x00ffffff),
9791 ptr + 12);
9792 }
9793 else if (htab->fdpic_p)
9794 {
9795 const bfd_vma *plt_entry = using_thumb_only (htab)
9796 ? elf32_arm_fdpic_thumb_plt_entry
9797 : elf32_arm_fdpic_plt_entry;
9798
9799 /* Fill-up Thumb stub if needed. */
9800 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9801 {
9802 put_thumb_insn (htab, output_bfd,
9803 elf32_arm_plt_thumb_stub[0], ptr - 4);
9804 put_thumb_insn (htab, output_bfd,
9805 elf32_arm_plt_thumb_stub[1], ptr - 2);
9806 }
9807 /* As we are using 32 bit instructions even for the Thumb
9808 version, we have to use 'put_arm_insn' instead of
9809 'put_thumb_insn'. */
9810 put_arm_insn (htab, output_bfd, plt_entry[0], ptr + 0);
9811 put_arm_insn (htab, output_bfd, plt_entry[1], ptr + 4);
9812 put_arm_insn (htab, output_bfd, plt_entry[2], ptr + 8);
9813 put_arm_insn (htab, output_bfd, plt_entry[3], ptr + 12);
9814 bfd_put_32 (output_bfd, got_offset, ptr + 16);
9815
9816 if (!(info->flags & DF_BIND_NOW))
9817 {
9818 /* funcdesc_value_reloc_offset. */
9819 bfd_put_32 (output_bfd,
9820 htab->root.srelplt->reloc_count * RELOC_SIZE (htab),
9821 ptr + 20);
9822 put_arm_insn (htab, output_bfd, plt_entry[6], ptr + 24);
9823 put_arm_insn (htab, output_bfd, plt_entry[7], ptr + 28);
9824 put_arm_insn (htab, output_bfd, plt_entry[8], ptr + 32);
9825 put_arm_insn (htab, output_bfd, plt_entry[9], ptr + 36);
9826 }
9827 }
9828 else if (using_thumb_only (htab))
9829 {
9830 /* PR ld/16017: Generate thumb only PLT entries. */
9831 if (!using_thumb2 (htab))
9832 {
9833 /* FIXME: We ought to be able to generate thumb-1 PLT
9834 instructions... */
9835 _bfd_error_handler (_("%pB: warning: thumb-1 mode PLT generation not currently supported"),
9836 output_bfd);
9837 return false;
9838 }
9839
9840 /* Calculate the displacement between the PLT slot and the entry in
9841 the GOT. The 12-byte offset accounts for the value produced by
9842 adding to pc in the 3rd instruction of the PLT stub. */
9843 got_displacement = got_address - (plt_address + 12);
9844
9845 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9846 instead of 'put_thumb_insn'. */
9847 put_arm_insn (htab, output_bfd,
9848 elf32_thumb2_plt_entry[0]
9849 | ((got_displacement & 0x000000ff) << 16)
9850 | ((got_displacement & 0x00000700) << 20)
9851 | ((got_displacement & 0x00000800) >> 1)
9852 | ((got_displacement & 0x0000f000) >> 12),
9853 ptr + 0);
9854 put_arm_insn (htab, output_bfd,
9855 elf32_thumb2_plt_entry[1]
9856 | ((got_displacement & 0x00ff0000) )
9857 | ((got_displacement & 0x07000000) << 4)
9858 | ((got_displacement & 0x08000000) >> 17)
9859 | ((got_displacement & 0xf0000000) >> 28),
9860 ptr + 4);
9861 put_arm_insn (htab, output_bfd,
9862 elf32_thumb2_plt_entry[2],
9863 ptr + 8);
9864 put_arm_insn (htab, output_bfd,
9865 elf32_thumb2_plt_entry[3],
9866 ptr + 12);
9867 }
9868 else
9869 {
9870 /* Calculate the displacement between the PLT slot and the
9871 entry in the GOT. The eight-byte offset accounts for the
9872 value produced by adding to pc in the first instruction
9873 of the PLT stub. */
9874 got_displacement = got_address - (plt_address + 8);
9875
9876 if (elf32_arm_plt_needs_thumb_stub_p (info, arm_plt))
9877 {
9878 put_thumb_insn (htab, output_bfd,
9879 elf32_arm_plt_thumb_stub[0], ptr - 4);
9880 put_thumb_insn (htab, output_bfd,
9881 elf32_arm_plt_thumb_stub[1], ptr - 2);
9882 }
9883
9884 if (!elf32_arm_use_long_plt_entry)
9885 {
9886 BFD_ASSERT ((got_displacement & 0xf0000000) == 0);
9887
9888 put_arm_insn (htab, output_bfd,
9889 elf32_arm_plt_entry_short[0]
9890 | ((got_displacement & 0x0ff00000) >> 20),
9891 ptr + 0);
9892 put_arm_insn (htab, output_bfd,
9893 elf32_arm_plt_entry_short[1]
9894 | ((got_displacement & 0x000ff000) >> 12),
9895 ptr+ 4);
9896 put_arm_insn (htab, output_bfd,
9897 elf32_arm_plt_entry_short[2]
9898 | (got_displacement & 0x00000fff),
9899 ptr + 8);
9900 #ifdef FOUR_WORD_PLT
9901 bfd_put_32 (output_bfd, elf32_arm_plt_entry_short[3], ptr + 12);
9902 #endif
9903 }
9904 else
9905 {
9906 put_arm_insn (htab, output_bfd,
9907 elf32_arm_plt_entry_long[0]
9908 | ((got_displacement & 0xf0000000) >> 28),
9909 ptr + 0);
9910 put_arm_insn (htab, output_bfd,
9911 elf32_arm_plt_entry_long[1]
9912 | ((got_displacement & 0x0ff00000) >> 20),
9913 ptr + 4);
9914 put_arm_insn (htab, output_bfd,
9915 elf32_arm_plt_entry_long[2]
9916 | ((got_displacement & 0x000ff000) >> 12),
9917 ptr+ 8);
9918 put_arm_insn (htab, output_bfd,
9919 elf32_arm_plt_entry_long[3]
9920 | (got_displacement & 0x00000fff),
9921 ptr + 12);
9922 }
9923 }
9924
9925 /* Fill in the entry in the .rel(a).(i)plt section. */
9926 rel.r_offset = got_address;
9927 rel.r_addend = 0;
9928 if (dynindx == -1)
9929 {
9930 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9931 The dynamic linker or static executable then calls SYM_VALUE
9932 to determine the correct run-time value of the .igot.plt entry. */
9933 rel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
9934 initial_got_entry = sym_value;
9935 }
9936 else
9937 {
9938 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9939 used by PLT entry. */
9940 if (htab->fdpic_p)
9941 {
9942 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_FUNCDESC_VALUE);
9943 initial_got_entry = 0;
9944 }
9945 else
9946 {
9947 rel.r_info = ELF32_R_INFO (dynindx, R_ARM_JUMP_SLOT);
9948 initial_got_entry = (splt->output_section->vma
9949 + splt->output_offset);
9950
9951 /* PR ld/16017
9952 When thumb only we need to set the LSB for any address that
9953 will be used with an interworking branch instruction. */
9954 if (using_thumb_only (htab))
9955 initial_got_entry |= 1;
9956 }
9957 }
9958
9959 /* Fill in the entry in the global offset table. */
9960 bfd_put_32 (output_bfd, initial_got_entry,
9961 sgot->contents + got_offset);
9962
9963 if (htab->fdpic_p && !(info->flags & DF_BIND_NOW))
9964 {
9965 /* Setup initial funcdesc value. */
9966 /* FIXME: we don't support lazy binding because there is a
9967 race condition between both words getting written and
9968 some other thread attempting to read them. The ARM
9969 architecture does not have an atomic 64 bit load/store
9970 instruction that could be used to prevent it; it is
9971 recommended that threaded FDPIC applications run with the
9972 LD_BIND_NOW environment variable set. */
9973 bfd_put_32 (output_bfd, plt_address + 0x18,
9974 sgot->contents + got_offset);
9975 bfd_put_32 (output_bfd, -1 /*TODO*/,
9976 sgot->contents + got_offset + 4);
9977 }
9978
9979 if (dynindx == -1)
9980 elf32_arm_add_dynreloc (output_bfd, info, srel, &rel);
9981 else
9982 {
9983 if (htab->fdpic_p)
9984 {
9985 /* For FDPIC we put PLT relocationss into .rel.got when not
9986 lazy binding otherwise we put them in .rel.plt. For now,
9987 we don't support lazy binding so put it in .rel.got. */
9988 if (info->flags & DF_BIND_NOW)
9989 elf32_arm_add_dynreloc (output_bfd, info, htab->root.srelgot, &rel);
9990 else
9991 elf32_arm_add_dynreloc (output_bfd, info, htab->root.srelplt, &rel);
9992 }
9993 else
9994 {
9995 loc = srel->contents + plt_index * RELOC_SIZE (htab);
9996 SWAP_RELOC_OUT (htab) (output_bfd, &rel, loc);
9997 }
9998 }
9999
10000 return true;
10001 }
10002
10003 /* Some relocations map to different relocations depending on the
10004 target. Return the real relocation. */
10005
10006 static int
10007 arm_real_reloc_type (struct elf32_arm_link_hash_table * globals,
10008 int r_type)
10009 {
10010 switch (r_type)
10011 {
10012 case R_ARM_TARGET1:
10013 if (globals->target1_is_rel)
10014 return R_ARM_REL32;
10015 else
10016 return R_ARM_ABS32;
10017
10018 case R_ARM_TARGET2:
10019 return globals->target2_reloc;
10020
10021 default:
10022 return r_type;
10023 }
10024 }
10025
10026 /* Return the base VMA address which should be subtracted from real addresses
10027 when resolving @dtpoff relocation.
10028 This is PT_TLS segment p_vaddr. */
10029
10030 static bfd_vma
10031 dtpoff_base (struct bfd_link_info *info)
10032 {
10033 /* If tls_sec is NULL, we should have signalled an error already. */
10034 if (elf_hash_table (info)->tls_sec == NULL)
10035 return 0;
10036 return elf_hash_table (info)->tls_sec->vma;
10037 }
10038
10039 /* Return the relocation value for @tpoff relocation
10040 if STT_TLS virtual address is ADDRESS. */
10041
10042 static bfd_vma
10043 tpoff (struct bfd_link_info *info, bfd_vma address)
10044 {
10045 struct elf_link_hash_table *htab = elf_hash_table (info);
10046 bfd_vma base;
10047
10048 /* If tls_sec is NULL, we should have signalled an error already. */
10049 if (htab->tls_sec == NULL)
10050 return 0;
10051 base = align_power ((bfd_vma) TCB_SIZE, htab->tls_sec->alignment_power);
10052 return address - htab->tls_sec->vma + base;
10053 }
10054
10055 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10056 VALUE is the relocation value. */
10057
10058 static bfd_reloc_status_type
10059 elf32_arm_abs12_reloc (bfd *abfd, void *data, bfd_vma value)
10060 {
10061 if (value > 0xfff)
10062 return bfd_reloc_overflow;
10063
10064 value |= bfd_get_32 (abfd, data) & 0xfffff000;
10065 bfd_put_32 (abfd, value, data);
10066 return bfd_reloc_ok;
10067 }
10068
10069 /* Handle TLS relaxations. Relaxing is possible for symbols that use
10070 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10071 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10072
10073 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10074 is to then call final_link_relocate. Return other values in the
10075 case of error.
10076
10077 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10078 the pre-relaxed code. It would be nice if the relocs were updated
10079 to match the optimization. */
10080
10081 static bfd_reloc_status_type
10082 elf32_arm_tls_relax (struct elf32_arm_link_hash_table *globals,
10083 bfd *input_bfd, asection *input_sec, bfd_byte *contents,
10084 Elf_Internal_Rela *rel, unsigned long is_local)
10085 {
10086 unsigned long insn;
10087
10088 switch (ELF32_R_TYPE (rel->r_info))
10089 {
10090 default:
10091 return bfd_reloc_notsupported;
10092
10093 case R_ARM_TLS_GOTDESC:
10094 if (is_local)
10095 insn = 0;
10096 else
10097 {
10098 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10099 if (insn & 1)
10100 insn -= 5; /* THUMB */
10101 else
10102 insn -= 8; /* ARM */
10103 }
10104 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10105 return bfd_reloc_continue;
10106
10107 case R_ARM_THM_TLS_DESCSEQ:
10108 /* Thumb insn. */
10109 insn = bfd_get_16 (input_bfd, contents + rel->r_offset);
10110 if ((insn & 0xff78) == 0x4478) /* add rx, pc */
10111 {
10112 if (is_local)
10113 /* nop */
10114 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10115 }
10116 else if ((insn & 0xffc0) == 0x6840) /* ldr rx,[ry,#4] */
10117 {
10118 if (is_local)
10119 /* nop */
10120 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10121 else
10122 /* ldr rx,[ry] */
10123 bfd_put_16 (input_bfd, insn & 0xf83f, contents + rel->r_offset);
10124 }
10125 else if ((insn & 0xff87) == 0x4780) /* blx rx */
10126 {
10127 if (is_local)
10128 /* nop */
10129 bfd_put_16 (input_bfd, 0x46c0, contents + rel->r_offset);
10130 else
10131 /* mov r0, rx */
10132 bfd_put_16 (input_bfd, 0x4600 | (insn & 0x78),
10133 contents + rel->r_offset);
10134 }
10135 else
10136 {
10137 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
10138 /* It's a 32 bit instruction, fetch the rest of it for
10139 error generation. */
10140 insn = (insn << 16)
10141 | bfd_get_16 (input_bfd, contents + rel->r_offset + 2);
10142 _bfd_error_handler
10143 /* xgettext:c-format */
10144 (_("%pB(%pA+%#" PRIx64 "): "
10145 "unexpected %s instruction '%#lx' in TLS trampoline"),
10146 input_bfd, input_sec, (uint64_t) rel->r_offset,
10147 "Thumb", insn);
10148 return bfd_reloc_notsupported;
10149 }
10150 break;
10151
10152 case R_ARM_TLS_DESCSEQ:
10153 /* arm insn. */
10154 insn = bfd_get_32 (input_bfd, contents + rel->r_offset);
10155 if ((insn & 0xffff0ff0) == 0xe08f0000) /* add rx,pc,ry */
10156 {
10157 if (is_local)
10158 /* mov rx, ry */
10159 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xffff),
10160 contents + rel->r_offset);
10161 }
10162 else if ((insn & 0xfff00fff) == 0xe5900004) /* ldr rx,[ry,#4]*/
10163 {
10164 if (is_local)
10165 /* nop */
10166 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10167 else
10168 /* ldr rx,[ry] */
10169 bfd_put_32 (input_bfd, insn & 0xfffff000,
10170 contents + rel->r_offset);
10171 }
10172 else if ((insn & 0xfffffff0) == 0xe12fff30) /* blx rx */
10173 {
10174 if (is_local)
10175 /* nop */
10176 bfd_put_32 (input_bfd, 0xe1a00000, contents + rel->r_offset);
10177 else
10178 /* mov r0, rx */
10179 bfd_put_32 (input_bfd, 0xe1a00000 | (insn & 0xf),
10180 contents + rel->r_offset);
10181 }
10182 else
10183 {
10184 _bfd_error_handler
10185 /* xgettext:c-format */
10186 (_("%pB(%pA+%#" PRIx64 "): "
10187 "unexpected %s instruction '%#lx' in TLS trampoline"),
10188 input_bfd, input_sec, (uint64_t) rel->r_offset,
10189 "ARM", insn);
10190 return bfd_reloc_notsupported;
10191 }
10192 break;
10193
10194 case R_ARM_TLS_CALL:
10195 /* GD->IE relaxation, turn the instruction into 'nop' or
10196 'ldr r0, [pc,r0]' */
10197 insn = is_local ? 0xe1a00000 : 0xe79f0000;
10198 bfd_put_32 (input_bfd, insn, contents + rel->r_offset);
10199 break;
10200
10201 case R_ARM_THM_TLS_CALL:
10202 /* GD->IE relaxation. */
10203 if (!is_local)
10204 /* add r0,pc; ldr r0, [r0] */
10205 insn = 0x44786800;
10206 else if (using_thumb2 (globals))
10207 /* nop.w */
10208 insn = 0xf3af8000;
10209 else
10210 /* nop; nop */
10211 insn = 0xbf00bf00;
10212
10213 bfd_put_16 (input_bfd, insn >> 16, contents + rel->r_offset);
10214 bfd_put_16 (input_bfd, insn & 0xffff, contents + rel->r_offset + 2);
10215 break;
10216 }
10217 return bfd_reloc_ok;
10218 }
10219
10220 /* For a given value of n, calculate the value of G_n as required to
10221 deal with group relocations. We return it in the form of an
10222 encoded constant-and-rotation, together with the final residual. If n is
10223 specified as less than zero, then final_residual is filled with the
10224 input value and no further action is performed. */
10225
10226 static bfd_vma
10227 calculate_group_reloc_mask (bfd_vma value, int n, bfd_vma *final_residual)
10228 {
10229 int current_n;
10230 bfd_vma g_n;
10231 bfd_vma encoded_g_n = 0;
10232 bfd_vma residual = value; /* Also known as Y_n. */
10233
10234 for (current_n = 0; current_n <= n; current_n++)
10235 {
10236 int shift;
10237
10238 /* Calculate which part of the value to mask. */
10239 if (residual == 0)
10240 shift = 0;
10241 else
10242 {
10243 int msb;
10244
10245 /* Determine the most significant bit in the residual and
10246 align the resulting value to a 2-bit boundary. */
10247 for (msb = 30; msb >= 0; msb -= 2)
10248 if (residual & (3u << msb))
10249 break;
10250
10251 /* The desired shift is now (msb - 6), or zero, whichever
10252 is the greater. */
10253 shift = msb - 6;
10254 if (shift < 0)
10255 shift = 0;
10256 }
10257
10258 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10259 g_n = residual & (0xff << shift);
10260 encoded_g_n = (g_n >> shift)
10261 | ((g_n <= 0xff ? 0 : (32 - shift) / 2) << 8);
10262
10263 /* Calculate the residual for the next time around. */
10264 residual &= ~g_n;
10265 }
10266
10267 *final_residual = residual;
10268
10269 return encoded_g_n;
10270 }
10271
10272 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
10273 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
10274
10275 static int
10276 identify_add_or_sub (bfd_vma insn)
10277 {
10278 int opcode = insn & 0x1e00000;
10279
10280 if (opcode == 1 << 23) /* ADD */
10281 return 1;
10282
10283 if (opcode == 1 << 22) /* SUB */
10284 return -1;
10285
10286 return 0;
10287 }
10288
10289 /* Perform a relocation as part of a final link. */
10290
10291 static bfd_reloc_status_type
10292 elf32_arm_final_link_relocate (reloc_howto_type * howto,
10293 bfd * input_bfd,
10294 bfd * output_bfd,
10295 asection * input_section,
10296 bfd_byte * contents,
10297 Elf_Internal_Rela * rel,
10298 bfd_vma value,
10299 struct bfd_link_info * info,
10300 asection * sym_sec,
10301 const char * sym_name,
10302 unsigned char st_type,
10303 enum arm_st_branch_type branch_type,
10304 struct elf_link_hash_entry * h,
10305 bool * unresolved_reloc_p,
10306 char ** error_message)
10307 {
10308 unsigned long r_type = howto->type;
10309 unsigned long r_symndx;
10310 bfd_byte * hit_data = contents + rel->r_offset;
10311 bfd_vma * local_got_offsets;
10312 bfd_vma * local_tlsdesc_gotents;
10313 asection * sgot;
10314 asection * splt;
10315 asection * sreloc = NULL;
10316 asection * srelgot;
10317 bfd_vma addend;
10318 bfd_signed_vma signed_addend;
10319 unsigned char dynreloc_st_type;
10320 bfd_vma dynreloc_value;
10321 struct elf32_arm_link_hash_table * globals;
10322 struct elf32_arm_link_hash_entry *eh;
10323 union gotplt_union *root_plt;
10324 struct arm_plt_info *arm_plt;
10325 bfd_vma plt_offset;
10326 bfd_vma gotplt_offset;
10327 bool has_iplt_entry;
10328 bool resolved_to_zero;
10329
10330 globals = elf32_arm_hash_table (info);
10331 if (globals == NULL)
10332 return bfd_reloc_notsupported;
10333
10334 BFD_ASSERT (is_arm_elf (input_bfd));
10335 BFD_ASSERT (howto != NULL);
10336
10337 /* Some relocation types map to different relocations depending on the
10338 target. We pick the right one here. */
10339 r_type = arm_real_reloc_type (globals, r_type);
10340
10341 /* It is possible to have linker relaxations on some TLS access
10342 models. Update our information here. */
10343 r_type = elf32_arm_tls_transition (info, r_type, h);
10344
10345 if (r_type != howto->type)
10346 howto = elf32_arm_howto_from_type (r_type);
10347
10348 eh = (struct elf32_arm_link_hash_entry *) h;
10349 sgot = globals->root.sgot;
10350 local_got_offsets = elf_local_got_offsets (input_bfd);
10351 local_tlsdesc_gotents = elf32_arm_local_tlsdesc_gotent (input_bfd);
10352
10353 if (globals->root.dynamic_sections_created)
10354 srelgot = globals->root.srelgot;
10355 else
10356 srelgot = NULL;
10357
10358 r_symndx = ELF32_R_SYM (rel->r_info);
10359
10360 if (globals->use_rel)
10361 {
10362 bfd_vma sign;
10363
10364 switch (bfd_get_reloc_size (howto))
10365 {
10366 case 1: addend = bfd_get_8 (input_bfd, hit_data); break;
10367 case 2: addend = bfd_get_16 (input_bfd, hit_data); break;
10368 case 4: addend = bfd_get_32 (input_bfd, hit_data); break;
10369 default: addend = 0; break;
10370 }
10371 /* Note: the addend and signed_addend calculated here are
10372 incorrect for any split field. */
10373 addend &= howto->src_mask;
10374 sign = howto->src_mask & ~(howto->src_mask >> 1);
10375 signed_addend = (addend ^ sign) - sign;
10376 signed_addend = (bfd_vma) signed_addend << howto->rightshift;
10377 addend <<= howto->rightshift;
10378 }
10379 else
10380 addend = signed_addend = rel->r_addend;
10381
10382 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10383 are resolving a function call relocation. */
10384 if (using_thumb_only (globals)
10385 && (r_type == R_ARM_THM_CALL
10386 || r_type == R_ARM_THM_JUMP24)
10387 && branch_type == ST_BRANCH_TO_ARM)
10388 branch_type = ST_BRANCH_TO_THUMB;
10389
10390 /* Record the symbol information that should be used in dynamic
10391 relocations. */
10392 dynreloc_st_type = st_type;
10393 dynreloc_value = value;
10394 if (branch_type == ST_BRANCH_TO_THUMB)
10395 dynreloc_value |= 1;
10396
10397 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10398 VALUE appropriately for relocations that we resolve at link time. */
10399 has_iplt_entry = false;
10400 if (elf32_arm_get_plt_info (input_bfd, globals, eh, r_symndx, &root_plt,
10401 &arm_plt)
10402 && root_plt->offset != (bfd_vma) -1)
10403 {
10404 plt_offset = root_plt->offset;
10405 gotplt_offset = arm_plt->got_offset;
10406
10407 if (h == NULL || eh->is_iplt)
10408 {
10409 has_iplt_entry = true;
10410 splt = globals->root.iplt;
10411
10412 /* Populate .iplt entries here, because not all of them will
10413 be seen by finish_dynamic_symbol. The lower bit is set if
10414 we have already populated the entry. */
10415 if (plt_offset & 1)
10416 plt_offset--;
10417 else
10418 {
10419 if (elf32_arm_populate_plt_entry (output_bfd, info, root_plt, arm_plt,
10420 -1, dynreloc_value))
10421 root_plt->offset |= 1;
10422 else
10423 return bfd_reloc_notsupported;
10424 }
10425
10426 /* Static relocations always resolve to the .iplt entry. */
10427 st_type = STT_FUNC;
10428 value = (splt->output_section->vma
10429 + splt->output_offset
10430 + plt_offset);
10431 branch_type = ST_BRANCH_TO_ARM;
10432
10433 /* If there are non-call relocations that resolve to the .iplt
10434 entry, then all dynamic ones must too. */
10435 if (arm_plt->noncall_refcount != 0)
10436 {
10437 dynreloc_st_type = st_type;
10438 dynreloc_value = value;
10439 }
10440 }
10441 else
10442 /* We populate the .plt entry in finish_dynamic_symbol. */
10443 splt = globals->root.splt;
10444 }
10445 else
10446 {
10447 splt = NULL;
10448 plt_offset = (bfd_vma) -1;
10449 gotplt_offset = (bfd_vma) -1;
10450 }
10451
10452 resolved_to_zero = (h != NULL
10453 && UNDEFWEAK_NO_DYNAMIC_RELOC (info, h));
10454
10455 switch (r_type)
10456 {
10457 case R_ARM_NONE:
10458 /* We don't need to find a value for this symbol. It's just a
10459 marker. */
10460 *unresolved_reloc_p = false;
10461 return bfd_reloc_ok;
10462
10463 case R_ARM_ABS12:
10464 if (globals->root.target_os != is_vxworks)
10465 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10466 /* Fall through. */
10467
10468 case R_ARM_PC24:
10469 case R_ARM_ABS32:
10470 case R_ARM_ABS32_NOI:
10471 case R_ARM_REL32:
10472 case R_ARM_REL32_NOI:
10473 case R_ARM_CALL:
10474 case R_ARM_JUMP24:
10475 case R_ARM_XPC25:
10476 case R_ARM_PREL31:
10477 case R_ARM_PLT32:
10478 /* Handle relocations which should use the PLT entry. ABS32/REL32
10479 will use the symbol's value, which may point to a PLT entry, but we
10480 don't need to handle that here. If we created a PLT entry, all
10481 branches in this object should go to it, except if the PLT is too
10482 far away, in which case a long branch stub should be inserted. */
10483 if ((r_type != R_ARM_ABS32 && r_type != R_ARM_REL32
10484 && r_type != R_ARM_ABS32_NOI && r_type != R_ARM_REL32_NOI
10485 && r_type != R_ARM_CALL
10486 && r_type != R_ARM_JUMP24
10487 && r_type != R_ARM_PLT32)
10488 && plt_offset != (bfd_vma) -1)
10489 {
10490 /* If we've created a .plt section, and assigned a PLT entry
10491 to this function, it must either be a STT_GNU_IFUNC reference
10492 or not be known to bind locally. In other cases, we should
10493 have cleared the PLT entry by now. */
10494 BFD_ASSERT (has_iplt_entry || !SYMBOL_CALLS_LOCAL (info, h));
10495
10496 value = (splt->output_section->vma
10497 + splt->output_offset
10498 + plt_offset);
10499 *unresolved_reloc_p = false;
10500 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10501 contents, rel->r_offset, value,
10502 rel->r_addend);
10503 }
10504
10505 /* When generating a shared object or relocatable executable, these
10506 relocations are copied into the output file to be resolved at
10507 run time. */
10508 if ((bfd_link_pic (info)
10509 || globals->root.is_relocatable_executable
10510 || globals->fdpic_p)
10511 && (input_section->flags & SEC_ALLOC)
10512 && !(globals->root.target_os == is_vxworks
10513 && strcmp (input_section->output_section->name,
10514 ".tls_vars") == 0)
10515 && ((r_type != R_ARM_REL32 && r_type != R_ARM_REL32_NOI)
10516 || !SYMBOL_CALLS_LOCAL (info, h))
10517 && !(input_bfd == globals->stub_bfd
10518 && strstr (input_section->name, STUB_SUFFIX))
10519 && (h == NULL
10520 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
10521 && !resolved_to_zero)
10522 || h->root.type != bfd_link_hash_undefweak)
10523 && r_type != R_ARM_PC24
10524 && r_type != R_ARM_CALL
10525 && r_type != R_ARM_JUMP24
10526 && r_type != R_ARM_PREL31
10527 && r_type != R_ARM_PLT32)
10528 {
10529 Elf_Internal_Rela outrel;
10530 bool skip, relocate;
10531 int isrofixup = 0;
10532
10533 if ((r_type == R_ARM_REL32 || r_type == R_ARM_REL32_NOI)
10534 && !h->def_regular)
10535 {
10536 char *v = _("shared object");
10537
10538 if (bfd_link_executable (info))
10539 v = _("PIE executable");
10540
10541 _bfd_error_handler
10542 (_("%pB: relocation %s against external or undefined symbol `%s'"
10543 " can not be used when making a %s; recompile with -fPIC"), input_bfd,
10544 elf32_arm_howto_table_1[r_type].name, h->root.root.string, v);
10545 return bfd_reloc_notsupported;
10546 }
10547
10548 *unresolved_reloc_p = false;
10549
10550 if (sreloc == NULL && globals->root.dynamic_sections_created)
10551 {
10552 sreloc = _bfd_elf_get_dynamic_reloc_section (input_bfd, input_section,
10553 ! globals->use_rel);
10554
10555 if (sreloc == NULL)
10556 return bfd_reloc_notsupported;
10557 }
10558
10559 skip = false;
10560 relocate = false;
10561
10562 outrel.r_addend = addend;
10563 outrel.r_offset =
10564 _bfd_elf_section_offset (output_bfd, info, input_section,
10565 rel->r_offset);
10566 if (outrel.r_offset == (bfd_vma) -1)
10567 skip = true;
10568 else if (outrel.r_offset == (bfd_vma) -2)
10569 skip = true, relocate = true;
10570 outrel.r_offset += (input_section->output_section->vma
10571 + input_section->output_offset);
10572
10573 if (skip)
10574 memset (&outrel, 0, sizeof outrel);
10575 else if (h != NULL
10576 && h->dynindx != -1
10577 && (!bfd_link_pic (info)
10578 || !(bfd_link_pie (info)
10579 || SYMBOLIC_BIND (info, h))
10580 || !h->def_regular))
10581 outrel.r_info = ELF32_R_INFO (h->dynindx, r_type);
10582 else
10583 {
10584 int symbol;
10585
10586 /* This symbol is local, or marked to become local. */
10587 BFD_ASSERT (r_type == R_ARM_ABS32 || r_type == R_ARM_ABS32_NOI
10588 || (globals->fdpic_p && !bfd_link_pic (info)));
10589 /* On SVR4-ish systems, the dynamic loader cannot
10590 relocate the text and data segments independently,
10591 so the symbol does not matter. */
10592 symbol = 0;
10593 if (dynreloc_st_type == STT_GNU_IFUNC)
10594 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10595 to the .iplt entry. Instead, every non-call reference
10596 must use an R_ARM_IRELATIVE relocation to obtain the
10597 correct run-time address. */
10598 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_IRELATIVE);
10599 else if (globals->fdpic_p && !bfd_link_pic (info))
10600 isrofixup = 1;
10601 else
10602 outrel.r_info = ELF32_R_INFO (symbol, R_ARM_RELATIVE);
10603 if (globals->use_rel)
10604 relocate = true;
10605 else
10606 outrel.r_addend += dynreloc_value;
10607 }
10608
10609 if (isrofixup)
10610 arm_elf_add_rofixup (output_bfd, globals->srofixup, outrel.r_offset);
10611 else
10612 elf32_arm_add_dynreloc (output_bfd, info, sreloc, &outrel);
10613
10614 /* If this reloc is against an external symbol, we do not want to
10615 fiddle with the addend. Otherwise, we need to include the symbol
10616 value so that it becomes an addend for the dynamic reloc. */
10617 if (! relocate)
10618 return bfd_reloc_ok;
10619
10620 return _bfd_final_link_relocate (howto, input_bfd, input_section,
10621 contents, rel->r_offset,
10622 dynreloc_value, (bfd_vma) 0);
10623 }
10624 else switch (r_type)
10625 {
10626 case R_ARM_ABS12:
10627 return elf32_arm_abs12_reloc (input_bfd, hit_data, value + addend);
10628
10629 case R_ARM_XPC25: /* Arm BLX instruction. */
10630 case R_ARM_CALL:
10631 case R_ARM_JUMP24:
10632 case R_ARM_PC24: /* Arm B/BL instruction. */
10633 case R_ARM_PLT32:
10634 {
10635 struct elf32_arm_stub_hash_entry *stub_entry = NULL;
10636
10637 if (r_type == R_ARM_XPC25)
10638 {
10639 /* Check for Arm calling Arm function. */
10640 /* FIXME: Should we translate the instruction into a BL
10641 instruction instead ? */
10642 if (branch_type != ST_BRANCH_TO_THUMB)
10643 _bfd_error_handler
10644 (_("\%pB: warning: %s BLX instruction targets"
10645 " %s function '%s'"),
10646 input_bfd, "ARM",
10647 "ARM", h ? h->root.root.string : "(local)");
10648 }
10649 else if (r_type == R_ARM_PC24)
10650 {
10651 /* Check for Arm calling Thumb function. */
10652 if (branch_type == ST_BRANCH_TO_THUMB)
10653 {
10654 if (elf32_arm_to_thumb_stub (info, sym_name, input_bfd,
10655 output_bfd, input_section,
10656 hit_data, sym_sec, rel->r_offset,
10657 signed_addend, value,
10658 error_message))
10659 return bfd_reloc_ok;
10660 else
10661 return bfd_reloc_dangerous;
10662 }
10663 }
10664
10665 /* Check if a stub has to be inserted because the
10666 destination is too far or we are changing mode. */
10667 if ( r_type == R_ARM_CALL
10668 || r_type == R_ARM_JUMP24
10669 || r_type == R_ARM_PLT32)
10670 {
10671 enum elf32_arm_stub_type stub_type = arm_stub_none;
10672 struct elf32_arm_link_hash_entry *hash;
10673
10674 hash = (struct elf32_arm_link_hash_entry *) h;
10675 stub_type = arm_type_of_stub (info, input_section, rel,
10676 st_type, &branch_type,
10677 hash, value, sym_sec,
10678 input_bfd, sym_name);
10679
10680 if (stub_type != arm_stub_none)
10681 {
10682 /* The target is out of reach, so redirect the
10683 branch to the local stub for this function. */
10684 stub_entry = elf32_arm_get_stub_entry (input_section,
10685 sym_sec, h,
10686 rel, globals,
10687 stub_type);
10688 {
10689 if (stub_entry != NULL)
10690 value = (stub_entry->stub_offset
10691 + stub_entry->stub_sec->output_offset
10692 + stub_entry->stub_sec->output_section->vma);
10693
10694 if (plt_offset != (bfd_vma) -1)
10695 *unresolved_reloc_p = false;
10696 }
10697 }
10698 else
10699 {
10700 /* If the call goes through a PLT entry, make sure to
10701 check distance to the right destination address. */
10702 if (plt_offset != (bfd_vma) -1)
10703 {
10704 value = (splt->output_section->vma
10705 + splt->output_offset
10706 + plt_offset);
10707 *unresolved_reloc_p = false;
10708 /* The PLT entry is in ARM mode, regardless of the
10709 target function. */
10710 branch_type = ST_BRANCH_TO_ARM;
10711 }
10712 }
10713 }
10714
10715 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10716 where:
10717 S is the address of the symbol in the relocation.
10718 P is address of the instruction being relocated.
10719 A is the addend (extracted from the instruction) in bytes.
10720
10721 S is held in 'value'.
10722 P is the base address of the section containing the
10723 instruction plus the offset of the reloc into that
10724 section, ie:
10725 (input_section->output_section->vma +
10726 input_section->output_offset +
10727 rel->r_offset).
10728 A is the addend, converted into bytes, ie:
10729 (signed_addend * 4)
10730
10731 Note: None of these operations have knowledge of the pipeline
10732 size of the processor, thus it is up to the assembler to
10733 encode this information into the addend. */
10734 value -= (input_section->output_section->vma
10735 + input_section->output_offset);
10736 value -= rel->r_offset;
10737 value += signed_addend;
10738
10739 signed_addend = value;
10740 signed_addend >>= howto->rightshift;
10741
10742 /* A branch to an undefined weak symbol is turned into a jump to
10743 the next instruction unless a PLT entry will be created.
10744 Do the same for local undefined symbols (but not for STN_UNDEF).
10745 The jump to the next instruction is optimized as a NOP depending
10746 on the architecture. */
10747 if (h ? (h->root.type == bfd_link_hash_undefweak
10748 && plt_offset == (bfd_vma) -1)
10749 : r_symndx != STN_UNDEF && bfd_is_und_section (sym_sec))
10750 {
10751 value = (bfd_get_32 (input_bfd, hit_data) & 0xf0000000);
10752
10753 if (arch_has_arm_nop (globals))
10754 value |= 0x0320f000;
10755 else
10756 value |= 0x01a00000; /* Using pre-UAL nop: mov r0, r0. */
10757 }
10758 else
10759 {
10760 /* Perform a signed range check. */
10761 if ( signed_addend > ((bfd_signed_vma) (howto->dst_mask >> 1))
10762 || signed_addend < - ((bfd_signed_vma) ((howto->dst_mask + 1) >> 1)))
10763 return bfd_reloc_overflow;
10764
10765 addend = (value & 2);
10766
10767 value = (signed_addend & howto->dst_mask)
10768 | (bfd_get_32 (input_bfd, hit_data) & (~ howto->dst_mask));
10769
10770 if (r_type == R_ARM_CALL)
10771 {
10772 /* Set the H bit in the BLX instruction. */
10773 if (branch_type == ST_BRANCH_TO_THUMB)
10774 {
10775 if (addend)
10776 value |= (1 << 24);
10777 else
10778 value &= ~(bfd_vma)(1 << 24);
10779 }
10780
10781 /* Select the correct instruction (BL or BLX). */
10782 /* Only if we are not handling a BL to a stub. In this
10783 case, mode switching is performed by the stub. */
10784 if (branch_type == ST_BRANCH_TO_THUMB && !stub_entry)
10785 value |= (1 << 28);
10786 else if (stub_entry || branch_type != ST_BRANCH_UNKNOWN)
10787 {
10788 value &= ~(bfd_vma)(1 << 28);
10789 value |= (1 << 24);
10790 }
10791 }
10792 }
10793 }
10794 break;
10795
10796 case R_ARM_ABS32:
10797 value += addend;
10798 if (branch_type == ST_BRANCH_TO_THUMB)
10799 value |= 1;
10800 break;
10801
10802 case R_ARM_ABS32_NOI:
10803 value += addend;
10804 break;
10805
10806 case R_ARM_REL32:
10807 value += addend;
10808 if (branch_type == ST_BRANCH_TO_THUMB)
10809 value |= 1;
10810 value -= (input_section->output_section->vma
10811 + input_section->output_offset + rel->r_offset);
10812 break;
10813
10814 case R_ARM_REL32_NOI:
10815 value += addend;
10816 value -= (input_section->output_section->vma
10817 + input_section->output_offset + rel->r_offset);
10818 break;
10819
10820 case R_ARM_PREL31:
10821 value -= (input_section->output_section->vma
10822 + input_section->output_offset + rel->r_offset);
10823 value += signed_addend;
10824 if (! h || h->root.type != bfd_link_hash_undefweak)
10825 {
10826 /* Check for overflow. */
10827 if ((value ^ (value >> 1)) & (1 << 30))
10828 return bfd_reloc_overflow;
10829 }
10830 value &= 0x7fffffff;
10831 value |= (bfd_get_32 (input_bfd, hit_data) & 0x80000000);
10832 if (branch_type == ST_BRANCH_TO_THUMB)
10833 value |= 1;
10834 break;
10835 }
10836
10837 bfd_put_32 (input_bfd, value, hit_data);
10838 return bfd_reloc_ok;
10839
10840 case R_ARM_ABS8:
10841 value += addend;
10842
10843 /* There is no way to tell whether the user intended to use a signed or
10844 unsigned addend. When checking for overflow we accept either,
10845 as specified by the AAELF. */
10846 if ((long) value > 0xff || (long) value < -0x80)
10847 return bfd_reloc_overflow;
10848
10849 bfd_put_8 (input_bfd, value, hit_data);
10850 return bfd_reloc_ok;
10851
10852 case R_ARM_ABS16:
10853 value += addend;
10854
10855 /* See comment for R_ARM_ABS8. */
10856 if ((long) value > 0xffff || (long) value < -0x8000)
10857 return bfd_reloc_overflow;
10858
10859 bfd_put_16 (input_bfd, value, hit_data);
10860 return bfd_reloc_ok;
10861
10862 case R_ARM_THM_ABS5:
10863 /* Support ldr and str instructions for the thumb. */
10864 if (globals->use_rel)
10865 {
10866 /* Need to refetch addend. */
10867 addend = bfd_get_16 (input_bfd, hit_data) & howto->src_mask;
10868 /* ??? Need to determine shift amount from operand size. */
10869 addend >>= howto->rightshift;
10870 }
10871 value += addend;
10872
10873 /* ??? Isn't value unsigned? */
10874 if ((long) value > 0x1f || (long) value < -0x10)
10875 return bfd_reloc_overflow;
10876
10877 /* ??? Value needs to be properly shifted into place first. */
10878 value |= bfd_get_16 (input_bfd, hit_data) & 0xf83f;
10879 bfd_put_16 (input_bfd, value, hit_data);
10880 return bfd_reloc_ok;
10881
10882 case R_ARM_THM_ALU_PREL_11_0:
10883 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10884 {
10885 bfd_vma insn;
10886 bfd_signed_vma relocation;
10887
10888 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
10889 | bfd_get_16 (input_bfd, hit_data + 2);
10890
10891 if (globals->use_rel)
10892 {
10893 signed_addend = (insn & 0xff) | ((insn & 0x7000) >> 4)
10894 | ((insn & (1 << 26)) >> 15);
10895 if (insn & 0xf00000)
10896 signed_addend = -signed_addend;
10897 }
10898
10899 relocation = value + signed_addend;
10900 relocation -= Pa (input_section->output_section->vma
10901 + input_section->output_offset
10902 + rel->r_offset);
10903
10904 /* PR 21523: Use an absolute value. The user of this reloc will
10905 have already selected an ADD or SUB insn appropriately. */
10906 value = llabs (relocation);
10907
10908 if (value >= 0x1000)
10909 return bfd_reloc_overflow;
10910
10911 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10912 if (branch_type == ST_BRANCH_TO_THUMB)
10913 value |= 1;
10914
10915 insn = (insn & 0xfb0f8f00) | (value & 0xff)
10916 | ((value & 0x700) << 4)
10917 | ((value & 0x800) << 15);
10918 if (relocation < 0)
10919 insn |= 0xa00000;
10920
10921 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10922 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10923
10924 return bfd_reloc_ok;
10925 }
10926
10927 case R_ARM_THM_PC8:
10928 /* PR 10073: This reloc is not generated by the GNU toolchain,
10929 but it is supported for compatibility with third party libraries
10930 generated by other compilers, specifically the ARM/IAR. */
10931 {
10932 bfd_vma insn;
10933 bfd_signed_vma relocation;
10934
10935 insn = bfd_get_16 (input_bfd, hit_data);
10936
10937 if (globals->use_rel)
10938 addend = ((((insn & 0x00ff) << 2) + 4) & 0x3ff) -4;
10939
10940 relocation = value + addend;
10941 relocation -= Pa (input_section->output_section->vma
10942 + input_section->output_offset
10943 + rel->r_offset);
10944
10945 value = relocation;
10946
10947 /* We do not check for overflow of this reloc. Although strictly
10948 speaking this is incorrect, it appears to be necessary in order
10949 to work with IAR generated relocs. Since GCC and GAS do not
10950 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10951 a problem for them. */
10952 value &= 0x3fc;
10953
10954 insn = (insn & 0xff00) | (value >> 2);
10955
10956 bfd_put_16 (input_bfd, insn, hit_data);
10957
10958 return bfd_reloc_ok;
10959 }
10960
10961 case R_ARM_THM_PC12:
10962 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10963 {
10964 bfd_vma insn;
10965 bfd_signed_vma relocation;
10966
10967 insn = (bfd_get_16 (input_bfd, hit_data) << 16)
10968 | bfd_get_16 (input_bfd, hit_data + 2);
10969
10970 if (globals->use_rel)
10971 {
10972 signed_addend = insn & 0xfff;
10973 if (!(insn & (1 << 23)))
10974 signed_addend = -signed_addend;
10975 }
10976
10977 relocation = value + signed_addend;
10978 relocation -= Pa (input_section->output_section->vma
10979 + input_section->output_offset
10980 + rel->r_offset);
10981
10982 value = relocation;
10983
10984 if (value >= 0x1000)
10985 return bfd_reloc_overflow;
10986
10987 insn = (insn & 0xff7ff000) | value;
10988 if (relocation >= 0)
10989 insn |= (1 << 23);
10990
10991 bfd_put_16 (input_bfd, insn >> 16, hit_data);
10992 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
10993
10994 return bfd_reloc_ok;
10995 }
10996
10997 case R_ARM_THM_XPC22:
10998 case R_ARM_THM_CALL:
10999 case R_ARM_THM_JUMP24:
11000 /* Thumb BL (branch long instruction). */
11001 {
11002 bfd_vma relocation;
11003 bfd_vma reloc_sign;
11004 bool overflow = false;
11005 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11006 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
11007 bfd_signed_vma reloc_signed_max;
11008 bfd_signed_vma reloc_signed_min;
11009 bfd_vma check;
11010 bfd_signed_vma signed_check;
11011 int bitsize;
11012 const int thumb2 = using_thumb2 (globals);
11013 const int thumb2_bl = using_thumb2_bl (globals);
11014
11015 /* A branch to an undefined weak symbol is turned into a jump to
11016 the next instruction unless a PLT entry will be created.
11017 The jump to the next instruction is optimized as a NOP.W for
11018 Thumb-2 enabled architectures. */
11019 if (h && h->root.type == bfd_link_hash_undefweak
11020 && plt_offset == (bfd_vma) -1)
11021 {
11022 if (thumb2)
11023 {
11024 bfd_put_16 (input_bfd, 0xf3af, hit_data);
11025 bfd_put_16 (input_bfd, 0x8000, hit_data + 2);
11026 }
11027 else
11028 {
11029 bfd_put_16 (input_bfd, 0xe000, hit_data);
11030 bfd_put_16 (input_bfd, 0xbf00, hit_data + 2);
11031 }
11032 return bfd_reloc_ok;
11033 }
11034
11035 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
11036 with Thumb-1) involving the J1 and J2 bits. */
11037 if (globals->use_rel)
11038 {
11039 bfd_vma s = (upper_insn & (1 << 10)) >> 10;
11040 bfd_vma upper = upper_insn & 0x3ff;
11041 bfd_vma lower = lower_insn & 0x7ff;
11042 bfd_vma j1 = (lower_insn & (1 << 13)) >> 13;
11043 bfd_vma j2 = (lower_insn & (1 << 11)) >> 11;
11044 bfd_vma i1 = j1 ^ s ? 0 : 1;
11045 bfd_vma i2 = j2 ^ s ? 0 : 1;
11046
11047 addend = (i1 << 23) | (i2 << 22) | (upper << 12) | (lower << 1);
11048 /* Sign extend. */
11049 addend = (addend | ((s ? 0 : 1) << 24)) - (1 << 24);
11050
11051 signed_addend = addend;
11052 }
11053
11054 if (r_type == R_ARM_THM_XPC22)
11055 {
11056 /* Check for Thumb to Thumb call. */
11057 /* FIXME: Should we translate the instruction into a BL
11058 instruction instead ? */
11059 if (branch_type == ST_BRANCH_TO_THUMB)
11060 _bfd_error_handler
11061 (_("%pB: warning: %s BLX instruction targets"
11062 " %s function '%s'"),
11063 input_bfd, "Thumb",
11064 "Thumb", h ? h->root.root.string : "(local)");
11065 }
11066 else
11067 {
11068 /* If it is not a call to Thumb, assume call to Arm.
11069 If it is a call relative to a section name, then it is not a
11070 function call at all, but rather a long jump. Calls through
11071 the PLT do not require stubs. */
11072 if (branch_type == ST_BRANCH_TO_ARM && plt_offset == (bfd_vma) -1)
11073 {
11074 if (globals->use_blx && r_type == R_ARM_THM_CALL)
11075 {
11076 /* Convert BL to BLX. */
11077 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11078 }
11079 else if (( r_type != R_ARM_THM_CALL)
11080 && (r_type != R_ARM_THM_JUMP24))
11081 {
11082 if (elf32_thumb_to_arm_stub
11083 (info, sym_name, input_bfd, output_bfd, input_section,
11084 hit_data, sym_sec, rel->r_offset, signed_addend, value,
11085 error_message))
11086 return bfd_reloc_ok;
11087 else
11088 return bfd_reloc_dangerous;
11089 }
11090 }
11091 else if (branch_type == ST_BRANCH_TO_THUMB
11092 && globals->use_blx
11093 && r_type == R_ARM_THM_CALL)
11094 {
11095 /* Make sure this is a BL. */
11096 lower_insn |= 0x1800;
11097 }
11098 }
11099
11100 enum elf32_arm_stub_type stub_type = arm_stub_none;
11101 if (r_type == R_ARM_THM_CALL || r_type == R_ARM_THM_JUMP24)
11102 {
11103 /* Check if a stub has to be inserted because the destination
11104 is too far. */
11105 struct elf32_arm_stub_hash_entry *stub_entry;
11106 struct elf32_arm_link_hash_entry *hash;
11107
11108 hash = (struct elf32_arm_link_hash_entry *) h;
11109
11110 stub_type = arm_type_of_stub (info, input_section, rel,
11111 st_type, &branch_type,
11112 hash, value, sym_sec,
11113 input_bfd, sym_name);
11114
11115 if (stub_type != arm_stub_none)
11116 {
11117 /* The target is out of reach or we are changing modes, so
11118 redirect the branch to the local stub for this
11119 function. */
11120 stub_entry = elf32_arm_get_stub_entry (input_section,
11121 sym_sec, h,
11122 rel, globals,
11123 stub_type);
11124 if (stub_entry != NULL)
11125 {
11126 value = (stub_entry->stub_offset
11127 + stub_entry->stub_sec->output_offset
11128 + stub_entry->stub_sec->output_section->vma);
11129
11130 if (plt_offset != (bfd_vma) -1)
11131 *unresolved_reloc_p = false;
11132 }
11133
11134 /* If this call becomes a call to Arm, force BLX. */
11135 if (globals->use_blx && (r_type == R_ARM_THM_CALL))
11136 {
11137 if ((stub_entry
11138 && !arm_stub_is_thumb (stub_entry->stub_type))
11139 || branch_type != ST_BRANCH_TO_THUMB)
11140 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11141 }
11142 }
11143 }
11144
11145 /* Handle calls via the PLT. */
11146 if (stub_type == arm_stub_none && plt_offset != (bfd_vma) -1)
11147 {
11148 value = (splt->output_section->vma
11149 + splt->output_offset
11150 + plt_offset);
11151
11152 if (globals->use_blx
11153 && r_type == R_ARM_THM_CALL
11154 && ! using_thumb_only (globals))
11155 {
11156 /* If the Thumb BLX instruction is available, convert
11157 the BL to a BLX instruction to call the ARM-mode
11158 PLT entry. */
11159 lower_insn = (lower_insn & ~0x1000) | 0x0800;
11160 branch_type = ST_BRANCH_TO_ARM;
11161 }
11162 else
11163 {
11164 if (! using_thumb_only (globals))
11165 /* Target the Thumb stub before the ARM PLT entry. */
11166 value -= PLT_THUMB_STUB_SIZE;
11167 branch_type = ST_BRANCH_TO_THUMB;
11168 }
11169 *unresolved_reloc_p = false;
11170 }
11171
11172 relocation = value + signed_addend;
11173
11174 relocation -= (input_section->output_section->vma
11175 + input_section->output_offset
11176 + rel->r_offset);
11177
11178 check = relocation >> howto->rightshift;
11179
11180 /* If this is a signed value, the rightshift just dropped
11181 leading 1 bits (assuming twos complement). */
11182 if ((bfd_signed_vma) relocation >= 0)
11183 signed_check = check;
11184 else
11185 signed_check = check | ~((bfd_vma) -1 >> howto->rightshift);
11186
11187 /* Calculate the permissable maximum and minimum values for
11188 this relocation according to whether we're relocating for
11189 Thumb-2 or not. */
11190 bitsize = howto->bitsize;
11191 if (!thumb2_bl)
11192 bitsize -= 2;
11193 reloc_signed_max = (1 << (bitsize - 1)) - 1;
11194 reloc_signed_min = ~reloc_signed_max;
11195
11196 /* Assumes two's complement. */
11197 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11198 overflow = true;
11199
11200 if ((lower_insn & 0x5000) == 0x4000)
11201 /* For a BLX instruction, make sure that the relocation is rounded up
11202 to a word boundary. This follows the semantics of the instruction
11203 which specifies that bit 1 of the target address will come from bit
11204 1 of the base address. */
11205 relocation = (relocation + 2) & ~ 3;
11206
11207 /* Put RELOCATION back into the insn. Assumes two's complement.
11208 We use the Thumb-2 encoding, which is safe even if dealing with
11209 a Thumb-1 instruction by virtue of our overflow check above. */
11210 reloc_sign = (signed_check < 0) ? 1 : 0;
11211 upper_insn = (upper_insn & ~(bfd_vma) 0x7ff)
11212 | ((relocation >> 12) & 0x3ff)
11213 | (reloc_sign << 10);
11214 lower_insn = (lower_insn & ~(bfd_vma) 0x2fff)
11215 | (((!((relocation >> 23) & 1)) ^ reloc_sign) << 13)
11216 | (((!((relocation >> 22) & 1)) ^ reloc_sign) << 11)
11217 | ((relocation >> 1) & 0x7ff);
11218
11219 /* Put the relocated value back in the object file: */
11220 bfd_put_16 (input_bfd, upper_insn, hit_data);
11221 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11222
11223 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11224 }
11225 break;
11226
11227 case R_ARM_THM_JUMP19:
11228 /* Thumb32 conditional branch instruction. */
11229 {
11230 bfd_vma relocation;
11231 bool overflow = false;
11232 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
11233 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
11234 bfd_signed_vma reloc_signed_max = 0xffffe;
11235 bfd_signed_vma reloc_signed_min = -0x100000;
11236 bfd_signed_vma signed_check;
11237 enum elf32_arm_stub_type stub_type = arm_stub_none;
11238 struct elf32_arm_stub_hash_entry *stub_entry;
11239 struct elf32_arm_link_hash_entry *hash;
11240
11241 /* Need to refetch the addend, reconstruct the top three bits,
11242 and squish the two 11 bit pieces together. */
11243 if (globals->use_rel)
11244 {
11245 bfd_vma S = (upper_insn & 0x0400) >> 10;
11246 bfd_vma upper = (upper_insn & 0x003f);
11247 bfd_vma J1 = (lower_insn & 0x2000) >> 13;
11248 bfd_vma J2 = (lower_insn & 0x0800) >> 11;
11249 bfd_vma lower = (lower_insn & 0x07ff);
11250
11251 upper |= J1 << 6;
11252 upper |= J2 << 7;
11253 upper |= (!S) << 8;
11254 upper -= 0x0100; /* Sign extend. */
11255
11256 addend = (upper << 12) | (lower << 1);
11257 signed_addend = addend;
11258 }
11259
11260 /* Handle calls via the PLT. */
11261 if (plt_offset != (bfd_vma) -1)
11262 {
11263 value = (splt->output_section->vma
11264 + splt->output_offset
11265 + plt_offset);
11266 /* Target the Thumb stub before the ARM PLT entry. */
11267 value -= PLT_THUMB_STUB_SIZE;
11268 *unresolved_reloc_p = false;
11269 }
11270
11271 hash = (struct elf32_arm_link_hash_entry *)h;
11272
11273 stub_type = arm_type_of_stub (info, input_section, rel,
11274 st_type, &branch_type,
11275 hash, value, sym_sec,
11276 input_bfd, sym_name);
11277 if (stub_type != arm_stub_none)
11278 {
11279 stub_entry = elf32_arm_get_stub_entry (input_section,
11280 sym_sec, h,
11281 rel, globals,
11282 stub_type);
11283 if (stub_entry != NULL)
11284 {
11285 value = (stub_entry->stub_offset
11286 + stub_entry->stub_sec->output_offset
11287 + stub_entry->stub_sec->output_section->vma);
11288 }
11289 }
11290
11291 relocation = value + signed_addend;
11292 relocation -= (input_section->output_section->vma
11293 + input_section->output_offset
11294 + rel->r_offset);
11295 signed_check = (bfd_signed_vma) relocation;
11296
11297 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11298 overflow = true;
11299
11300 /* Put RELOCATION back into the insn. */
11301 {
11302 bfd_vma S = (relocation & 0x00100000) >> 20;
11303 bfd_vma J2 = (relocation & 0x00080000) >> 19;
11304 bfd_vma J1 = (relocation & 0x00040000) >> 18;
11305 bfd_vma hi = (relocation & 0x0003f000) >> 12;
11306 bfd_vma lo = (relocation & 0x00000ffe) >> 1;
11307
11308 upper_insn = (upper_insn & 0xfbc0) | (S << 10) | hi;
11309 lower_insn = (lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | lo;
11310 }
11311
11312 /* Put the relocated value back in the object file: */
11313 bfd_put_16 (input_bfd, upper_insn, hit_data);
11314 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11315
11316 return (overflow ? bfd_reloc_overflow : bfd_reloc_ok);
11317 }
11318
11319 case R_ARM_THM_JUMP11:
11320 case R_ARM_THM_JUMP8:
11321 case R_ARM_THM_JUMP6:
11322 /* Thumb B (branch) instruction). */
11323 {
11324 bfd_signed_vma relocation;
11325 bfd_signed_vma reloc_signed_max = (1 << (howto->bitsize - 1)) - 1;
11326 bfd_signed_vma reloc_signed_min = ~ reloc_signed_max;
11327 bfd_signed_vma signed_check;
11328
11329 /* CZB cannot jump backward. */
11330 if (r_type == R_ARM_THM_JUMP6)
11331 {
11332 reloc_signed_min = 0;
11333 if (globals->use_rel)
11334 signed_addend = ((addend & 0x200) >> 3) | ((addend & 0xf8) >> 2);
11335 }
11336
11337 relocation = value + signed_addend;
11338
11339 relocation -= (input_section->output_section->vma
11340 + input_section->output_offset
11341 + rel->r_offset);
11342
11343 relocation >>= howto->rightshift;
11344 signed_check = relocation;
11345
11346 if (r_type == R_ARM_THM_JUMP6)
11347 relocation = ((relocation & 0x0020) << 4) | ((relocation & 0x001f) << 3);
11348 else
11349 relocation &= howto->dst_mask;
11350 relocation |= (bfd_get_16 (input_bfd, hit_data) & (~ howto->dst_mask));
11351
11352 bfd_put_16 (input_bfd, relocation, hit_data);
11353
11354 /* Assumes two's complement. */
11355 if (signed_check > reloc_signed_max || signed_check < reloc_signed_min)
11356 return bfd_reloc_overflow;
11357
11358 return bfd_reloc_ok;
11359 }
11360
11361 case R_ARM_ALU_PCREL7_0:
11362 case R_ARM_ALU_PCREL15_8:
11363 case R_ARM_ALU_PCREL23_15:
11364 {
11365 bfd_vma insn;
11366 bfd_vma relocation;
11367
11368 insn = bfd_get_32 (input_bfd, hit_data);
11369 if (globals->use_rel)
11370 {
11371 /* Extract the addend. */
11372 addend = (insn & 0xff) << ((insn & 0xf00) >> 7);
11373 signed_addend = addend;
11374 }
11375 relocation = value + signed_addend;
11376
11377 relocation -= (input_section->output_section->vma
11378 + input_section->output_offset
11379 + rel->r_offset);
11380 insn = (insn & ~0xfff)
11381 | ((howto->bitpos << 7) & 0xf00)
11382 | ((relocation >> howto->bitpos) & 0xff);
11383 bfd_put_32 (input_bfd, value, hit_data);
11384 }
11385 return bfd_reloc_ok;
11386
11387 case R_ARM_GNU_VTINHERIT:
11388 case R_ARM_GNU_VTENTRY:
11389 return bfd_reloc_ok;
11390
11391 case R_ARM_GOTOFF32:
11392 /* Relocation is relative to the start of the
11393 global offset table. */
11394
11395 BFD_ASSERT (sgot != NULL);
11396 if (sgot == NULL)
11397 return bfd_reloc_notsupported;
11398
11399 /* If we are addressing a Thumb function, we need to adjust the
11400 address by one, so that attempts to call the function pointer will
11401 correctly interpret it as Thumb code. */
11402 if (branch_type == ST_BRANCH_TO_THUMB)
11403 value += 1;
11404
11405 /* Note that sgot->output_offset is not involved in this
11406 calculation. We always want the start of .got. If we
11407 define _GLOBAL_OFFSET_TABLE in a different way, as is
11408 permitted by the ABI, we might have to change this
11409 calculation. */
11410 value -= sgot->output_section->vma;
11411 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11412 contents, rel->r_offset, value,
11413 rel->r_addend);
11414
11415 case R_ARM_GOTPC:
11416 /* Use global offset table as symbol value. */
11417 BFD_ASSERT (sgot != NULL);
11418
11419 if (sgot == NULL)
11420 return bfd_reloc_notsupported;
11421
11422 *unresolved_reloc_p = false;
11423 value = sgot->output_section->vma;
11424 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11425 contents, rel->r_offset, value,
11426 rel->r_addend);
11427
11428 case R_ARM_GOT32:
11429 case R_ARM_GOT_PREL:
11430 /* Relocation is to the entry for this symbol in the
11431 global offset table. */
11432 if (sgot == NULL)
11433 return bfd_reloc_notsupported;
11434
11435 if (dynreloc_st_type == STT_GNU_IFUNC
11436 && plt_offset != (bfd_vma) -1
11437 && (h == NULL || SYMBOL_REFERENCES_LOCAL (info, h)))
11438 {
11439 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11440 symbol, and the relocation resolves directly to the runtime
11441 target rather than to the .iplt entry. This means that any
11442 .got entry would be the same value as the .igot.plt entry,
11443 so there's no point creating both. */
11444 sgot = globals->root.igotplt;
11445 value = sgot->output_offset + gotplt_offset;
11446 }
11447 else if (h != NULL)
11448 {
11449 bfd_vma off;
11450
11451 off = h->got.offset;
11452 BFD_ASSERT (off != (bfd_vma) -1);
11453 if ((off & 1) != 0)
11454 {
11455 /* We have already processsed one GOT relocation against
11456 this symbol. */
11457 off &= ~1;
11458 if (globals->root.dynamic_sections_created
11459 && !SYMBOL_REFERENCES_LOCAL (info, h))
11460 *unresolved_reloc_p = false;
11461 }
11462 else
11463 {
11464 Elf_Internal_Rela outrel;
11465 int isrofixup = 0;
11466
11467 if (((h->dynindx != -1) || globals->fdpic_p)
11468 && !SYMBOL_REFERENCES_LOCAL (info, h))
11469 {
11470 /* If the symbol doesn't resolve locally in a static
11471 object, we have an undefined reference. If the
11472 symbol doesn't resolve locally in a dynamic object,
11473 it should be resolved by the dynamic linker. */
11474 if (globals->root.dynamic_sections_created)
11475 {
11476 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_GLOB_DAT);
11477 *unresolved_reloc_p = false;
11478 }
11479 else
11480 outrel.r_info = 0;
11481 outrel.r_addend = 0;
11482 }
11483 else
11484 {
11485 if (dynreloc_st_type == STT_GNU_IFUNC)
11486 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11487 else if (bfd_link_pic (info)
11488 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
11489 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11490 else
11491 {
11492 outrel.r_info = 0;
11493 if (globals->fdpic_p)
11494 isrofixup = 1;
11495 }
11496 outrel.r_addend = dynreloc_value;
11497 }
11498
11499 /* The GOT entry is initialized to zero by default.
11500 See if we should install a different value. */
11501 if (outrel.r_addend != 0
11502 && (globals->use_rel || outrel.r_info == 0))
11503 {
11504 bfd_put_32 (output_bfd, outrel.r_addend,
11505 sgot->contents + off);
11506 outrel.r_addend = 0;
11507 }
11508
11509 if (isrofixup)
11510 arm_elf_add_rofixup (output_bfd,
11511 elf32_arm_hash_table (info)->srofixup,
11512 sgot->output_section->vma
11513 + sgot->output_offset + off);
11514
11515 else if (outrel.r_info != 0)
11516 {
11517 outrel.r_offset = (sgot->output_section->vma
11518 + sgot->output_offset
11519 + off);
11520 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11521 }
11522
11523 h->got.offset |= 1;
11524 }
11525 value = sgot->output_offset + off;
11526 }
11527 else
11528 {
11529 bfd_vma off;
11530
11531 BFD_ASSERT (local_got_offsets != NULL
11532 && local_got_offsets[r_symndx] != (bfd_vma) -1);
11533
11534 off = local_got_offsets[r_symndx];
11535
11536 /* The offset must always be a multiple of 4. We use the
11537 least significant bit to record whether we have already
11538 generated the necessary reloc. */
11539 if ((off & 1) != 0)
11540 off &= ~1;
11541 else
11542 {
11543 Elf_Internal_Rela outrel;
11544 int isrofixup = 0;
11545
11546 if (dynreloc_st_type == STT_GNU_IFUNC)
11547 outrel.r_info = ELF32_R_INFO (0, R_ARM_IRELATIVE);
11548 else if (bfd_link_pic (info))
11549 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
11550 else
11551 {
11552 outrel.r_info = 0;
11553 if (globals->fdpic_p)
11554 isrofixup = 1;
11555 }
11556
11557 /* The GOT entry is initialized to zero by default.
11558 See if we should install a different value. */
11559 if (globals->use_rel || outrel.r_info == 0)
11560 bfd_put_32 (output_bfd, dynreloc_value, sgot->contents + off);
11561
11562 if (isrofixup)
11563 arm_elf_add_rofixup (output_bfd,
11564 globals->srofixup,
11565 sgot->output_section->vma
11566 + sgot->output_offset + off);
11567
11568 else if (outrel.r_info != 0)
11569 {
11570 outrel.r_addend = addend + dynreloc_value;
11571 outrel.r_offset = (sgot->output_section->vma
11572 + sgot->output_offset
11573 + off);
11574 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11575 }
11576
11577 local_got_offsets[r_symndx] |= 1;
11578 }
11579
11580 value = sgot->output_offset + off;
11581 }
11582 if (r_type != R_ARM_GOT32)
11583 value += sgot->output_section->vma;
11584
11585 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11586 contents, rel->r_offset, value,
11587 rel->r_addend);
11588
11589 case R_ARM_TLS_LDO32:
11590 value = value - dtpoff_base (info);
11591
11592 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11593 contents, rel->r_offset, value,
11594 rel->r_addend);
11595
11596 case R_ARM_TLS_LDM32:
11597 case R_ARM_TLS_LDM32_FDPIC:
11598 {
11599 bfd_vma off;
11600
11601 if (sgot == NULL)
11602 abort ();
11603
11604 off = globals->tls_ldm_got.offset;
11605
11606 if ((off & 1) != 0)
11607 off &= ~1;
11608 else
11609 {
11610 /* If we don't know the module number, create a relocation
11611 for it. */
11612 if (bfd_link_dll (info))
11613 {
11614 Elf_Internal_Rela outrel;
11615
11616 if (srelgot == NULL)
11617 abort ();
11618
11619 outrel.r_addend = 0;
11620 outrel.r_offset = (sgot->output_section->vma
11621 + sgot->output_offset + off);
11622 outrel.r_info = ELF32_R_INFO (0, R_ARM_TLS_DTPMOD32);
11623
11624 if (globals->use_rel)
11625 bfd_put_32 (output_bfd, outrel.r_addend,
11626 sgot->contents + off);
11627
11628 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11629 }
11630 else
11631 bfd_put_32 (output_bfd, 1, sgot->contents + off);
11632
11633 globals->tls_ldm_got.offset |= 1;
11634 }
11635
11636 if (r_type == R_ARM_TLS_LDM32_FDPIC)
11637 {
11638 bfd_put_32 (output_bfd,
11639 globals->root.sgot->output_offset + off,
11640 contents + rel->r_offset);
11641
11642 return bfd_reloc_ok;
11643 }
11644 else
11645 {
11646 value = sgot->output_section->vma + sgot->output_offset + off
11647 - (input_section->output_section->vma
11648 + input_section->output_offset + rel->r_offset);
11649
11650 return _bfd_final_link_relocate (howto, input_bfd, input_section,
11651 contents, rel->r_offset, value,
11652 rel->r_addend);
11653 }
11654 }
11655
11656 case R_ARM_TLS_CALL:
11657 case R_ARM_THM_TLS_CALL:
11658 case R_ARM_TLS_GD32:
11659 case R_ARM_TLS_GD32_FDPIC:
11660 case R_ARM_TLS_IE32:
11661 case R_ARM_TLS_IE32_FDPIC:
11662 case R_ARM_TLS_GOTDESC:
11663 case R_ARM_TLS_DESCSEQ:
11664 case R_ARM_THM_TLS_DESCSEQ:
11665 {
11666 bfd_vma off, offplt;
11667 int indx = 0;
11668 char tls_type;
11669
11670 BFD_ASSERT (sgot != NULL);
11671
11672 if (h != NULL)
11673 {
11674 bool dyn;
11675 dyn = globals->root.dynamic_sections_created;
11676 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn,
11677 bfd_link_pic (info),
11678 h)
11679 && (!bfd_link_pic (info)
11680 || !SYMBOL_REFERENCES_LOCAL (info, h)))
11681 {
11682 *unresolved_reloc_p = false;
11683 indx = h->dynindx;
11684 }
11685 off = h->got.offset;
11686 offplt = elf32_arm_hash_entry (h)->tlsdesc_got;
11687 tls_type = ((struct elf32_arm_link_hash_entry *) h)->tls_type;
11688 }
11689 else
11690 {
11691 BFD_ASSERT (local_got_offsets != NULL);
11692
11693 if (r_symndx >= elf32_arm_num_entries (input_bfd))
11694 {
11695 _bfd_error_handler (_("\
11696 %pB: expected symbol index in range 0..%lu but found local symbol with index %lu"),
11697 input_bfd,
11698 (unsigned long) elf32_arm_num_entries (input_bfd),
11699 r_symndx);
11700 return false;
11701 }
11702 off = local_got_offsets[r_symndx];
11703 offplt = local_tlsdesc_gotents[r_symndx];
11704 tls_type = elf32_arm_local_got_tls_type (input_bfd)[r_symndx];
11705 }
11706
11707 /* Linker relaxations happens from one of the
11708 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
11709 if (ELF32_R_TYPE (rel->r_info) != r_type)
11710 tls_type = GOT_TLS_IE;
11711
11712 BFD_ASSERT (tls_type != GOT_UNKNOWN);
11713
11714 if ((off & 1) != 0)
11715 off &= ~1;
11716 else
11717 {
11718 bool need_relocs = false;
11719 Elf_Internal_Rela outrel;
11720 int cur_off = off;
11721
11722 /* The GOT entries have not been initialized yet. Do it
11723 now, and emit any relocations. If both an IE GOT and a
11724 GD GOT are necessary, we emit the GD first. */
11725
11726 if ((bfd_link_dll (info) || indx != 0)
11727 && (h == NULL
11728 || (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
11729 && !resolved_to_zero)
11730 || h->root.type != bfd_link_hash_undefweak))
11731 {
11732 need_relocs = true;
11733 BFD_ASSERT (srelgot != NULL);
11734 }
11735
11736 if (tls_type & GOT_TLS_GDESC)
11737 {
11738 bfd_byte *loc;
11739
11740 /* We should have relaxed, unless this is an undefined
11741 weak symbol. */
11742 BFD_ASSERT ((h && (h->root.type == bfd_link_hash_undefweak))
11743 || bfd_link_dll (info));
11744 BFD_ASSERT (globals->sgotplt_jump_table_size + offplt + 8
11745 <= globals->root.sgotplt->size);
11746
11747 outrel.r_addend = 0;
11748 outrel.r_offset = (globals->root.sgotplt->output_section->vma
11749 + globals->root.sgotplt->output_offset
11750 + offplt
11751 + globals->sgotplt_jump_table_size);
11752
11753 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DESC);
11754 sreloc = globals->root.srelplt;
11755 loc = sreloc->contents;
11756 loc += globals->next_tls_desc_index++ * RELOC_SIZE (globals);
11757 BFD_ASSERT (loc + RELOC_SIZE (globals)
11758 <= sreloc->contents + sreloc->size);
11759
11760 SWAP_RELOC_OUT (globals) (output_bfd, &outrel, loc);
11761
11762 /* For globals, the first word in the relocation gets
11763 the relocation index and the top bit set, or zero,
11764 if we're binding now. For locals, it gets the
11765 symbol's offset in the tls section. */
11766 bfd_put_32 (output_bfd,
11767 !h ? value - elf_hash_table (info)->tls_sec->vma
11768 : info->flags & DF_BIND_NOW ? 0
11769 : 0x80000000 | ELF32_R_SYM (outrel.r_info),
11770 globals->root.sgotplt->contents + offplt
11771 + globals->sgotplt_jump_table_size);
11772
11773 /* Second word in the relocation is always zero. */
11774 bfd_put_32 (output_bfd, 0,
11775 globals->root.sgotplt->contents + offplt
11776 + globals->sgotplt_jump_table_size + 4);
11777 }
11778 if (tls_type & GOT_TLS_GD)
11779 {
11780 if (need_relocs)
11781 {
11782 outrel.r_addend = 0;
11783 outrel.r_offset = (sgot->output_section->vma
11784 + sgot->output_offset
11785 + cur_off);
11786 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_DTPMOD32);
11787
11788 if (globals->use_rel)
11789 bfd_put_32 (output_bfd, outrel.r_addend,
11790 sgot->contents + cur_off);
11791
11792 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11793
11794 if (indx == 0)
11795 bfd_put_32 (output_bfd, value - dtpoff_base (info),
11796 sgot->contents + cur_off + 4);
11797 else
11798 {
11799 outrel.r_addend = 0;
11800 outrel.r_info = ELF32_R_INFO (indx,
11801 R_ARM_TLS_DTPOFF32);
11802 outrel.r_offset += 4;
11803
11804 if (globals->use_rel)
11805 bfd_put_32 (output_bfd, outrel.r_addend,
11806 sgot->contents + cur_off + 4);
11807
11808 elf32_arm_add_dynreloc (output_bfd, info,
11809 srelgot, &outrel);
11810 }
11811 }
11812 else
11813 {
11814 /* If we are not emitting relocations for a
11815 general dynamic reference, then we must be in a
11816 static link or an executable link with the
11817 symbol binding locally. Mark it as belonging
11818 to module 1, the executable. */
11819 bfd_put_32 (output_bfd, 1,
11820 sgot->contents + cur_off);
11821 bfd_put_32 (output_bfd, value - dtpoff_base (info),
11822 sgot->contents + cur_off + 4);
11823 }
11824
11825 cur_off += 8;
11826 }
11827
11828 if (tls_type & GOT_TLS_IE)
11829 {
11830 if (need_relocs)
11831 {
11832 if (indx == 0)
11833 outrel.r_addend = value - dtpoff_base (info);
11834 else
11835 outrel.r_addend = 0;
11836 outrel.r_offset = (sgot->output_section->vma
11837 + sgot->output_offset
11838 + cur_off);
11839 outrel.r_info = ELF32_R_INFO (indx, R_ARM_TLS_TPOFF32);
11840
11841 if (globals->use_rel)
11842 bfd_put_32 (output_bfd, outrel.r_addend,
11843 sgot->contents + cur_off);
11844
11845 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
11846 }
11847 else
11848 bfd_put_32 (output_bfd, tpoff (info, value),
11849 sgot->contents + cur_off);
11850 cur_off += 4;
11851 }
11852
11853 if (h != NULL)
11854 h->got.offset |= 1;
11855 else
11856 local_got_offsets[r_symndx] |= 1;
11857 }
11858
11859 if ((tls_type & GOT_TLS_GD) && r_type != R_ARM_TLS_GD32 && r_type != R_ARM_TLS_GD32_FDPIC)
11860 off += 8;
11861 else if (tls_type & GOT_TLS_GDESC)
11862 off = offplt;
11863
11864 if (ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL
11865 || ELF32_R_TYPE (rel->r_info) == R_ARM_THM_TLS_CALL)
11866 {
11867 bfd_signed_vma offset;
11868 /* TLS stubs are arm mode. The original symbol is a
11869 data object, so branch_type is bogus. */
11870 branch_type = ST_BRANCH_TO_ARM;
11871 enum elf32_arm_stub_type stub_type
11872 = arm_type_of_stub (info, input_section, rel,
11873 st_type, &branch_type,
11874 (struct elf32_arm_link_hash_entry *)h,
11875 globals->tls_trampoline, globals->root.splt,
11876 input_bfd, sym_name);
11877
11878 if (stub_type != arm_stub_none)
11879 {
11880 struct elf32_arm_stub_hash_entry *stub_entry
11881 = elf32_arm_get_stub_entry
11882 (input_section, globals->root.splt, 0, rel,
11883 globals, stub_type);
11884 offset = (stub_entry->stub_offset
11885 + stub_entry->stub_sec->output_offset
11886 + stub_entry->stub_sec->output_section->vma);
11887 }
11888 else
11889 offset = (globals->root.splt->output_section->vma
11890 + globals->root.splt->output_offset
11891 + globals->tls_trampoline);
11892
11893 if (ELF32_R_TYPE (rel->r_info) == R_ARM_TLS_CALL)
11894 {
11895 unsigned long inst;
11896
11897 offset -= (input_section->output_section->vma
11898 + input_section->output_offset
11899 + rel->r_offset + 8);
11900
11901 inst = offset >> 2;
11902 inst &= 0x00ffffff;
11903 value = inst | (globals->use_blx ? 0xfa000000 : 0xeb000000);
11904 }
11905 else
11906 {
11907 /* Thumb blx encodes the offset in a complicated
11908 fashion. */
11909 unsigned upper_insn, lower_insn;
11910 unsigned neg;
11911
11912 offset -= (input_section->output_section->vma
11913 + input_section->output_offset
11914 + rel->r_offset + 4);
11915
11916 if (stub_type != arm_stub_none
11917 && arm_stub_is_thumb (stub_type))
11918 {
11919 lower_insn = 0xd000;
11920 }
11921 else
11922 {
11923 lower_insn = 0xc000;
11924 /* Round up the offset to a word boundary. */
11925 offset = (offset + 2) & ~2;
11926 }
11927
11928 neg = offset < 0;
11929 upper_insn = (0xf000
11930 | ((offset >> 12) & 0x3ff)
11931 | (neg << 10));
11932 lower_insn |= (((!((offset >> 23) & 1)) ^ neg) << 13)
11933 | (((!((offset >> 22) & 1)) ^ neg) << 11)
11934 | ((offset >> 1) & 0x7ff);
11935 bfd_put_16 (input_bfd, upper_insn, hit_data);
11936 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
11937 return bfd_reloc_ok;
11938 }
11939 }
11940 /* These relocations needs special care, as besides the fact
11941 they point somewhere in .gotplt, the addend must be
11942 adjusted accordingly depending on the type of instruction
11943 we refer to. */
11944 else if ((r_type == R_ARM_TLS_GOTDESC) && (tls_type & GOT_TLS_GDESC))
11945 {
11946 unsigned long data, insn;
11947 unsigned thumb;
11948
11949 data = bfd_get_signed_32 (input_bfd, hit_data);
11950 thumb = data & 1;
11951 data &= ~1ul;
11952
11953 if (thumb)
11954 {
11955 insn = bfd_get_16 (input_bfd, contents + rel->r_offset - data);
11956 if ((insn & 0xf000) == 0xf000 || (insn & 0xf800) == 0xe800)
11957 insn = (insn << 16)
11958 | bfd_get_16 (input_bfd,
11959 contents + rel->r_offset - data + 2);
11960 if ((insn & 0xf800c000) == 0xf000c000)
11961 /* bl/blx */
11962 value = -6;
11963 else if ((insn & 0xffffff00) == 0x4400)
11964 /* add */
11965 value = -5;
11966 else
11967 {
11968 _bfd_error_handler
11969 /* xgettext:c-format */
11970 (_("%pB(%pA+%#" PRIx64 "): "
11971 "unexpected %s instruction '%#lx' "
11972 "referenced by TLS_GOTDESC"),
11973 input_bfd, input_section, (uint64_t) rel->r_offset,
11974 "Thumb", insn);
11975 return bfd_reloc_notsupported;
11976 }
11977 }
11978 else
11979 {
11980 insn = bfd_get_32 (input_bfd, contents + rel->r_offset - data);
11981
11982 switch (insn >> 24)
11983 {
11984 case 0xeb: /* bl */
11985 case 0xfa: /* blx */
11986 value = -4;
11987 break;
11988
11989 case 0xe0: /* add */
11990 value = -8;
11991 break;
11992
11993 default:
11994 _bfd_error_handler
11995 /* xgettext:c-format */
11996 (_("%pB(%pA+%#" PRIx64 "): "
11997 "unexpected %s instruction '%#lx' "
11998 "referenced by TLS_GOTDESC"),
11999 input_bfd, input_section, (uint64_t) rel->r_offset,
12000 "ARM", insn);
12001 return bfd_reloc_notsupported;
12002 }
12003 }
12004
12005 value += ((globals->root.sgotplt->output_section->vma
12006 + globals->root.sgotplt->output_offset + off)
12007 - (input_section->output_section->vma
12008 + input_section->output_offset
12009 + rel->r_offset)
12010 + globals->sgotplt_jump_table_size);
12011 }
12012 else
12013 value = ((globals->root.sgot->output_section->vma
12014 + globals->root.sgot->output_offset + off)
12015 - (input_section->output_section->vma
12016 + input_section->output_offset + rel->r_offset));
12017
12018 if (globals->fdpic_p && (r_type == R_ARM_TLS_GD32_FDPIC ||
12019 r_type == R_ARM_TLS_IE32_FDPIC))
12020 {
12021 /* For FDPIC relocations, resolve to the offset of the GOT
12022 entry from the start of GOT. */
12023 bfd_put_32 (output_bfd,
12024 globals->root.sgot->output_offset + off,
12025 contents + rel->r_offset);
12026
12027 return bfd_reloc_ok;
12028 }
12029 else
12030 {
12031 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12032 contents, rel->r_offset, value,
12033 rel->r_addend);
12034 }
12035 }
12036
12037 case R_ARM_TLS_LE32:
12038 if (bfd_link_dll (info))
12039 {
12040 _bfd_error_handler
12041 /* xgettext:c-format */
12042 (_("%pB(%pA+%#" PRIx64 "): %s relocation not permitted "
12043 "in shared object"),
12044 input_bfd, input_section, (uint64_t) rel->r_offset, howto->name);
12045 return bfd_reloc_notsupported;
12046 }
12047 else
12048 value = tpoff (info, value);
12049
12050 return _bfd_final_link_relocate (howto, input_bfd, input_section,
12051 contents, rel->r_offset, value,
12052 rel->r_addend);
12053
12054 case R_ARM_V4BX:
12055 if (globals->fix_v4bx)
12056 {
12057 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12058
12059 /* Ensure that we have a BX instruction. */
12060 BFD_ASSERT ((insn & 0x0ffffff0) == 0x012fff10);
12061
12062 if (globals->fix_v4bx == 2 && (insn & 0xf) != 0xf)
12063 {
12064 /* Branch to veneer. */
12065 bfd_vma glue_addr;
12066 glue_addr = elf32_arm_bx_glue (info, insn & 0xf);
12067 glue_addr -= input_section->output_section->vma
12068 + input_section->output_offset
12069 + rel->r_offset + 8;
12070 insn = (insn & 0xf0000000) | 0x0a000000
12071 | ((glue_addr >> 2) & 0x00ffffff);
12072 }
12073 else
12074 {
12075 /* Preserve Rm (lowest four bits) and the condition code
12076 (highest four bits). Other bits encode MOV PC,Rm. */
12077 insn = (insn & 0xf000000f) | 0x01a0f000;
12078 }
12079
12080 bfd_put_32 (input_bfd, insn, hit_data);
12081 }
12082 return bfd_reloc_ok;
12083
12084 case R_ARM_MOVW_ABS_NC:
12085 case R_ARM_MOVT_ABS:
12086 case R_ARM_MOVW_PREL_NC:
12087 case R_ARM_MOVT_PREL:
12088 /* Until we properly support segment-base-relative addressing then
12089 we assume the segment base to be zero, as for the group relocations.
12090 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12091 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12092 case R_ARM_MOVW_BREL_NC:
12093 case R_ARM_MOVW_BREL:
12094 case R_ARM_MOVT_BREL:
12095 {
12096 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12097
12098 if (globals->use_rel)
12099 {
12100 addend = ((insn >> 4) & 0xf000) | (insn & 0xfff);
12101 signed_addend = (addend ^ 0x8000) - 0x8000;
12102 }
12103
12104 value += signed_addend;
12105
12106 if (r_type == R_ARM_MOVW_PREL_NC || r_type == R_ARM_MOVT_PREL)
12107 value -= (input_section->output_section->vma
12108 + input_section->output_offset + rel->r_offset);
12109
12110 if (r_type == R_ARM_MOVW_BREL && value >= 0x10000)
12111 return bfd_reloc_overflow;
12112
12113 if (branch_type == ST_BRANCH_TO_THUMB)
12114 value |= 1;
12115
12116 if (r_type == R_ARM_MOVT_ABS || r_type == R_ARM_MOVT_PREL
12117 || r_type == R_ARM_MOVT_BREL)
12118 value >>= 16;
12119
12120 insn &= 0xfff0f000;
12121 insn |= value & 0xfff;
12122 insn |= (value & 0xf000) << 4;
12123 bfd_put_32 (input_bfd, insn, hit_data);
12124 }
12125 return bfd_reloc_ok;
12126
12127 case R_ARM_THM_MOVW_ABS_NC:
12128 case R_ARM_THM_MOVT_ABS:
12129 case R_ARM_THM_MOVW_PREL_NC:
12130 case R_ARM_THM_MOVT_PREL:
12131 /* Until we properly support segment-base-relative addressing then
12132 we assume the segment base to be zero, as for the above relocations.
12133 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12134 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12135 as R_ARM_THM_MOVT_ABS. */
12136 case R_ARM_THM_MOVW_BREL_NC:
12137 case R_ARM_THM_MOVW_BREL:
12138 case R_ARM_THM_MOVT_BREL:
12139 {
12140 bfd_vma insn;
12141
12142 insn = bfd_get_16 (input_bfd, hit_data) << 16;
12143 insn |= bfd_get_16 (input_bfd, hit_data + 2);
12144
12145 if (globals->use_rel)
12146 {
12147 addend = ((insn >> 4) & 0xf000)
12148 | ((insn >> 15) & 0x0800)
12149 | ((insn >> 4) & 0x0700)
12150 | (insn & 0x00ff);
12151 signed_addend = (addend ^ 0x8000) - 0x8000;
12152 }
12153
12154 value += signed_addend;
12155
12156 if (r_type == R_ARM_THM_MOVW_PREL_NC || r_type == R_ARM_THM_MOVT_PREL)
12157 value -= (input_section->output_section->vma
12158 + input_section->output_offset + rel->r_offset);
12159
12160 if (r_type == R_ARM_THM_MOVW_BREL && value >= 0x10000)
12161 return bfd_reloc_overflow;
12162
12163 if (branch_type == ST_BRANCH_TO_THUMB)
12164 value |= 1;
12165
12166 if (r_type == R_ARM_THM_MOVT_ABS || r_type == R_ARM_THM_MOVT_PREL
12167 || r_type == R_ARM_THM_MOVT_BREL)
12168 value >>= 16;
12169
12170 insn &= 0xfbf08f00;
12171 insn |= (value & 0xf000) << 4;
12172 insn |= (value & 0x0800) << 15;
12173 insn |= (value & 0x0700) << 4;
12174 insn |= (value & 0x00ff);
12175
12176 bfd_put_16 (input_bfd, insn >> 16, hit_data);
12177 bfd_put_16 (input_bfd, insn & 0xffff, hit_data + 2);
12178 }
12179 return bfd_reloc_ok;
12180
12181 case R_ARM_ALU_PC_G0_NC:
12182 case R_ARM_ALU_PC_G1_NC:
12183 case R_ARM_ALU_PC_G0:
12184 case R_ARM_ALU_PC_G1:
12185 case R_ARM_ALU_PC_G2:
12186 case R_ARM_ALU_SB_G0_NC:
12187 case R_ARM_ALU_SB_G1_NC:
12188 case R_ARM_ALU_SB_G0:
12189 case R_ARM_ALU_SB_G1:
12190 case R_ARM_ALU_SB_G2:
12191 {
12192 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12193 bfd_vma pc = input_section->output_section->vma
12194 + input_section->output_offset + rel->r_offset;
12195 /* sb is the origin of the *segment* containing the symbol. */
12196 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
12197 bfd_vma residual;
12198 bfd_vma g_n;
12199 bfd_signed_vma signed_value;
12200 int group = 0;
12201
12202 /* Determine which group of bits to select. */
12203 switch (r_type)
12204 {
12205 case R_ARM_ALU_PC_G0_NC:
12206 case R_ARM_ALU_PC_G0:
12207 case R_ARM_ALU_SB_G0_NC:
12208 case R_ARM_ALU_SB_G0:
12209 group = 0;
12210 break;
12211
12212 case R_ARM_ALU_PC_G1_NC:
12213 case R_ARM_ALU_PC_G1:
12214 case R_ARM_ALU_SB_G1_NC:
12215 case R_ARM_ALU_SB_G1:
12216 group = 1;
12217 break;
12218
12219 case R_ARM_ALU_PC_G2:
12220 case R_ARM_ALU_SB_G2:
12221 group = 2;
12222 break;
12223
12224 default:
12225 abort ();
12226 }
12227
12228 /* If REL, extract the addend from the insn. If RELA, it will
12229 have already been fetched for us. */
12230 if (globals->use_rel)
12231 {
12232 int negative;
12233 bfd_vma constant = insn & 0xff;
12234 bfd_vma rotation = (insn & 0xf00) >> 8;
12235
12236 if (rotation == 0)
12237 signed_addend = constant;
12238 else
12239 {
12240 /* Compensate for the fact that in the instruction, the
12241 rotation is stored in multiples of 2 bits. */
12242 rotation *= 2;
12243
12244 /* Rotate "constant" right by "rotation" bits. */
12245 signed_addend = (constant >> rotation) |
12246 (constant << (8 * sizeof (bfd_vma) - rotation));
12247 }
12248
12249 /* Determine if the instruction is an ADD or a SUB.
12250 (For REL, this determines the sign of the addend.) */
12251 negative = identify_add_or_sub (insn);
12252 if (negative == 0)
12253 {
12254 _bfd_error_handler
12255 /* xgettext:c-format */
12256 (_("%pB(%pA+%#" PRIx64 "): only ADD or SUB instructions "
12257 "are allowed for ALU group relocations"),
12258 input_bfd, input_section, (uint64_t) rel->r_offset);
12259 return bfd_reloc_overflow;
12260 }
12261
12262 signed_addend *= negative;
12263 }
12264
12265 /* Compute the value (X) to go in the place. */
12266 if (r_type == R_ARM_ALU_PC_G0_NC
12267 || r_type == R_ARM_ALU_PC_G1_NC
12268 || r_type == R_ARM_ALU_PC_G0
12269 || r_type == R_ARM_ALU_PC_G1
12270 || r_type == R_ARM_ALU_PC_G2)
12271 /* PC relative. */
12272 signed_value = value - pc + signed_addend;
12273 else
12274 /* Section base relative. */
12275 signed_value = value - sb + signed_addend;
12276
12277 /* If the target symbol is a Thumb function, then set the
12278 Thumb bit in the address. */
12279 if (branch_type == ST_BRANCH_TO_THUMB)
12280 signed_value |= 1;
12281
12282 /* Calculate the value of the relevant G_n, in encoded
12283 constant-with-rotation format. */
12284 g_n = calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12285 group, &residual);
12286
12287 /* Check for overflow if required. */
12288 if ((r_type == R_ARM_ALU_PC_G0
12289 || r_type == R_ARM_ALU_PC_G1
12290 || r_type == R_ARM_ALU_PC_G2
12291 || r_type == R_ARM_ALU_SB_G0
12292 || r_type == R_ARM_ALU_SB_G1
12293 || r_type == R_ARM_ALU_SB_G2) && residual != 0)
12294 {
12295 _bfd_error_handler
12296 /* xgettext:c-format */
12297 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
12298 "splitting %#" PRIx64 " for group relocation %s"),
12299 input_bfd, input_section, (uint64_t) rel->r_offset,
12300 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12301 howto->name);
12302 return bfd_reloc_overflow;
12303 }
12304
12305 /* Mask out the value and the ADD/SUB part of the opcode; take care
12306 not to destroy the S bit. */
12307 insn &= 0xff1ff000;
12308
12309 /* Set the opcode according to whether the value to go in the
12310 place is negative. */
12311 if (signed_value < 0)
12312 insn |= 1 << 22;
12313 else
12314 insn |= 1 << 23;
12315
12316 /* Encode the offset. */
12317 insn |= g_n;
12318
12319 bfd_put_32 (input_bfd, insn, hit_data);
12320 }
12321 return bfd_reloc_ok;
12322
12323 case R_ARM_LDR_PC_G0:
12324 case R_ARM_LDR_PC_G1:
12325 case R_ARM_LDR_PC_G2:
12326 case R_ARM_LDR_SB_G0:
12327 case R_ARM_LDR_SB_G1:
12328 case R_ARM_LDR_SB_G2:
12329 {
12330 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12331 bfd_vma pc = input_section->output_section->vma
12332 + input_section->output_offset + rel->r_offset;
12333 /* sb is the origin of the *segment* containing the symbol. */
12334 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
12335 bfd_vma residual;
12336 bfd_signed_vma signed_value;
12337 int group = 0;
12338
12339 /* Determine which groups of bits to calculate. */
12340 switch (r_type)
12341 {
12342 case R_ARM_LDR_PC_G0:
12343 case R_ARM_LDR_SB_G0:
12344 group = 0;
12345 break;
12346
12347 case R_ARM_LDR_PC_G1:
12348 case R_ARM_LDR_SB_G1:
12349 group = 1;
12350 break;
12351
12352 case R_ARM_LDR_PC_G2:
12353 case R_ARM_LDR_SB_G2:
12354 group = 2;
12355 break;
12356
12357 default:
12358 abort ();
12359 }
12360
12361 /* If REL, extract the addend from the insn. If RELA, it will
12362 have already been fetched for us. */
12363 if (globals->use_rel)
12364 {
12365 int negative = (insn & (1 << 23)) ? 1 : -1;
12366 signed_addend = negative * (insn & 0xfff);
12367 }
12368
12369 /* Compute the value (X) to go in the place. */
12370 if (r_type == R_ARM_LDR_PC_G0
12371 || r_type == R_ARM_LDR_PC_G1
12372 || r_type == R_ARM_LDR_PC_G2)
12373 /* PC relative. */
12374 signed_value = value - pc + signed_addend;
12375 else
12376 /* Section base relative. */
12377 signed_value = value - sb + signed_addend;
12378
12379 /* Calculate the value of the relevant G_{n-1} to obtain
12380 the residual at that stage. */
12381 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12382 group - 1, &residual);
12383
12384 /* Check for overflow. */
12385 if (residual >= 0x1000)
12386 {
12387 _bfd_error_handler
12388 /* xgettext:c-format */
12389 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
12390 "splitting %#" PRIx64 " for group relocation %s"),
12391 input_bfd, input_section, (uint64_t) rel->r_offset,
12392 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12393 howto->name);
12394 return bfd_reloc_overflow;
12395 }
12396
12397 /* Mask out the value and U bit. */
12398 insn &= 0xff7ff000;
12399
12400 /* Set the U bit if the value to go in the place is non-negative. */
12401 if (signed_value >= 0)
12402 insn |= 1 << 23;
12403
12404 /* Encode the offset. */
12405 insn |= residual;
12406
12407 bfd_put_32 (input_bfd, insn, hit_data);
12408 }
12409 return bfd_reloc_ok;
12410
12411 case R_ARM_LDRS_PC_G0:
12412 case R_ARM_LDRS_PC_G1:
12413 case R_ARM_LDRS_PC_G2:
12414 case R_ARM_LDRS_SB_G0:
12415 case R_ARM_LDRS_SB_G1:
12416 case R_ARM_LDRS_SB_G2:
12417 {
12418 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12419 bfd_vma pc = input_section->output_section->vma
12420 + input_section->output_offset + rel->r_offset;
12421 /* sb is the origin of the *segment* containing the symbol. */
12422 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
12423 bfd_vma residual;
12424 bfd_signed_vma signed_value;
12425 int group = 0;
12426
12427 /* Determine which groups of bits to calculate. */
12428 switch (r_type)
12429 {
12430 case R_ARM_LDRS_PC_G0:
12431 case R_ARM_LDRS_SB_G0:
12432 group = 0;
12433 break;
12434
12435 case R_ARM_LDRS_PC_G1:
12436 case R_ARM_LDRS_SB_G1:
12437 group = 1;
12438 break;
12439
12440 case R_ARM_LDRS_PC_G2:
12441 case R_ARM_LDRS_SB_G2:
12442 group = 2;
12443 break;
12444
12445 default:
12446 abort ();
12447 }
12448
12449 /* If REL, extract the addend from the insn. If RELA, it will
12450 have already been fetched for us. */
12451 if (globals->use_rel)
12452 {
12453 int negative = (insn & (1 << 23)) ? 1 : -1;
12454 signed_addend = negative * (((insn & 0xf00) >> 4) + (insn & 0xf));
12455 }
12456
12457 /* Compute the value (X) to go in the place. */
12458 if (r_type == R_ARM_LDRS_PC_G0
12459 || r_type == R_ARM_LDRS_PC_G1
12460 || r_type == R_ARM_LDRS_PC_G2)
12461 /* PC relative. */
12462 signed_value = value - pc + signed_addend;
12463 else
12464 /* Section base relative. */
12465 signed_value = value - sb + signed_addend;
12466
12467 /* Calculate the value of the relevant G_{n-1} to obtain
12468 the residual at that stage. */
12469 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12470 group - 1, &residual);
12471
12472 /* Check for overflow. */
12473 if (residual >= 0x100)
12474 {
12475 _bfd_error_handler
12476 /* xgettext:c-format */
12477 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
12478 "splitting %#" PRIx64 " for group relocation %s"),
12479 input_bfd, input_section, (uint64_t) rel->r_offset,
12480 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12481 howto->name);
12482 return bfd_reloc_overflow;
12483 }
12484
12485 /* Mask out the value and U bit. */
12486 insn &= 0xff7ff0f0;
12487
12488 /* Set the U bit if the value to go in the place is non-negative. */
12489 if (signed_value >= 0)
12490 insn |= 1 << 23;
12491
12492 /* Encode the offset. */
12493 insn |= ((residual & 0xf0) << 4) | (residual & 0xf);
12494
12495 bfd_put_32 (input_bfd, insn, hit_data);
12496 }
12497 return bfd_reloc_ok;
12498
12499 case R_ARM_LDC_PC_G0:
12500 case R_ARM_LDC_PC_G1:
12501 case R_ARM_LDC_PC_G2:
12502 case R_ARM_LDC_SB_G0:
12503 case R_ARM_LDC_SB_G1:
12504 case R_ARM_LDC_SB_G2:
12505 {
12506 bfd_vma insn = bfd_get_32 (input_bfd, hit_data);
12507 bfd_vma pc = input_section->output_section->vma
12508 + input_section->output_offset + rel->r_offset;
12509 /* sb is the origin of the *segment* containing the symbol. */
12510 bfd_vma sb = sym_sec ? sym_sec->output_section->vma : 0;
12511 bfd_vma residual;
12512 bfd_signed_vma signed_value;
12513 int group = 0;
12514
12515 /* Determine which groups of bits to calculate. */
12516 switch (r_type)
12517 {
12518 case R_ARM_LDC_PC_G0:
12519 case R_ARM_LDC_SB_G0:
12520 group = 0;
12521 break;
12522
12523 case R_ARM_LDC_PC_G1:
12524 case R_ARM_LDC_SB_G1:
12525 group = 1;
12526 break;
12527
12528 case R_ARM_LDC_PC_G2:
12529 case R_ARM_LDC_SB_G2:
12530 group = 2;
12531 break;
12532
12533 default:
12534 abort ();
12535 }
12536
12537 /* If REL, extract the addend from the insn. If RELA, it will
12538 have already been fetched for us. */
12539 if (globals->use_rel)
12540 {
12541 int negative = (insn & (1 << 23)) ? 1 : -1;
12542 signed_addend = negative * ((insn & 0xff) << 2);
12543 }
12544
12545 /* Compute the value (X) to go in the place. */
12546 if (r_type == R_ARM_LDC_PC_G0
12547 || r_type == R_ARM_LDC_PC_G1
12548 || r_type == R_ARM_LDC_PC_G2)
12549 /* PC relative. */
12550 signed_value = value - pc + signed_addend;
12551 else
12552 /* Section base relative. */
12553 signed_value = value - sb + signed_addend;
12554
12555 /* Calculate the value of the relevant G_{n-1} to obtain
12556 the residual at that stage. */
12557 calculate_group_reloc_mask (signed_value < 0 ? - signed_value : signed_value,
12558 group - 1, &residual);
12559
12560 /* Check for overflow. (The absolute value to go in the place must be
12561 divisible by four and, after having been divided by four, must
12562 fit in eight bits.) */
12563 if ((residual & 0x3) != 0 || residual >= 0x400)
12564 {
12565 _bfd_error_handler
12566 /* xgettext:c-format */
12567 (_("%pB(%pA+%#" PRIx64 "): overflow whilst "
12568 "splitting %#" PRIx64 " for group relocation %s"),
12569 input_bfd, input_section, (uint64_t) rel->r_offset,
12570 (uint64_t) (signed_value < 0 ? -signed_value : signed_value),
12571 howto->name);
12572 return bfd_reloc_overflow;
12573 }
12574
12575 /* Mask out the value and U bit. */
12576 insn &= 0xff7fff00;
12577
12578 /* Set the U bit if the value to go in the place is non-negative. */
12579 if (signed_value >= 0)
12580 insn |= 1 << 23;
12581
12582 /* Encode the offset. */
12583 insn |= residual >> 2;
12584
12585 bfd_put_32 (input_bfd, insn, hit_data);
12586 }
12587 return bfd_reloc_ok;
12588
12589 case R_ARM_THM_ALU_ABS_G0_NC:
12590 case R_ARM_THM_ALU_ABS_G1_NC:
12591 case R_ARM_THM_ALU_ABS_G2_NC:
12592 case R_ARM_THM_ALU_ABS_G3_NC:
12593 {
12594 const int shift_array[4] = {0, 8, 16, 24};
12595 bfd_vma insn = bfd_get_16 (input_bfd, hit_data);
12596 bfd_vma addr = value;
12597 int shift = shift_array[r_type - R_ARM_THM_ALU_ABS_G0_NC];
12598
12599 /* Compute address. */
12600 if (globals->use_rel)
12601 signed_addend = insn & 0xff;
12602 addr += signed_addend;
12603 if (branch_type == ST_BRANCH_TO_THUMB)
12604 addr |= 1;
12605 /* Clean imm8 insn. */
12606 insn &= 0xff00;
12607 /* And update with correct part of address. */
12608 insn |= (addr >> shift) & 0xff;
12609 /* Update insn. */
12610 bfd_put_16 (input_bfd, insn, hit_data);
12611 }
12612
12613 *unresolved_reloc_p = false;
12614 return bfd_reloc_ok;
12615
12616 case R_ARM_GOTOFFFUNCDESC:
12617 {
12618 if (h == NULL)
12619 {
12620 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts (input_bfd);
12621 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12622
12623 if (r_symndx >= elf32_arm_num_entries (input_bfd))
12624 {
12625 * error_message = _("local symbol index too big");
12626 return bfd_reloc_dangerous;
12627 }
12628
12629 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12630 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12631 bfd_vma seg = -1;
12632
12633 if (bfd_link_pic (info) && dynindx == 0)
12634 {
12635 * error_message = _("no dynamic index information available");
12636 return bfd_reloc_dangerous;
12637 }
12638
12639 /* Resolve relocation. */
12640 bfd_put_32 (output_bfd, (offset + sgot->output_offset)
12641 , contents + rel->r_offset);
12642 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12643 not done yet. */
12644 arm_elf_fill_funcdesc (output_bfd, info,
12645 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12646 dynindx, offset, addr, dynreloc_value, seg);
12647 }
12648 else
12649 {
12650 int dynindx;
12651 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12652 bfd_vma addr;
12653 bfd_vma seg = -1;
12654
12655 /* For static binaries, sym_sec can be null. */
12656 if (sym_sec)
12657 {
12658 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12659 addr = dynreloc_value - sym_sec->output_section->vma;
12660 }
12661 else
12662 {
12663 dynindx = 0;
12664 addr = 0;
12665 }
12666
12667 if (bfd_link_pic (info) && dynindx == 0)
12668 {
12669 * error_message = _("no dynamic index information available");
12670 return bfd_reloc_dangerous;
12671 }
12672
12673 /* This case cannot occur since funcdesc is allocated by
12674 the dynamic loader so we cannot resolve the relocation. */
12675 if (h->dynindx != -1)
12676 {
12677 * error_message = _("invalid dynamic index");
12678 return bfd_reloc_dangerous;
12679 }
12680
12681 /* Resolve relocation. */
12682 bfd_put_32 (output_bfd, (offset + sgot->output_offset),
12683 contents + rel->r_offset);
12684 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12685 arm_elf_fill_funcdesc (output_bfd, info,
12686 &eh->fdpic_cnts.funcdesc_offset,
12687 dynindx, offset, addr, dynreloc_value, seg);
12688 }
12689 }
12690 *unresolved_reloc_p = false;
12691 return bfd_reloc_ok;
12692
12693 case R_ARM_GOTFUNCDESC:
12694 {
12695 if (h != NULL)
12696 {
12697 Elf_Internal_Rela outrel;
12698
12699 /* Resolve relocation. */
12700 bfd_put_32 (output_bfd, ((eh->fdpic_cnts.gotfuncdesc_offset & ~1)
12701 + sgot->output_offset),
12702 contents + rel->r_offset);
12703 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12704 if (h->dynindx == -1)
12705 {
12706 int dynindx;
12707 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12708 bfd_vma addr;
12709 bfd_vma seg = -1;
12710
12711 /* For static binaries sym_sec can be null. */
12712 if (sym_sec)
12713 {
12714 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12715 addr = dynreloc_value - sym_sec->output_section->vma;
12716 }
12717 else
12718 {
12719 dynindx = 0;
12720 addr = 0;
12721 }
12722
12723 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12724 arm_elf_fill_funcdesc (output_bfd, info,
12725 &eh->fdpic_cnts.funcdesc_offset,
12726 dynindx, offset, addr, dynreloc_value, seg);
12727 }
12728
12729 /* Add a dynamic relocation on GOT entry if not already done. */
12730 if ((eh->fdpic_cnts.gotfuncdesc_offset & 1) == 0)
12731 {
12732 if (h->dynindx == -1)
12733 {
12734 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12735 if (h->root.type == bfd_link_hash_undefweak)
12736 bfd_put_32 (output_bfd, 0, sgot->contents
12737 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12738 else
12739 bfd_put_32 (output_bfd, sgot->output_section->vma
12740 + sgot->output_offset
12741 + (eh->fdpic_cnts.funcdesc_offset & ~1),
12742 sgot->contents
12743 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1));
12744 }
12745 else
12746 {
12747 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12748 }
12749 outrel.r_offset = sgot->output_section->vma
12750 + sgot->output_offset
12751 + (eh->fdpic_cnts.gotfuncdesc_offset & ~1);
12752 outrel.r_addend = 0;
12753 if (h->dynindx == -1 && !bfd_link_pic (info))
12754 if (h->root.type == bfd_link_hash_undefweak)
12755 arm_elf_add_rofixup (output_bfd, globals->srofixup, -1);
12756 else
12757 arm_elf_add_rofixup (output_bfd, globals->srofixup,
12758 outrel.r_offset);
12759 else
12760 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12761 eh->fdpic_cnts.gotfuncdesc_offset |= 1;
12762 }
12763 }
12764 else
12765 {
12766 /* Such relocation on static function should not have been
12767 emitted by the compiler. */
12768 return bfd_reloc_notsupported;
12769 }
12770 }
12771 *unresolved_reloc_p = false;
12772 return bfd_reloc_ok;
12773
12774 case R_ARM_FUNCDESC:
12775 {
12776 if (h == NULL)
12777 {
12778 struct fdpic_local *local_fdpic_cnts = elf32_arm_local_fdpic_cnts (input_bfd);
12779 Elf_Internal_Rela outrel;
12780 int dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12781
12782 if (r_symndx >= elf32_arm_num_entries (input_bfd))
12783 {
12784 * error_message = _("local symbol index too big");
12785 return bfd_reloc_dangerous;
12786 }
12787
12788 int offset = local_fdpic_cnts[r_symndx].funcdesc_offset & ~1;
12789 bfd_vma addr = dynreloc_value - sym_sec->output_section->vma;
12790 bfd_vma seg = -1;
12791
12792 if (bfd_link_pic (info) && dynindx == 0)
12793 {
12794 * error_message = _("dynamic index information not available");
12795 return bfd_reloc_dangerous;
12796 }
12797
12798 /* Replace static FUNCDESC relocation with a
12799 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12800 executable. */
12801 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12802 outrel.r_offset = input_section->output_section->vma
12803 + input_section->output_offset + rel->r_offset;
12804 outrel.r_addend = 0;
12805 if (bfd_link_pic (info))
12806 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12807 else
12808 arm_elf_add_rofixup (output_bfd, globals->srofixup, outrel.r_offset);
12809
12810 bfd_put_32 (input_bfd, sgot->output_section->vma
12811 + sgot->output_offset + offset, hit_data);
12812
12813 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12814 arm_elf_fill_funcdesc (output_bfd, info,
12815 &local_fdpic_cnts[r_symndx].funcdesc_offset,
12816 dynindx, offset, addr, dynreloc_value, seg);
12817 }
12818 else
12819 {
12820 if (h->dynindx == -1)
12821 {
12822 int dynindx;
12823 int offset = eh->fdpic_cnts.funcdesc_offset & ~1;
12824 bfd_vma addr;
12825 bfd_vma seg = -1;
12826 Elf_Internal_Rela outrel;
12827
12828 /* For static binaries sym_sec can be null. */
12829 if (sym_sec)
12830 {
12831 dynindx = elf_section_data (sym_sec->output_section)->dynindx;
12832 addr = dynreloc_value - sym_sec->output_section->vma;
12833 }
12834 else
12835 {
12836 dynindx = 0;
12837 addr = 0;
12838 }
12839
12840 if (bfd_link_pic (info) && dynindx == 0)
12841 abort ();
12842
12843 /* Replace static FUNCDESC relocation with a
12844 R_ARM_RELATIVE dynamic relocation. */
12845 outrel.r_info = ELF32_R_INFO (0, R_ARM_RELATIVE);
12846 outrel.r_offset = input_section->output_section->vma
12847 + input_section->output_offset + rel->r_offset;
12848 outrel.r_addend = 0;
12849 if (bfd_link_pic (info))
12850 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12851 else
12852 arm_elf_add_rofixup (output_bfd, globals->srofixup, outrel.r_offset);
12853
12854 bfd_put_32 (input_bfd, sgot->output_section->vma
12855 + sgot->output_offset + offset, hit_data);
12856
12857 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12858 arm_elf_fill_funcdesc (output_bfd, info,
12859 &eh->fdpic_cnts.funcdesc_offset,
12860 dynindx, offset, addr, dynreloc_value, seg);
12861 }
12862 else
12863 {
12864 Elf_Internal_Rela outrel;
12865
12866 /* Add a dynamic relocation. */
12867 outrel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_FUNCDESC);
12868 outrel.r_offset = input_section->output_section->vma
12869 + input_section->output_offset + rel->r_offset;
12870 outrel.r_addend = 0;
12871 elf32_arm_add_dynreloc (output_bfd, info, srelgot, &outrel);
12872 }
12873 }
12874 }
12875 *unresolved_reloc_p = false;
12876 return bfd_reloc_ok;
12877
12878 case R_ARM_THM_BF16:
12879 {
12880 bfd_vma relocation;
12881 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12882 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12883
12884 if (globals->use_rel)
12885 {
12886 bfd_vma immA = (upper_insn & 0x001f);
12887 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12888 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12889 addend = (immA << 12);
12890 addend |= (immB << 2);
12891 addend |= (immC << 1);
12892 addend |= 1;
12893 /* Sign extend. */
12894 signed_addend = (addend & 0x10000) ? addend - (1 << 17) : addend;
12895 }
12896
12897 relocation = value + signed_addend;
12898 relocation -= (input_section->output_section->vma
12899 + input_section->output_offset
12900 + rel->r_offset);
12901
12902 /* Put RELOCATION back into the insn. */
12903 {
12904 bfd_vma immA = (relocation & 0x0001f000) >> 12;
12905 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12906 bfd_vma immC = (relocation & 0x00000002) >> 1;
12907
12908 upper_insn = (upper_insn & 0xffe0) | immA;
12909 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12910 }
12911
12912 /* Put the relocated value back in the object file: */
12913 bfd_put_16 (input_bfd, upper_insn, hit_data);
12914 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12915
12916 return bfd_reloc_ok;
12917 }
12918
12919 case R_ARM_THM_BF12:
12920 {
12921 bfd_vma relocation;
12922 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12923 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12924
12925 if (globals->use_rel)
12926 {
12927 bfd_vma immA = (upper_insn & 0x0001);
12928 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12929 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12930 addend = (immA << 12);
12931 addend |= (immB << 2);
12932 addend |= (immC << 1);
12933 addend |= 1;
12934 /* Sign extend. */
12935 addend = (addend & 0x1000) ? addend - (1 << 13) : addend;
12936 signed_addend = addend;
12937 }
12938
12939 relocation = value + signed_addend;
12940 relocation -= (input_section->output_section->vma
12941 + input_section->output_offset
12942 + rel->r_offset);
12943
12944 /* Put RELOCATION back into the insn. */
12945 {
12946 bfd_vma immA = (relocation & 0x00001000) >> 12;
12947 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12948 bfd_vma immC = (relocation & 0x00000002) >> 1;
12949
12950 upper_insn = (upper_insn & 0xfffe) | immA;
12951 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12952 }
12953
12954 /* Put the relocated value back in the object file: */
12955 bfd_put_16 (input_bfd, upper_insn, hit_data);
12956 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12957
12958 return bfd_reloc_ok;
12959 }
12960
12961 case R_ARM_THM_BF18:
12962 {
12963 bfd_vma relocation;
12964 bfd_vma upper_insn = bfd_get_16 (input_bfd, hit_data);
12965 bfd_vma lower_insn = bfd_get_16 (input_bfd, hit_data + 2);
12966
12967 if (globals->use_rel)
12968 {
12969 bfd_vma immA = (upper_insn & 0x007f);
12970 bfd_vma immB = (lower_insn & 0x07fe) >> 1;
12971 bfd_vma immC = (lower_insn & 0x0800) >> 11;
12972 addend = (immA << 12);
12973 addend |= (immB << 2);
12974 addend |= (immC << 1);
12975 addend |= 1;
12976 /* Sign extend. */
12977 addend = (addend & 0x40000) ? addend - (1 << 19) : addend;
12978 signed_addend = addend;
12979 }
12980
12981 relocation = value + signed_addend;
12982 relocation -= (input_section->output_section->vma
12983 + input_section->output_offset
12984 + rel->r_offset);
12985
12986 /* Put RELOCATION back into the insn. */
12987 {
12988 bfd_vma immA = (relocation & 0x0007f000) >> 12;
12989 bfd_vma immB = (relocation & 0x00000ffc) >> 2;
12990 bfd_vma immC = (relocation & 0x00000002) >> 1;
12991
12992 upper_insn = (upper_insn & 0xff80) | immA;
12993 lower_insn = (lower_insn & 0xf001) | (immC << 11) | (immB << 1);
12994 }
12995
12996 /* Put the relocated value back in the object file: */
12997 bfd_put_16 (input_bfd, upper_insn, hit_data);
12998 bfd_put_16 (input_bfd, lower_insn, hit_data + 2);
12999
13000 return bfd_reloc_ok;
13001 }
13002
13003 default:
13004 return bfd_reloc_notsupported;
13005 }
13006 }
13007
13008 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13009 static void
13010 arm_add_to_rel (bfd * abfd,
13011 bfd_byte * address,
13012 reloc_howto_type * howto,
13013 bfd_signed_vma increment)
13014 {
13015 bfd_signed_vma addend;
13016
13017 if (howto->type == R_ARM_THM_CALL
13018 || howto->type == R_ARM_THM_JUMP24)
13019 {
13020 int upper_insn, lower_insn;
13021 int upper, lower;
13022
13023 upper_insn = bfd_get_16 (abfd, address);
13024 lower_insn = bfd_get_16 (abfd, address + 2);
13025 upper = upper_insn & 0x7ff;
13026 lower = lower_insn & 0x7ff;
13027
13028 addend = (upper << 12) | (lower << 1);
13029 addend += increment;
13030 addend >>= 1;
13031
13032 upper_insn = (upper_insn & 0xf800) | ((addend >> 11) & 0x7ff);
13033 lower_insn = (lower_insn & 0xf800) | (addend & 0x7ff);
13034
13035 bfd_put_16 (abfd, (bfd_vma) upper_insn, address);
13036 bfd_put_16 (abfd, (bfd_vma) lower_insn, address + 2);
13037 }
13038 else
13039 {
13040 bfd_vma contents;
13041
13042 contents = bfd_get_32 (abfd, address);
13043
13044 /* Get the (signed) value from the instruction. */
13045 addend = contents & howto->src_mask;
13046 if (addend & ((howto->src_mask + 1) >> 1))
13047 {
13048 bfd_signed_vma mask;
13049
13050 mask = -1;
13051 mask &= ~ howto->src_mask;
13052 addend |= mask;
13053 }
13054
13055 /* Add in the increment, (which is a byte value). */
13056 switch (howto->type)
13057 {
13058 default:
13059 addend += increment;
13060 break;
13061
13062 case R_ARM_PC24:
13063 case R_ARM_PLT32:
13064 case R_ARM_CALL:
13065 case R_ARM_JUMP24:
13066 addend *= bfd_get_reloc_size (howto);
13067 addend += increment;
13068
13069 /* Should we check for overflow here ? */
13070
13071 /* Drop any undesired bits. */
13072 addend >>= howto->rightshift;
13073 break;
13074 }
13075
13076 contents = (contents & ~ howto->dst_mask) | (addend & howto->dst_mask);
13077
13078 bfd_put_32 (abfd, contents, address);
13079 }
13080 }
13081
13082 #define IS_ARM_TLS_RELOC(R_TYPE) \
13083 ((R_TYPE) == R_ARM_TLS_GD32 \
13084 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
13085 || (R_TYPE) == R_ARM_TLS_LDO32 \
13086 || (R_TYPE) == R_ARM_TLS_LDM32 \
13087 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
13088 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13089 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13090 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13091 || (R_TYPE) == R_ARM_TLS_LE32 \
13092 || (R_TYPE) == R_ARM_TLS_IE32 \
13093 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
13094 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13095
13096 /* Specific set of relocations for the gnu tls dialect. */
13097 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13098 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13099 || (R_TYPE) == R_ARM_TLS_CALL \
13100 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13101 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13102 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
13103
13104 /* Relocate an ARM ELF section. */
13105
13106 static int
13107 elf32_arm_relocate_section (bfd * output_bfd,
13108 struct bfd_link_info * info,
13109 bfd * input_bfd,
13110 asection * input_section,
13111 bfd_byte * contents,
13112 Elf_Internal_Rela * relocs,
13113 Elf_Internal_Sym * local_syms,
13114 asection ** local_sections)
13115 {
13116 Elf_Internal_Shdr *symtab_hdr;
13117 struct elf_link_hash_entry **sym_hashes;
13118 Elf_Internal_Rela *rel;
13119 Elf_Internal_Rela *relend;
13120 const char *name;
13121 struct elf32_arm_link_hash_table * globals;
13122
13123 globals = elf32_arm_hash_table (info);
13124 if (globals == NULL)
13125 return false;
13126
13127 symtab_hdr = & elf_symtab_hdr (input_bfd);
13128 sym_hashes = elf_sym_hashes (input_bfd);
13129
13130 rel = relocs;
13131 relend = relocs + input_section->reloc_count;
13132 for (; rel < relend; rel++)
13133 {
13134 int r_type;
13135 reloc_howto_type * howto;
13136 unsigned long r_symndx;
13137 Elf_Internal_Sym * sym;
13138 asection * sec;
13139 struct elf_link_hash_entry * h;
13140 bfd_vma relocation;
13141 bfd_reloc_status_type r;
13142 arelent bfd_reloc;
13143 char sym_type;
13144 bool unresolved_reloc = false;
13145 char *error_message = NULL;
13146
13147 r_symndx = ELF32_R_SYM (rel->r_info);
13148 r_type = ELF32_R_TYPE (rel->r_info);
13149 r_type = arm_real_reloc_type (globals, r_type);
13150
13151 if ( r_type == R_ARM_GNU_VTENTRY
13152 || r_type == R_ARM_GNU_VTINHERIT)
13153 continue;
13154
13155 howto = bfd_reloc.howto = elf32_arm_howto_from_type (r_type);
13156
13157 if (howto == NULL)
13158 return _bfd_unrecognized_reloc (input_bfd, input_section, r_type);
13159
13160 h = NULL;
13161 sym = NULL;
13162 sec = NULL;
13163
13164 if (r_symndx < symtab_hdr->sh_info)
13165 {
13166 sym = local_syms + r_symndx;
13167 sym_type = ELF32_ST_TYPE (sym->st_info);
13168 sec = local_sections[r_symndx];
13169
13170 /* An object file might have a reference to a local
13171 undefined symbol. This is a daft object file, but we
13172 should at least do something about it. V4BX & NONE
13173 relocations do not use the symbol and are explicitly
13174 allowed to use the undefined symbol, so allow those.
13175 Likewise for relocations against STN_UNDEF. */
13176 if (r_type != R_ARM_V4BX
13177 && r_type != R_ARM_NONE
13178 && r_symndx != STN_UNDEF
13179 && bfd_is_und_section (sec)
13180 && ELF_ST_BIND (sym->st_info) != STB_WEAK)
13181 (*info->callbacks->undefined_symbol)
13182 (info, bfd_elf_string_from_elf_section
13183 (input_bfd, symtab_hdr->sh_link, sym->st_name),
13184 input_bfd, input_section,
13185 rel->r_offset, true);
13186
13187 if (globals->use_rel)
13188 {
13189 relocation = (sec->output_section->vma
13190 + sec->output_offset
13191 + sym->st_value);
13192 if (!bfd_link_relocatable (info)
13193 && (sec->flags & SEC_MERGE)
13194 && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13195 {
13196 asection *msec;
13197 bfd_vma addend, value;
13198
13199 switch (r_type)
13200 {
13201 case R_ARM_MOVW_ABS_NC:
13202 case R_ARM_MOVT_ABS:
13203 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13204 addend = ((value & 0xf0000) >> 4) | (value & 0xfff);
13205 addend = (addend ^ 0x8000) - 0x8000;
13206 break;
13207
13208 case R_ARM_THM_MOVW_ABS_NC:
13209 case R_ARM_THM_MOVT_ABS:
13210 value = bfd_get_16 (input_bfd, contents + rel->r_offset)
13211 << 16;
13212 value |= bfd_get_16 (input_bfd,
13213 contents + rel->r_offset + 2);
13214 addend = ((value & 0xf7000) >> 4) | (value & 0xff)
13215 | ((value & 0x04000000) >> 15);
13216 addend = (addend ^ 0x8000) - 0x8000;
13217 break;
13218
13219 default:
13220 if (howto->rightshift
13221 || (howto->src_mask & (howto->src_mask + 1)))
13222 {
13223 _bfd_error_handler
13224 /* xgettext:c-format */
13225 (_("%pB(%pA+%#" PRIx64 "): "
13226 "%s relocation against SEC_MERGE section"),
13227 input_bfd, input_section,
13228 (uint64_t) rel->r_offset, howto->name);
13229 return false;
13230 }
13231
13232 value = bfd_get_32 (input_bfd, contents + rel->r_offset);
13233
13234 /* Get the (signed) value from the instruction. */
13235 addend = value & howto->src_mask;
13236 if (addend & ((howto->src_mask + 1) >> 1))
13237 {
13238 bfd_signed_vma mask;
13239
13240 mask = -1;
13241 mask &= ~ howto->src_mask;
13242 addend |= mask;
13243 }
13244 break;
13245 }
13246
13247 msec = sec;
13248 addend =
13249 _bfd_elf_rel_local_sym (output_bfd, sym, &msec, addend)
13250 - relocation;
13251 addend += msec->output_section->vma + msec->output_offset;
13252
13253 /* Cases here must match those in the preceding
13254 switch statement. */
13255 switch (r_type)
13256 {
13257 case R_ARM_MOVW_ABS_NC:
13258 case R_ARM_MOVT_ABS:
13259 value = (value & 0xfff0f000) | ((addend & 0xf000) << 4)
13260 | (addend & 0xfff);
13261 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13262 break;
13263
13264 case R_ARM_THM_MOVW_ABS_NC:
13265 case R_ARM_THM_MOVT_ABS:
13266 value = (value & 0xfbf08f00) | ((addend & 0xf700) << 4)
13267 | (addend & 0xff) | ((addend & 0x0800) << 15);
13268 bfd_put_16 (input_bfd, value >> 16,
13269 contents + rel->r_offset);
13270 bfd_put_16 (input_bfd, value,
13271 contents + rel->r_offset + 2);
13272 break;
13273
13274 default:
13275 value = (value & ~ howto->dst_mask)
13276 | (addend & howto->dst_mask);
13277 bfd_put_32 (input_bfd, value, contents + rel->r_offset);
13278 break;
13279 }
13280 }
13281 }
13282 else
13283 relocation = _bfd_elf_rela_local_sym (output_bfd, sym, &sec, rel);
13284 }
13285 else
13286 {
13287 bool warned, ignored;
13288
13289 RELOC_FOR_GLOBAL_SYMBOL (info, input_bfd, input_section, rel,
13290 r_symndx, symtab_hdr, sym_hashes,
13291 h, sec, relocation,
13292 unresolved_reloc, warned, ignored);
13293
13294 sym_type = h->type;
13295 }
13296
13297 if (sec != NULL && discarded_section (sec))
13298 RELOC_AGAINST_DISCARDED_SECTION (info, input_bfd, input_section,
13299 rel, 1, relend, howto, 0, contents);
13300
13301 if (bfd_link_relocatable (info))
13302 {
13303 /* This is a relocatable link. We don't have to change
13304 anything, unless the reloc is against a section symbol,
13305 in which case we have to adjust according to where the
13306 section symbol winds up in the output section. */
13307 if (sym != NULL && ELF_ST_TYPE (sym->st_info) == STT_SECTION)
13308 {
13309 if (globals->use_rel)
13310 arm_add_to_rel (input_bfd, contents + rel->r_offset,
13311 howto, (bfd_signed_vma) sec->output_offset);
13312 else
13313 rel->r_addend += sec->output_offset;
13314 }
13315 continue;
13316 }
13317
13318 if (h != NULL)
13319 name = h->root.root.string;
13320 else
13321 {
13322 name = (bfd_elf_string_from_elf_section
13323 (input_bfd, symtab_hdr->sh_link, sym->st_name));
13324 if (name == NULL || *name == '\0')
13325 name = bfd_section_name (sec);
13326 }
13327
13328 if (r_symndx != STN_UNDEF
13329 && r_type != R_ARM_NONE
13330 && (h == NULL
13331 || h->root.type == bfd_link_hash_defined
13332 || h->root.type == bfd_link_hash_defweak)
13333 && IS_ARM_TLS_RELOC (r_type) != (sym_type == STT_TLS))
13334 {
13335 _bfd_error_handler
13336 ((sym_type == STT_TLS
13337 /* xgettext:c-format */
13338 ? _("%pB(%pA+%#" PRIx64 "): %s used with TLS symbol %s")
13339 /* xgettext:c-format */
13340 : _("%pB(%pA+%#" PRIx64 "): %s used with non-TLS symbol %s")),
13341 input_bfd,
13342 input_section,
13343 (uint64_t) rel->r_offset,
13344 howto->name,
13345 name);
13346 }
13347
13348 /* We call elf32_arm_final_link_relocate unless we're completely
13349 done, i.e., the relaxation produced the final output we want,
13350 and we won't let anybody mess with it. Also, we have to do
13351 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
13352 both in relaxed and non-relaxed cases. */
13353 if ((elf32_arm_tls_transition (info, r_type, h) != (unsigned)r_type)
13354 || (IS_ARM_TLS_GNU_RELOC (r_type)
13355 && !((h ? elf32_arm_hash_entry (h)->tls_type :
13356 elf32_arm_local_got_tls_type (input_bfd)[r_symndx])
13357 & GOT_TLS_GDESC)))
13358 {
13359 r = elf32_arm_tls_relax (globals, input_bfd, input_section,
13360 contents, rel, h == NULL);
13361 /* This may have been marked unresolved because it came from
13362 a shared library. But we've just dealt with that. */
13363 unresolved_reloc = 0;
13364 }
13365 else
13366 r = bfd_reloc_continue;
13367
13368 if (r == bfd_reloc_continue)
13369 {
13370 unsigned char branch_type =
13371 h ? ARM_GET_SYM_BRANCH_TYPE (h->target_internal)
13372 : ARM_GET_SYM_BRANCH_TYPE (sym->st_target_internal);
13373
13374 r = elf32_arm_final_link_relocate (howto, input_bfd, output_bfd,
13375 input_section, contents, rel,
13376 relocation, info, sec, name,
13377 sym_type, branch_type, h,
13378 &unresolved_reloc,
13379 &error_message);
13380 }
13381
13382 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13383 because such sections are not SEC_ALLOC and thus ld.so will
13384 not process them. */
13385 if (unresolved_reloc
13386 && !((input_section->flags & SEC_DEBUGGING) != 0
13387 && h->def_dynamic)
13388 && _bfd_elf_section_offset (output_bfd, info, input_section,
13389 rel->r_offset) != (bfd_vma) -1)
13390 {
13391 _bfd_error_handler
13392 /* xgettext:c-format */
13393 (_("%pB(%pA+%#" PRIx64 "): "
13394 "unresolvable %s relocation against symbol `%s'"),
13395 input_bfd,
13396 input_section,
13397 (uint64_t) rel->r_offset,
13398 howto->name,
13399 h->root.root.string);
13400 return false;
13401 }
13402
13403 if (r != bfd_reloc_ok)
13404 {
13405 switch (r)
13406 {
13407 case bfd_reloc_overflow:
13408 /* If the overflowing reloc was to an undefined symbol,
13409 we have already printed one error message and there
13410 is no point complaining again. */
13411 if (!h || h->root.type != bfd_link_hash_undefined)
13412 (*info->callbacks->reloc_overflow)
13413 (info, (h ? &h->root : NULL), name, howto->name,
13414 (bfd_vma) 0, input_bfd, input_section, rel->r_offset);
13415 break;
13416
13417 case bfd_reloc_undefined:
13418 (*info->callbacks->undefined_symbol)
13419 (info, name, input_bfd, input_section, rel->r_offset, true);
13420 break;
13421
13422 case bfd_reloc_outofrange:
13423 error_message = _("out of range");
13424 goto common_error;
13425
13426 case bfd_reloc_notsupported:
13427 error_message = _("unsupported relocation");
13428 goto common_error;
13429
13430 case bfd_reloc_dangerous:
13431 /* error_message should already be set. */
13432 goto common_error;
13433
13434 default:
13435 error_message = _("unknown error");
13436 /* Fall through. */
13437
13438 common_error:
13439 BFD_ASSERT (error_message != NULL);
13440 (*info->callbacks->reloc_dangerous)
13441 (info, error_message, input_bfd, input_section, rel->r_offset);
13442 break;
13443 }
13444 }
13445 }
13446
13447 return true;
13448 }
13449
13450 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
13451 adds the edit to the start of the list. (The list must be built in order of
13452 ascending TINDEX: the function's callers are primarily responsible for
13453 maintaining that condition). */
13454
13455 static void
13456 add_unwind_table_edit (arm_unwind_table_edit **head,
13457 arm_unwind_table_edit **tail,
13458 arm_unwind_edit_type type,
13459 asection *linked_section,
13460 unsigned int tindex)
13461 {
13462 arm_unwind_table_edit *new_edit = (arm_unwind_table_edit *)
13463 xmalloc (sizeof (arm_unwind_table_edit));
13464
13465 new_edit->type = type;
13466 new_edit->linked_section = linked_section;
13467 new_edit->index = tindex;
13468
13469 if (tindex > 0)
13470 {
13471 new_edit->next = NULL;
13472
13473 if (*tail)
13474 (*tail)->next = new_edit;
13475
13476 (*tail) = new_edit;
13477
13478 if (!*head)
13479 (*head) = new_edit;
13480 }
13481 else
13482 {
13483 new_edit->next = *head;
13484
13485 if (!*tail)
13486 *tail = new_edit;
13487
13488 *head = new_edit;
13489 }
13490 }
13491
13492 static _arm_elf_section_data *get_arm_elf_section_data (asection *);
13493
13494 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13495
13496 static void
13497 adjust_exidx_size (asection *exidx_sec, int adjust)
13498 {
13499 asection *out_sec;
13500
13501 if (!exidx_sec->rawsize)
13502 exidx_sec->rawsize = exidx_sec->size;
13503
13504 bfd_set_section_size (exidx_sec, exidx_sec->size + adjust);
13505 out_sec = exidx_sec->output_section;
13506 /* Adjust size of output section. */
13507 bfd_set_section_size (out_sec, out_sec->size + adjust);
13508 }
13509
13510 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13511
13512 static void
13513 insert_cantunwind_after (asection *text_sec, asection *exidx_sec)
13514 {
13515 struct _arm_elf_section_data *exidx_arm_data;
13516
13517 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13518 add_unwind_table_edit
13519 (&exidx_arm_data->u.exidx.unwind_edit_list,
13520 &exidx_arm_data->u.exidx.unwind_edit_tail,
13521 INSERT_EXIDX_CANTUNWIND_AT_END, text_sec, UINT_MAX);
13522
13523 exidx_arm_data->additional_reloc_count++;
13524
13525 adjust_exidx_size (exidx_sec, 8);
13526 }
13527
13528 /* Scan .ARM.exidx tables, and create a list describing edits which should be
13529 made to those tables, such that:
13530
13531 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13532 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
13533 codes which have been inlined into the index).
13534
13535 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13536
13537 The edits are applied when the tables are written
13538 (in elf32_arm_write_section). */
13539
13540 bool
13541 elf32_arm_fix_exidx_coverage (asection **text_section_order,
13542 unsigned int num_text_sections,
13543 struct bfd_link_info *info,
13544 bool merge_exidx_entries)
13545 {
13546 bfd *inp;
13547 unsigned int last_second_word = 0, i;
13548 asection *last_exidx_sec = NULL;
13549 asection *last_text_sec = NULL;
13550 int last_unwind_type = -1;
13551
13552 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13553 text sections. */
13554 for (inp = info->input_bfds; inp != NULL; inp = inp->link.next)
13555 {
13556 asection *sec;
13557
13558 for (sec = inp->sections; sec != NULL; sec = sec->next)
13559 {
13560 struct bfd_elf_section_data *elf_sec = elf_section_data (sec);
13561 Elf_Internal_Shdr *hdr = &elf_sec->this_hdr;
13562
13563 if (!hdr || hdr->sh_type != SHT_ARM_EXIDX)
13564 continue;
13565
13566 if (elf_sec->linked_to)
13567 {
13568 Elf_Internal_Shdr *linked_hdr
13569 = &elf_section_data (elf_sec->linked_to)->this_hdr;
13570 struct _arm_elf_section_data *linked_sec_arm_data
13571 = get_arm_elf_section_data (linked_hdr->bfd_section);
13572
13573 if (linked_sec_arm_data == NULL)
13574 continue;
13575
13576 /* Link this .ARM.exidx section back from the text section it
13577 describes. */
13578 linked_sec_arm_data->u.text.arm_exidx_sec = sec;
13579 }
13580 }
13581 }
13582
13583 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13584 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
13585 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
13586
13587 for (i = 0; i < num_text_sections; i++)
13588 {
13589 asection *sec = text_section_order[i];
13590 asection *exidx_sec;
13591 struct _arm_elf_section_data *arm_data = get_arm_elf_section_data (sec);
13592 struct _arm_elf_section_data *exidx_arm_data;
13593 bfd_byte *contents = NULL;
13594 int deleted_exidx_bytes = 0;
13595 bfd_vma j;
13596 arm_unwind_table_edit *unwind_edit_head = NULL;
13597 arm_unwind_table_edit *unwind_edit_tail = NULL;
13598 Elf_Internal_Shdr *hdr;
13599 bfd *ibfd;
13600
13601 if (arm_data == NULL)
13602 continue;
13603
13604 exidx_sec = arm_data->u.text.arm_exidx_sec;
13605 if (exidx_sec == NULL)
13606 {
13607 /* Section has no unwind data. */
13608 if (last_unwind_type == 0 || !last_exidx_sec)
13609 continue;
13610
13611 /* Ignore zero sized sections. */
13612 if (sec->size == 0)
13613 continue;
13614
13615 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13616 last_unwind_type = 0;
13617 continue;
13618 }
13619
13620 /* Skip /DISCARD/ sections. */
13621 if (bfd_is_abs_section (exidx_sec->output_section))
13622 continue;
13623
13624 hdr = &elf_section_data (exidx_sec)->this_hdr;
13625 if (hdr->sh_type != SHT_ARM_EXIDX)
13626 continue;
13627
13628 exidx_arm_data = get_arm_elf_section_data (exidx_sec);
13629 if (exidx_arm_data == NULL)
13630 continue;
13631
13632 ibfd = exidx_sec->owner;
13633
13634 if (hdr->contents != NULL)
13635 contents = hdr->contents;
13636 else if (! bfd_malloc_and_get_section (ibfd, exidx_sec, &contents))
13637 /* An error? */
13638 continue;
13639
13640 if (last_unwind_type > 0)
13641 {
13642 unsigned int first_word = bfd_get_32 (ibfd, contents);
13643 /* Add cantunwind if first unwind item does not match section
13644 start. */
13645 if (first_word != sec->vma)
13646 {
13647 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13648 last_unwind_type = 0;
13649 }
13650 }
13651
13652 for (j = 0; j < hdr->sh_size; j += 8)
13653 {
13654 unsigned int second_word = bfd_get_32 (ibfd, contents + j + 4);
13655 int unwind_type;
13656 int elide = 0;
13657
13658 /* An EXIDX_CANTUNWIND entry. */
13659 if (second_word == 1)
13660 {
13661 if (last_unwind_type == 0)
13662 elide = 1;
13663 unwind_type = 0;
13664 }
13665 /* Inlined unwinding data. Merge if equal to previous. */
13666 else if ((second_word & 0x80000000) != 0)
13667 {
13668 if (merge_exidx_entries
13669 && last_second_word == second_word && last_unwind_type == 1)
13670 elide = 1;
13671 unwind_type = 1;
13672 last_second_word = second_word;
13673 }
13674 /* Normal table entry. In theory we could merge these too,
13675 but duplicate entries are likely to be much less common. */
13676 else
13677 unwind_type = 2;
13678
13679 if (elide && !bfd_link_relocatable (info))
13680 {
13681 add_unwind_table_edit (&unwind_edit_head, &unwind_edit_tail,
13682 DELETE_EXIDX_ENTRY, NULL, j / 8);
13683
13684 deleted_exidx_bytes += 8;
13685 }
13686
13687 last_unwind_type = unwind_type;
13688 }
13689
13690 /* Free contents if we allocated it ourselves. */
13691 if (contents != hdr->contents)
13692 free (contents);
13693
13694 /* Record edits to be applied later (in elf32_arm_write_section). */
13695 exidx_arm_data->u.exidx.unwind_edit_list = unwind_edit_head;
13696 exidx_arm_data->u.exidx.unwind_edit_tail = unwind_edit_tail;
13697
13698 if (deleted_exidx_bytes > 0)
13699 adjust_exidx_size (exidx_sec, - deleted_exidx_bytes);
13700
13701 last_exidx_sec = exidx_sec;
13702 last_text_sec = sec;
13703 }
13704
13705 /* Add terminating CANTUNWIND entry. */
13706 if (!bfd_link_relocatable (info) && last_exidx_sec
13707 && last_unwind_type != 0)
13708 insert_cantunwind_after (last_text_sec, last_exidx_sec);
13709
13710 return true;
13711 }
13712
13713 static bool
13714 elf32_arm_output_glue_section (struct bfd_link_info *info, bfd *obfd,
13715 bfd *ibfd, const char *name)
13716 {
13717 asection *sec, *osec;
13718
13719 sec = bfd_get_linker_section (ibfd, name);
13720 if (sec == NULL || (sec->flags & SEC_EXCLUDE) != 0)
13721 return true;
13722
13723 osec = sec->output_section;
13724 if (elf32_arm_write_section (obfd, info, sec, sec->contents))
13725 return true;
13726
13727 if (! bfd_set_section_contents (obfd, osec, sec->contents,
13728 sec->output_offset, sec->size))
13729 return false;
13730
13731 return true;
13732 }
13733
13734 static bool
13735 elf32_arm_final_link (bfd *abfd, struct bfd_link_info *info)
13736 {
13737 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
13738 asection *sec, *osec;
13739
13740 if (globals == NULL)
13741 return false;
13742
13743 /* Invoke the regular ELF backend linker to do all the work. */
13744 if (!bfd_elf_final_link (abfd, info))
13745 return false;
13746
13747 /* Process stub sections (eg BE8 encoding, ...). */
13748 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
13749 unsigned int i;
13750 for (i=0; i<htab->top_id; i++)
13751 {
13752 sec = htab->stub_group[i].stub_sec;
13753 /* Only process it once, in its link_sec slot. */
13754 if (sec && i == htab->stub_group[i].link_sec->id)
13755 {
13756 osec = sec->output_section;
13757 elf32_arm_write_section (abfd, info, sec, sec->contents);
13758 if (! bfd_set_section_contents (abfd, osec, sec->contents,
13759 sec->output_offset, sec->size))
13760 return false;
13761 }
13762 }
13763
13764 /* Write out any glue sections now that we have created all the
13765 stubs. */
13766 if (globals->bfd_of_glue_owner != NULL)
13767 {
13768 if (! elf32_arm_output_glue_section (info, abfd,
13769 globals->bfd_of_glue_owner,
13770 ARM2THUMB_GLUE_SECTION_NAME))
13771 return false;
13772
13773 if (! elf32_arm_output_glue_section (info, abfd,
13774 globals->bfd_of_glue_owner,
13775 THUMB2ARM_GLUE_SECTION_NAME))
13776 return false;
13777
13778 if (! elf32_arm_output_glue_section (info, abfd,
13779 globals->bfd_of_glue_owner,
13780 VFP11_ERRATUM_VENEER_SECTION_NAME))
13781 return false;
13782
13783 if (! elf32_arm_output_glue_section (info, abfd,
13784 globals->bfd_of_glue_owner,
13785 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13786 return false;
13787
13788 if (! elf32_arm_output_glue_section (info, abfd,
13789 globals->bfd_of_glue_owner,
13790 ARM_BX_GLUE_SECTION_NAME))
13791 return false;
13792 }
13793
13794 return true;
13795 }
13796
13797 /* Return a best guess for the machine number based on the attributes. */
13798
13799 static unsigned int
13800 bfd_arm_get_mach_from_attributes (bfd * abfd)
13801 {
13802 int arch = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_CPU_arch);
13803
13804 switch (arch)
13805 {
13806 case TAG_CPU_ARCH_PRE_V4: return bfd_mach_arm_3M;
13807 case TAG_CPU_ARCH_V4: return bfd_mach_arm_4;
13808 case TAG_CPU_ARCH_V4T: return bfd_mach_arm_4T;
13809 case TAG_CPU_ARCH_V5T: return bfd_mach_arm_5T;
13810
13811 case TAG_CPU_ARCH_V5TE:
13812 {
13813 char * name;
13814
13815 BFD_ASSERT (Tag_CPU_name < NUM_KNOWN_OBJ_ATTRIBUTES);
13816 name = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_CPU_name].s;
13817
13818 if (name)
13819 {
13820 if (strcmp (name, "IWMMXT2") == 0)
13821 return bfd_mach_arm_iWMMXt2;
13822
13823 if (strcmp (name, "IWMMXT") == 0)
13824 return bfd_mach_arm_iWMMXt;
13825
13826 if (strcmp (name, "XSCALE") == 0)
13827 {
13828 int wmmx;
13829
13830 BFD_ASSERT (Tag_WMMX_arch < NUM_KNOWN_OBJ_ATTRIBUTES);
13831 wmmx = elf_known_obj_attributes (abfd) [OBJ_ATTR_PROC][Tag_WMMX_arch].i;
13832 switch (wmmx)
13833 {
13834 case 1: return bfd_mach_arm_iWMMXt;
13835 case 2: return bfd_mach_arm_iWMMXt2;
13836 default: return bfd_mach_arm_XScale;
13837 }
13838 }
13839 }
13840
13841 return bfd_mach_arm_5TE;
13842 }
13843
13844 case TAG_CPU_ARCH_V5TEJ:
13845 return bfd_mach_arm_5TEJ;
13846 case TAG_CPU_ARCH_V6:
13847 return bfd_mach_arm_6;
13848 case TAG_CPU_ARCH_V6KZ:
13849 return bfd_mach_arm_6KZ;
13850 case TAG_CPU_ARCH_V6T2:
13851 return bfd_mach_arm_6T2;
13852 case TAG_CPU_ARCH_V6K:
13853 return bfd_mach_arm_6K;
13854 case TAG_CPU_ARCH_V7:
13855 return bfd_mach_arm_7;
13856 case TAG_CPU_ARCH_V6_M:
13857 return bfd_mach_arm_6M;
13858 case TAG_CPU_ARCH_V6S_M:
13859 return bfd_mach_arm_6SM;
13860 case TAG_CPU_ARCH_V7E_M:
13861 return bfd_mach_arm_7EM;
13862 case TAG_CPU_ARCH_V8:
13863 return bfd_mach_arm_8;
13864 case TAG_CPU_ARCH_V8R:
13865 return bfd_mach_arm_8R;
13866 case TAG_CPU_ARCH_V8M_BASE:
13867 return bfd_mach_arm_8M_BASE;
13868 case TAG_CPU_ARCH_V8M_MAIN:
13869 return bfd_mach_arm_8M_MAIN;
13870 case TAG_CPU_ARCH_V8_1M_MAIN:
13871 return bfd_mach_arm_8_1M_MAIN;
13872 case TAG_CPU_ARCH_V9:
13873 return bfd_mach_arm_9;
13874
13875 default:
13876 /* Force entry to be added for any new known Tag_CPU_arch value. */
13877 BFD_ASSERT (arch > MAX_TAG_CPU_ARCH);
13878
13879 /* Unknown Tag_CPU_arch value. */
13880 return bfd_mach_arm_unknown;
13881 }
13882 }
13883
13884 /* Set the right machine number. */
13885
13886 static bool
13887 elf32_arm_object_p (bfd *abfd)
13888 {
13889 unsigned int mach;
13890
13891 mach = bfd_arm_get_mach_from_notes (abfd, ARM_NOTE_SECTION);
13892
13893 if (mach == bfd_mach_arm_unknown)
13894 {
13895 if (elf_elfheader (abfd)->e_flags & EF_ARM_MAVERICK_FLOAT)
13896 mach = bfd_mach_arm_ep9312;
13897 else
13898 mach = bfd_arm_get_mach_from_attributes (abfd);
13899 }
13900
13901 bfd_default_set_arch_mach (abfd, bfd_arch_arm, mach);
13902 return true;
13903 }
13904
13905 /* Function to keep ARM specific flags in the ELF header. */
13906
13907 static bool
13908 elf32_arm_set_private_flags (bfd *abfd, flagword flags)
13909 {
13910 if (elf_flags_init (abfd)
13911 && elf_elfheader (abfd)->e_flags != flags)
13912 {
13913 if (EF_ARM_EABI_VERSION (flags) == EF_ARM_EABI_UNKNOWN)
13914 {
13915 if (flags & EF_ARM_INTERWORK)
13916 _bfd_error_handler
13917 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
13918 abfd);
13919 else
13920 _bfd_error_handler
13921 (_("warning: clearing the interworking flag of %pB due to outside request"),
13922 abfd);
13923 }
13924 }
13925 else
13926 {
13927 elf_elfheader (abfd)->e_flags = flags;
13928 elf_flags_init (abfd) = true;
13929 }
13930
13931 return true;
13932 }
13933
13934 /* Copy backend specific data from one object module to another. */
13935
13936 static bool
13937 elf32_arm_copy_private_bfd_data (bfd *ibfd, bfd *obfd)
13938 {
13939 flagword in_flags;
13940 flagword out_flags;
13941
13942 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
13943 return true;
13944
13945 in_flags = elf_elfheader (ibfd)->e_flags;
13946 out_flags = elf_elfheader (obfd)->e_flags;
13947
13948 if (elf_flags_init (obfd)
13949 && EF_ARM_EABI_VERSION (out_flags) == EF_ARM_EABI_UNKNOWN
13950 && in_flags != out_flags)
13951 {
13952 /* Cannot mix APCS26 and APCS32 code. */
13953 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
13954 return false;
13955
13956 /* Cannot mix float APCS and non-float APCS code. */
13957 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
13958 return false;
13959
13960 /* If the src and dest have different interworking flags
13961 then turn off the interworking bit. */
13962 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
13963 {
13964 if (out_flags & EF_ARM_INTERWORK)
13965 _bfd_error_handler
13966 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
13967 obfd, ibfd);
13968
13969 in_flags &= ~EF_ARM_INTERWORK;
13970 }
13971
13972 /* Likewise for PIC, though don't warn for this case. */
13973 if ((in_flags & EF_ARM_PIC) != (out_flags & EF_ARM_PIC))
13974 in_flags &= ~EF_ARM_PIC;
13975 }
13976
13977 elf_elfheader (obfd)->e_flags = in_flags;
13978 elf_flags_init (obfd) = true;
13979
13980 return _bfd_elf_copy_private_bfd_data (ibfd, obfd);
13981 }
13982
13983 /* Values for Tag_ABI_PCS_R9_use. */
13984 enum
13985 {
13986 AEABI_R9_V6,
13987 AEABI_R9_SB,
13988 AEABI_R9_TLS,
13989 AEABI_R9_unused
13990 };
13991
13992 /* Values for Tag_ABI_PCS_RW_data. */
13993 enum
13994 {
13995 AEABI_PCS_RW_data_absolute,
13996 AEABI_PCS_RW_data_PCrel,
13997 AEABI_PCS_RW_data_SBrel,
13998 AEABI_PCS_RW_data_unused
13999 };
14000
14001 /* Values for Tag_ABI_enum_size. */
14002 enum
14003 {
14004 AEABI_enum_unused,
14005 AEABI_enum_short,
14006 AEABI_enum_wide,
14007 AEABI_enum_forced_wide
14008 };
14009
14010 /* Determine whether an object attribute tag takes an integer, a
14011 string or both. */
14012
14013 static int
14014 elf32_arm_obj_attrs_arg_type (int tag)
14015 {
14016 if (tag == Tag_compatibility)
14017 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_STR_VAL;
14018 else if (tag == Tag_nodefaults)
14019 return ATTR_TYPE_FLAG_INT_VAL | ATTR_TYPE_FLAG_NO_DEFAULT;
14020 else if (tag == Tag_CPU_raw_name || tag == Tag_CPU_name)
14021 return ATTR_TYPE_FLAG_STR_VAL;
14022 else if (tag < 32)
14023 return ATTR_TYPE_FLAG_INT_VAL;
14024 else
14025 return (tag & 1) != 0 ? ATTR_TYPE_FLAG_STR_VAL : ATTR_TYPE_FLAG_INT_VAL;
14026 }
14027
14028 /* The ABI defines that Tag_conformance should be emitted first, and that
14029 Tag_nodefaults should be second (if either is defined). This sets those
14030 two positions, and bumps up the position of all the remaining tags to
14031 compensate. */
14032 static int
14033 elf32_arm_obj_attrs_order (int num)
14034 {
14035 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE)
14036 return Tag_conformance;
14037 if (num == LEAST_KNOWN_OBJ_ATTRIBUTE + 1)
14038 return Tag_nodefaults;
14039 if ((num - 2) < Tag_nodefaults)
14040 return num - 2;
14041 if ((num - 1) < Tag_conformance)
14042 return num - 1;
14043 return num;
14044 }
14045
14046 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
14047 static bool
14048 elf32_arm_obj_attrs_handle_unknown (bfd *abfd, int tag)
14049 {
14050 if ((tag & 127) < 64)
14051 {
14052 _bfd_error_handler
14053 (_("%pB: unknown mandatory EABI object attribute %d"),
14054 abfd, tag);
14055 bfd_set_error (bfd_error_bad_value);
14056 return false;
14057 }
14058 else
14059 {
14060 _bfd_error_handler
14061 (_("warning: %pB: unknown EABI object attribute %d"),
14062 abfd, tag);
14063 return true;
14064 }
14065 }
14066
14067 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
14068 Returns -1 if no architecture could be read. */
14069
14070 static int
14071 get_secondary_compatible_arch (bfd *abfd)
14072 {
14073 obj_attribute *attr =
14074 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14075
14076 /* Note: the tag and its argument below are uleb128 values, though
14077 currently-defined values fit in one byte for each. */
14078 if (attr->s
14079 && attr->s[0] == Tag_CPU_arch
14080 && (attr->s[1] & 128) != 128
14081 && attr->s[2] == 0)
14082 return attr->s[1];
14083
14084 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14085 return -1;
14086 }
14087
14088 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14089 The tag is removed if ARCH is -1. */
14090
14091 static void
14092 set_secondary_compatible_arch (bfd *abfd, int arch)
14093 {
14094 obj_attribute *attr =
14095 &elf_known_obj_attributes_proc (abfd)[Tag_also_compatible_with];
14096
14097 if (arch == -1)
14098 {
14099 attr->s = NULL;
14100 return;
14101 }
14102
14103 /* Note: the tag and its argument below are uleb128 values, though
14104 currently-defined values fit in one byte for each. */
14105 if (!attr->s)
14106 attr->s = (char *) bfd_alloc (abfd, 3);
14107 attr->s[0] = Tag_CPU_arch;
14108 attr->s[1] = arch;
14109 attr->s[2] = '\0';
14110 }
14111
14112 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14113 into account. */
14114
14115 static int
14116 tag_cpu_arch_combine (bfd *ibfd, int oldtag, int *secondary_compat_out,
14117 int newtag, int secondary_compat)
14118 {
14119 #define T(X) TAG_CPU_ARCH_##X
14120 int tagl, tagh, result;
14121 const int v6t2[] =
14122 {
14123 T(V6T2), /* PRE_V4. */
14124 T(V6T2), /* V4. */
14125 T(V6T2), /* V4T. */
14126 T(V6T2), /* V5T. */
14127 T(V6T2), /* V5TE. */
14128 T(V6T2), /* V5TEJ. */
14129 T(V6T2), /* V6. */
14130 T(V7), /* V6KZ. */
14131 T(V6T2) /* V6T2. */
14132 };
14133 const int v6k[] =
14134 {
14135 T(V6K), /* PRE_V4. */
14136 T(V6K), /* V4. */
14137 T(V6K), /* V4T. */
14138 T(V6K), /* V5T. */
14139 T(V6K), /* V5TE. */
14140 T(V6K), /* V5TEJ. */
14141 T(V6K), /* V6. */
14142 T(V6KZ), /* V6KZ. */
14143 T(V7), /* V6T2. */
14144 T(V6K) /* V6K. */
14145 };
14146 const int v7[] =
14147 {
14148 T(V7), /* PRE_V4. */
14149 T(V7), /* V4. */
14150 T(V7), /* V4T. */
14151 T(V7), /* V5T. */
14152 T(V7), /* V5TE. */
14153 T(V7), /* V5TEJ. */
14154 T(V7), /* V6. */
14155 T(V7), /* V6KZ. */
14156 T(V7), /* V6T2. */
14157 T(V7), /* V6K. */
14158 T(V7) /* V7. */
14159 };
14160 const int v6_m[] =
14161 {
14162 -1, /* PRE_V4. */
14163 -1, /* V4. */
14164 T(V6K), /* V4T. */
14165 T(V6K), /* V5T. */
14166 T(V6K), /* V5TE. */
14167 T(V6K), /* V5TEJ. */
14168 T(V6K), /* V6. */
14169 T(V6KZ), /* V6KZ. */
14170 T(V7), /* V6T2. */
14171 T(V6K), /* V6K. */
14172 T(V7), /* V7. */
14173 T(V6_M) /* V6_M. */
14174 };
14175 const int v6s_m[] =
14176 {
14177 -1, /* PRE_V4. */
14178 -1, /* V4. */
14179 T(V6K), /* V4T. */
14180 T(V6K), /* V5T. */
14181 T(V6K), /* V5TE. */
14182 T(V6K), /* V5TEJ. */
14183 T(V6K), /* V6. */
14184 T(V6KZ), /* V6KZ. */
14185 T(V7), /* V6T2. */
14186 T(V6K), /* V6K. */
14187 T(V7), /* V7. */
14188 T(V6S_M), /* V6_M. */
14189 T(V6S_M) /* V6S_M. */
14190 };
14191 const int v7e_m[] =
14192 {
14193 -1, /* PRE_V4. */
14194 -1, /* V4. */
14195 T(V7E_M), /* V4T. */
14196 T(V7E_M), /* V5T. */
14197 T(V7E_M), /* V5TE. */
14198 T(V7E_M), /* V5TEJ. */
14199 T(V7E_M), /* V6. */
14200 T(V7E_M), /* V6KZ. */
14201 T(V7E_M), /* V6T2. */
14202 T(V7E_M), /* V6K. */
14203 T(V7E_M), /* V7. */
14204 T(V7E_M), /* V6_M. */
14205 T(V7E_M), /* V6S_M. */
14206 T(V7E_M) /* V7E_M. */
14207 };
14208 const int v8[] =
14209 {
14210 T(V8), /* PRE_V4. */
14211 T(V8), /* V4. */
14212 T(V8), /* V4T. */
14213 T(V8), /* V5T. */
14214 T(V8), /* V5TE. */
14215 T(V8), /* V5TEJ. */
14216 T(V8), /* V6. */
14217 T(V8), /* V6KZ. */
14218 T(V8), /* V6T2. */
14219 T(V8), /* V6K. */
14220 T(V8), /* V7. */
14221 T(V8), /* V6_M. */
14222 T(V8), /* V6S_M. */
14223 T(V8), /* V7E_M. */
14224 T(V8), /* V8. */
14225 T(V8), /* V8-R. */
14226 T(V8), /* V8-M.BASE. */
14227 T(V8), /* V8-M.MAIN. */
14228 T(V8), /* V8.1. */
14229 T(V8), /* V8.2. */
14230 T(V8), /* V8.3. */
14231 T(V8), /* V8.1-M.MAIN. */
14232 };
14233 const int v8r[] =
14234 {
14235 T(V8R), /* PRE_V4. */
14236 T(V8R), /* V4. */
14237 T(V8R), /* V4T. */
14238 T(V8R), /* V5T. */
14239 T(V8R), /* V5TE. */
14240 T(V8R), /* V5TEJ. */
14241 T(V8R), /* V6. */
14242 T(V8R), /* V6KZ. */
14243 T(V8R), /* V6T2. */
14244 T(V8R), /* V6K. */
14245 T(V8R), /* V7. */
14246 T(V8R), /* V6_M. */
14247 T(V8R), /* V6S_M. */
14248 T(V8R), /* V7E_M. */
14249 T(V8), /* V8. */
14250 T(V8R), /* V8R. */
14251 };
14252 const int v8m_baseline[] =
14253 {
14254 -1, /* PRE_V4. */
14255 -1, /* V4. */
14256 -1, /* V4T. */
14257 -1, /* V5T. */
14258 -1, /* V5TE. */
14259 -1, /* V5TEJ. */
14260 -1, /* V6. */
14261 -1, /* V6KZ. */
14262 -1, /* V6T2. */
14263 -1, /* V6K. */
14264 -1, /* V7. */
14265 T(V8M_BASE), /* V6_M. */
14266 T(V8M_BASE), /* V6S_M. */
14267 -1, /* V7E_M. */
14268 -1, /* V8. */
14269 -1, /* V8R. */
14270 T(V8M_BASE) /* V8-M BASELINE. */
14271 };
14272 const int v8m_mainline[] =
14273 {
14274 -1, /* PRE_V4. */
14275 -1, /* V4. */
14276 -1, /* V4T. */
14277 -1, /* V5T. */
14278 -1, /* V5TE. */
14279 -1, /* V5TEJ. */
14280 -1, /* V6. */
14281 -1, /* V6KZ. */
14282 -1, /* V6T2. */
14283 -1, /* V6K. */
14284 T(V8M_MAIN), /* V7. */
14285 T(V8M_MAIN), /* V6_M. */
14286 T(V8M_MAIN), /* V6S_M. */
14287 T(V8M_MAIN), /* V7E_M. */
14288 -1, /* V8. */
14289 -1, /* V8R. */
14290 T(V8M_MAIN), /* V8-M BASELINE. */
14291 T(V8M_MAIN) /* V8-M MAINLINE. */
14292 };
14293 const int v8_1m_mainline[] =
14294 {
14295 -1, /* PRE_V4. */
14296 -1, /* V4. */
14297 -1, /* V4T. */
14298 -1, /* V5T. */
14299 -1, /* V5TE. */
14300 -1, /* V5TEJ. */
14301 -1, /* V6. */
14302 -1, /* V6KZ. */
14303 -1, /* V6T2. */
14304 -1, /* V6K. */
14305 T(V8_1M_MAIN), /* V7. */
14306 T(V8_1M_MAIN), /* V6_M. */
14307 T(V8_1M_MAIN), /* V6S_M. */
14308 T(V8_1M_MAIN), /* V7E_M. */
14309 -1, /* V8. */
14310 -1, /* V8R. */
14311 T(V8_1M_MAIN), /* V8-M BASELINE. */
14312 T(V8_1M_MAIN), /* V8-M MAINLINE. */
14313 -1, /* Unused (18). */
14314 -1, /* Unused (19). */
14315 -1, /* Unused (20). */
14316 T(V8_1M_MAIN) /* V8.1-M MAINLINE. */
14317 };
14318 const int v9[] =
14319 {
14320 T(V9), /* PRE_V4. */
14321 T(V9), /* V4. */
14322 T(V9), /* V4T. */
14323 T(V9), /* V5T. */
14324 T(V9), /* V5TE. */
14325 T(V9), /* V5TEJ. */
14326 T(V9), /* V6. */
14327 T(V9), /* V6KZ. */
14328 T(V9), /* V6T2. */
14329 T(V9), /* V6K. */
14330 T(V9), /* V7. */
14331 T(V9), /* V6_M. */
14332 T(V9), /* V6S_M. */
14333 T(V9), /* V7E_M. */
14334 T(V9), /* V8. */
14335 T(V9), /* V8-R. */
14336 T(V9), /* V8-M.BASE. */
14337 T(V9), /* V8-M.MAIN. */
14338 T(V9), /* V8.1. */
14339 T(V9), /* V8.2. */
14340 T(V9), /* V8.3. */
14341 T(V9), /* V8.1-M.MAIN. */
14342 T(V9), /* V9. */
14343 };
14344 const int v4t_plus_v6_m[] =
14345 {
14346 -1, /* PRE_V4. */
14347 -1, /* V4. */
14348 T(V4T), /* V4T. */
14349 T(V5T), /* V5T. */
14350 T(V5TE), /* V5TE. */
14351 T(V5TEJ), /* V5TEJ. */
14352 T(V6), /* V6. */
14353 T(V6KZ), /* V6KZ. */
14354 T(V6T2), /* V6T2. */
14355 T(V6K), /* V6K. */
14356 T(V7), /* V7. */
14357 T(V6_M), /* V6_M. */
14358 T(V6S_M), /* V6S_M. */
14359 T(V7E_M), /* V7E_M. */
14360 T(V8), /* V8. */
14361 -1, /* V8R. */
14362 T(V8M_BASE), /* V8-M BASELINE. */
14363 T(V8M_MAIN), /* V8-M MAINLINE. */
14364 -1, /* Unused (18). */
14365 -1, /* Unused (19). */
14366 -1, /* Unused (20). */
14367 T(V8_1M_MAIN), /* V8.1-M MAINLINE. */
14368 T(V9), /* V9. */
14369 T(V4T_PLUS_V6_M) /* V4T plus V6_M. */
14370 };
14371 const int *comb[] =
14372 {
14373 v6t2,
14374 v6k,
14375 v7,
14376 v6_m,
14377 v6s_m,
14378 v7e_m,
14379 v8,
14380 v8r,
14381 v8m_baseline,
14382 v8m_mainline,
14383 NULL,
14384 NULL,
14385 NULL,
14386 v8_1m_mainline,
14387 v9,
14388 /* Pseudo-architecture. */
14389 v4t_plus_v6_m
14390 };
14391
14392 /* Check we've not got a higher architecture than we know about. */
14393
14394 if (oldtag > MAX_TAG_CPU_ARCH || newtag > MAX_TAG_CPU_ARCH)
14395 {
14396 _bfd_error_handler (_("error: %pB: unknown CPU architecture"), ibfd);
14397 return -1;
14398 }
14399
14400 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14401
14402 if ((oldtag == T(V6_M) && *secondary_compat_out == T(V4T))
14403 || (oldtag == T(V4T) && *secondary_compat_out == T(V6_M)))
14404 oldtag = T(V4T_PLUS_V6_M);
14405
14406 /* And override the new tag if we have a Tag_also_compatible_with on the
14407 input. */
14408
14409 if ((newtag == T(V6_M) && secondary_compat == T(V4T))
14410 || (newtag == T(V4T) && secondary_compat == T(V6_M)))
14411 newtag = T(V4T_PLUS_V6_M);
14412
14413 tagl = (oldtag < newtag) ? oldtag : newtag;
14414 result = tagh = (oldtag > newtag) ? oldtag : newtag;
14415
14416 /* Architectures before V6KZ add features monotonically. */
14417 if (tagh <= TAG_CPU_ARCH_V6KZ)
14418 return result;
14419
14420 result = comb[tagh - T(V6T2)] ? comb[tagh - T(V6T2)][tagl] : -1;
14421
14422 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14423 as the canonical version. */
14424 if (result == T(V4T_PLUS_V6_M))
14425 {
14426 result = T(V4T);
14427 *secondary_compat_out = T(V6_M);
14428 }
14429 else
14430 *secondary_compat_out = -1;
14431
14432 if (result == -1)
14433 {
14434 _bfd_error_handler (_("error: %pB: conflicting CPU architectures %d/%d"),
14435 ibfd, oldtag, newtag);
14436 return -1;
14437 }
14438
14439 return result;
14440 #undef T
14441 }
14442
14443 /* Query attributes object to see if integer divide instructions may be
14444 present in an object. */
14445 static bool
14446 elf32_arm_attributes_accept_div (const obj_attribute *attr)
14447 {
14448 int arch = attr[Tag_CPU_arch].i;
14449 int profile = attr[Tag_CPU_arch_profile].i;
14450
14451 switch (attr[Tag_DIV_use].i)
14452 {
14453 case 0:
14454 /* Integer divide allowed if instruction contained in archetecture. */
14455 if (arch == TAG_CPU_ARCH_V7 && (profile == 'R' || profile == 'M'))
14456 return true;
14457 else if (arch >= TAG_CPU_ARCH_V7E_M)
14458 return true;
14459 else
14460 return false;
14461
14462 case 1:
14463 /* Integer divide explicitly prohibited. */
14464 return false;
14465
14466 default:
14467 /* Unrecognised case - treat as allowing divide everywhere. */
14468 case 2:
14469 /* Integer divide allowed in ARM state. */
14470 return true;
14471 }
14472 }
14473
14474 /* Query attributes object to see if integer divide instructions are
14475 forbidden to be in the object. This is not the inverse of
14476 elf32_arm_attributes_accept_div. */
14477 static bool
14478 elf32_arm_attributes_forbid_div (const obj_attribute *attr)
14479 {
14480 return attr[Tag_DIV_use].i == 1;
14481 }
14482
14483 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14484 are conflicting attributes. */
14485
14486 static bool
14487 elf32_arm_merge_eabi_attributes (bfd *ibfd, struct bfd_link_info *info)
14488 {
14489 bfd *obfd = info->output_bfd;
14490 obj_attribute *in_attr;
14491 obj_attribute *out_attr;
14492 /* Some tags have 0 = don't care, 1 = strong requirement,
14493 2 = weak requirement. */
14494 static const int order_021[3] = {0, 2, 1};
14495 int i;
14496 bool result = true;
14497 const char *sec_name = get_elf_backend_data (ibfd)->obj_attrs_section;
14498
14499 /* Skip the linker stubs file. This preserves previous behavior
14500 of accepting unknown attributes in the first input file - but
14501 is that a bug? */
14502 if (ibfd->flags & BFD_LINKER_CREATED)
14503 return true;
14504
14505 /* Skip any input that hasn't attribute section.
14506 This enables to link object files without attribute section with
14507 any others. */
14508 if (bfd_get_section_by_name (ibfd, sec_name) == NULL)
14509 return true;
14510
14511 if (!elf_known_obj_attributes_proc (obfd)[0].i)
14512 {
14513 /* This is the first object. Copy the attributes. */
14514 _bfd_elf_copy_obj_attributes (ibfd, obfd);
14515
14516 out_attr = elf_known_obj_attributes_proc (obfd);
14517
14518 /* Use the Tag_null value to indicate the attributes have been
14519 initialized. */
14520 out_attr[0].i = 1;
14521
14522 /* We do not output objects with Tag_MPextension_use_legacy - we move
14523 the attribute's value to Tag_MPextension_use. */
14524 if (out_attr[Tag_MPextension_use_legacy].i != 0)
14525 {
14526 if (out_attr[Tag_MPextension_use].i != 0
14527 && out_attr[Tag_MPextension_use_legacy].i
14528 != out_attr[Tag_MPextension_use].i)
14529 {
14530 _bfd_error_handler
14531 (_("Error: %pB has both the current and legacy "
14532 "Tag_MPextension_use attributes"), ibfd);
14533 result = false;
14534 }
14535
14536 out_attr[Tag_MPextension_use] =
14537 out_attr[Tag_MPextension_use_legacy];
14538 out_attr[Tag_MPextension_use_legacy].type = 0;
14539 out_attr[Tag_MPextension_use_legacy].i = 0;
14540 }
14541
14542 /* PR 28859 and 28848: Handle the case where the first input file,
14543 eg crti.o, has a Tag_ABI_HardFP_use of 3 but no Tag_FP_arch set.
14544 Using Tag_ABI_HardFP_use in this way is deprecated, so reset the
14545 attribute to zero.
14546 FIXME: Should we handle other non-zero values of Tag_ABI_HardFO_use ? */
14547 if (out_attr[Tag_ABI_HardFP_use].i == 3 && out_attr[Tag_FP_arch].i == 0)
14548 out_attr[Tag_ABI_HardFP_use].i = 0;
14549
14550 return result;
14551 }
14552
14553 in_attr = elf_known_obj_attributes_proc (ibfd);
14554 out_attr = elf_known_obj_attributes_proc (obfd);
14555 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14556 if (in_attr[Tag_ABI_VFP_args].i != out_attr[Tag_ABI_VFP_args].i)
14557 {
14558 /* Ignore mismatches if the object doesn't use floating point or is
14559 floating point ABI independent. */
14560 if (out_attr[Tag_ABI_FP_number_model].i == AEABI_FP_number_model_none
14561 || (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14562 && out_attr[Tag_ABI_VFP_args].i == AEABI_VFP_args_compatible))
14563 out_attr[Tag_ABI_VFP_args].i = in_attr[Tag_ABI_VFP_args].i;
14564 else if (in_attr[Tag_ABI_FP_number_model].i != AEABI_FP_number_model_none
14565 && in_attr[Tag_ABI_VFP_args].i != AEABI_VFP_args_compatible)
14566 {
14567 _bfd_error_handler
14568 (_("error: %pB uses VFP register arguments, %pB does not"),
14569 in_attr[Tag_ABI_VFP_args].i ? ibfd : obfd,
14570 in_attr[Tag_ABI_VFP_args].i ? obfd : ibfd);
14571 result = false;
14572 }
14573 }
14574
14575 for (i = LEAST_KNOWN_OBJ_ATTRIBUTE; i < NUM_KNOWN_OBJ_ATTRIBUTES; i++)
14576 {
14577 /* Merge this attribute with existing attributes. */
14578 switch (i)
14579 {
14580 case Tag_CPU_raw_name:
14581 case Tag_CPU_name:
14582 /* These are merged after Tag_CPU_arch. */
14583 break;
14584
14585 case Tag_ABI_optimization_goals:
14586 case Tag_ABI_FP_optimization_goals:
14587 /* Use the first value seen. */
14588 break;
14589
14590 case Tag_CPU_arch:
14591 {
14592 int secondary_compat = -1, secondary_compat_out = -1;
14593 unsigned int saved_out_attr = out_attr[i].i;
14594 int arch_attr;
14595 static const char *name_table[] =
14596 {
14597 /* These aren't real CPU names, but we can't guess
14598 that from the architecture version alone. */
14599 "Pre v4",
14600 "ARM v4",
14601 "ARM v4T",
14602 "ARM v5T",
14603 "ARM v5TE",
14604 "ARM v5TEJ",
14605 "ARM v6",
14606 "ARM v6KZ",
14607 "ARM v6T2",
14608 "ARM v6K",
14609 "ARM v7",
14610 "ARM v6-M",
14611 "ARM v6S-M",
14612 "ARM v7E-M",
14613 "ARM v8",
14614 "ARM v8-R",
14615 "ARM v8-M.baseline",
14616 "ARM v8-M.mainline",
14617 "ARM v8.1-A",
14618 "ARM v8.2-A",
14619 "ARM v8.3-A",
14620 "ARM v8.1-M.mainline",
14621 "ARM v9",
14622 };
14623
14624 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14625 secondary_compat = get_secondary_compatible_arch (ibfd);
14626 secondary_compat_out = get_secondary_compatible_arch (obfd);
14627 arch_attr = tag_cpu_arch_combine (ibfd, out_attr[i].i,
14628 &secondary_compat_out,
14629 in_attr[i].i,
14630 secondary_compat);
14631
14632 /* Return with error if failed to merge. */
14633 if (arch_attr == -1)
14634 return false;
14635
14636 out_attr[i].i = arch_attr;
14637
14638 set_secondary_compatible_arch (obfd, secondary_compat_out);
14639
14640 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14641 if (out_attr[i].i == saved_out_attr)
14642 ; /* Leave the names alone. */
14643 else if (out_attr[i].i == in_attr[i].i)
14644 {
14645 /* The output architecture has been changed to match the
14646 input architecture. Use the input names. */
14647 out_attr[Tag_CPU_name].s = in_attr[Tag_CPU_name].s
14648 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_name].s)
14649 : NULL;
14650 out_attr[Tag_CPU_raw_name].s = in_attr[Tag_CPU_raw_name].s
14651 ? _bfd_elf_attr_strdup (obfd, in_attr[Tag_CPU_raw_name].s)
14652 : NULL;
14653 }
14654 else
14655 {
14656 out_attr[Tag_CPU_name].s = NULL;
14657 out_attr[Tag_CPU_raw_name].s = NULL;
14658 }
14659
14660 /* If we still don't have a value for Tag_CPU_name,
14661 make one up now. Tag_CPU_raw_name remains blank. */
14662 if (out_attr[Tag_CPU_name].s == NULL
14663 && out_attr[i].i < ARRAY_SIZE (name_table))
14664 out_attr[Tag_CPU_name].s =
14665 _bfd_elf_attr_strdup (obfd, name_table[out_attr[i].i]);
14666 }
14667 break;
14668
14669 case Tag_ARM_ISA_use:
14670 case Tag_THUMB_ISA_use:
14671 case Tag_WMMX_arch:
14672 case Tag_Advanced_SIMD_arch:
14673 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
14674 case Tag_ABI_FP_rounding:
14675 case Tag_ABI_FP_exceptions:
14676 case Tag_ABI_FP_user_exceptions:
14677 case Tag_ABI_FP_number_model:
14678 case Tag_FP_HP_extension:
14679 case Tag_CPU_unaligned_access:
14680 case Tag_T2EE_use:
14681 case Tag_MPextension_use:
14682 case Tag_MVE_arch:
14683 case Tag_PAC_extension:
14684 case Tag_BTI_extension:
14685 case Tag_BTI_use:
14686 case Tag_PACRET_use:
14687 /* Use the largest value specified. */
14688 if (in_attr[i].i > out_attr[i].i)
14689 out_attr[i].i = in_attr[i].i;
14690 break;
14691
14692 case Tag_ABI_align_preserved:
14693 case Tag_ABI_PCS_RO_data:
14694 /* Use the smallest value specified. */
14695 if (in_attr[i].i < out_attr[i].i)
14696 out_attr[i].i = in_attr[i].i;
14697 break;
14698
14699 case Tag_ABI_align_needed:
14700 if ((in_attr[i].i > 0 || out_attr[i].i > 0)
14701 && (in_attr[Tag_ABI_align_preserved].i == 0
14702 || out_attr[Tag_ABI_align_preserved].i == 0))
14703 {
14704 /* This error message should be enabled once all non-conformant
14705 binaries in the toolchain have had the attributes set
14706 properly.
14707 _bfd_error_handler
14708 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
14709 obfd, ibfd);
14710 result = false; */
14711 }
14712 /* Fall through. */
14713 case Tag_ABI_FP_denormal:
14714 case Tag_ABI_PCS_GOT_use:
14715 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14716 value if greater than 2 (for future-proofing). */
14717 if ((in_attr[i].i > 2 && in_attr[i].i > out_attr[i].i)
14718 || (in_attr[i].i <= 2 && out_attr[i].i <= 2
14719 && order_021[in_attr[i].i] > order_021[out_attr[i].i]))
14720 out_attr[i].i = in_attr[i].i;
14721 break;
14722
14723 case Tag_Virtualization_use:
14724 /* The virtualization tag effectively stores two bits of
14725 information: the intended use of TrustZone (in bit 0), and the
14726 intended use of Virtualization (in bit 1). */
14727 if (out_attr[i].i == 0)
14728 out_attr[i].i = in_attr[i].i;
14729 else if (in_attr[i].i != 0
14730 && in_attr[i].i != out_attr[i].i)
14731 {
14732 if (in_attr[i].i <= 3 && out_attr[i].i <= 3)
14733 out_attr[i].i = 3;
14734 else
14735 {
14736 _bfd_error_handler
14737 (_("error: %pB: unable to merge virtualization attributes "
14738 "with %pB"),
14739 obfd, ibfd);
14740 result = false;
14741 }
14742 }
14743 break;
14744
14745 case Tag_CPU_arch_profile:
14746 if (out_attr[i].i != in_attr[i].i)
14747 {
14748 /* 0 will merge with anything.
14749 'A' and 'S' merge to 'A'.
14750 'R' and 'S' merge to 'R'.
14751 'M' and 'A|R|S' is an error. */
14752 if (out_attr[i].i == 0
14753 || (out_attr[i].i == 'S'
14754 && (in_attr[i].i == 'A' || in_attr[i].i == 'R')))
14755 out_attr[i].i = in_attr[i].i;
14756 else if (in_attr[i].i == 0
14757 || (in_attr[i].i == 'S'
14758 && (out_attr[i].i == 'A' || out_attr[i].i == 'R')))
14759 ; /* Do nothing. */
14760 else
14761 {
14762 _bfd_error_handler
14763 (_("error: %pB: conflicting architecture profiles %c/%c"),
14764 ibfd,
14765 in_attr[i].i ? in_attr[i].i : '0',
14766 out_attr[i].i ? out_attr[i].i : '0');
14767 result = false;
14768 }
14769 }
14770 break;
14771
14772 case Tag_DSP_extension:
14773 /* No need to change output value if any of:
14774 - pre (<=) ARMv5T input architecture (do not have DSP)
14775 - M input profile not ARMv7E-M and do not have DSP. */
14776 if (in_attr[Tag_CPU_arch].i <= 3
14777 || (in_attr[Tag_CPU_arch_profile].i == 'M'
14778 && in_attr[Tag_CPU_arch].i != 13
14779 && in_attr[i].i == 0))
14780 ; /* Do nothing. */
14781 /* Output value should be 0 if DSP part of architecture, ie.
14782 - post (>=) ARMv5te architecture output
14783 - A, R or S profile output or ARMv7E-M output architecture. */
14784 else if (out_attr[Tag_CPU_arch].i >= 4
14785 && (out_attr[Tag_CPU_arch_profile].i == 'A'
14786 || out_attr[Tag_CPU_arch_profile].i == 'R'
14787 || out_attr[Tag_CPU_arch_profile].i == 'S'
14788 || out_attr[Tag_CPU_arch].i == 13))
14789 out_attr[i].i = 0;
14790 /* Otherwise, DSP instructions are added and not part of output
14791 architecture. */
14792 else
14793 out_attr[i].i = 1;
14794 break;
14795
14796 case Tag_FP_arch:
14797 {
14798 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14799 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14800 when it's 0. It might mean absence of FP hardware if
14801 Tag_FP_arch is zero. */
14802
14803 #define VFP_VERSION_COUNT 9
14804 static const struct
14805 {
14806 int ver;
14807 int regs;
14808 } vfp_versions[VFP_VERSION_COUNT] =
14809 {
14810 {0, 0},
14811 {1, 16},
14812 {2, 16},
14813 {3, 32},
14814 {3, 16},
14815 {4, 32},
14816 {4, 16},
14817 {8, 32},
14818 {8, 16}
14819 };
14820 int ver;
14821 int regs;
14822 int newval;
14823
14824 /* If the output has no requirement about FP hardware,
14825 follow the requirement of the input. */
14826 if (out_attr[i].i == 0)
14827 {
14828 /* This assert is still reasonable, we shouldn't
14829 produce the suspicious build attribute
14830 combination (See below for in_attr). */
14831 BFD_ASSERT (out_attr[Tag_ABI_HardFP_use].i == 0);
14832 out_attr[i].i = in_attr[i].i;
14833 out_attr[Tag_ABI_HardFP_use].i
14834 = in_attr[Tag_ABI_HardFP_use].i;
14835 break;
14836 }
14837 /* If the input has no requirement about FP hardware, do
14838 nothing. */
14839 else if (in_attr[i].i == 0)
14840 {
14841 /* We used to assert that Tag_ABI_HardFP_use was
14842 zero here, but we should never assert when
14843 consuming an object file that has suspicious
14844 build attributes. The single precision variant
14845 of 'no FP architecture' is still 'no FP
14846 architecture', so we just ignore the tag in this
14847 case. */
14848 break;
14849 }
14850
14851 /* Both the input and the output have nonzero Tag_FP_arch.
14852 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
14853
14854 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14855 do nothing. */
14856 if (in_attr[Tag_ABI_HardFP_use].i == 0
14857 && out_attr[Tag_ABI_HardFP_use].i == 0)
14858 ;
14859 /* If the input and the output have different Tag_ABI_HardFP_use,
14860 the combination of them is 0 (implied by Tag_FP_arch). */
14861 else if (in_attr[Tag_ABI_HardFP_use].i
14862 != out_attr[Tag_ABI_HardFP_use].i)
14863 out_attr[Tag_ABI_HardFP_use].i = 0;
14864
14865 /* Now we can handle Tag_FP_arch. */
14866
14867 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14868 pick the biggest. */
14869 if (in_attr[i].i >= VFP_VERSION_COUNT
14870 && in_attr[i].i > out_attr[i].i)
14871 {
14872 out_attr[i] = in_attr[i];
14873 break;
14874 }
14875 /* The output uses the superset of input features
14876 (ISA version) and registers. */
14877 ver = vfp_versions[in_attr[i].i].ver;
14878 if (ver < vfp_versions[out_attr[i].i].ver)
14879 ver = vfp_versions[out_attr[i].i].ver;
14880 regs = vfp_versions[in_attr[i].i].regs;
14881 if (regs < vfp_versions[out_attr[i].i].regs)
14882 regs = vfp_versions[out_attr[i].i].regs;
14883 /* This assumes all possible supersets are also a valid
14884 options. */
14885 for (newval = VFP_VERSION_COUNT - 1; newval > 0; newval--)
14886 {
14887 if (regs == vfp_versions[newval].regs
14888 && ver == vfp_versions[newval].ver)
14889 break;
14890 }
14891 out_attr[i].i = newval;
14892 }
14893 break;
14894 case Tag_PCS_config:
14895 if (out_attr[i].i == 0)
14896 out_attr[i].i = in_attr[i].i;
14897 else if (in_attr[i].i != 0 && out_attr[i].i != in_attr[i].i)
14898 {
14899 /* It's sometimes ok to mix different configs, so this is only
14900 a warning. */
14901 _bfd_error_handler
14902 (_("warning: %pB: conflicting platform configuration"), ibfd);
14903 }
14904 break;
14905 case Tag_ABI_PCS_R9_use:
14906 if (in_attr[i].i != out_attr[i].i
14907 && out_attr[i].i != AEABI_R9_unused
14908 && in_attr[i].i != AEABI_R9_unused)
14909 {
14910 _bfd_error_handler
14911 (_("error: %pB: conflicting use of R9"), ibfd);
14912 result = false;
14913 }
14914 if (out_attr[i].i == AEABI_R9_unused)
14915 out_attr[i].i = in_attr[i].i;
14916 break;
14917 case Tag_ABI_PCS_RW_data:
14918 if (in_attr[i].i == AEABI_PCS_RW_data_SBrel
14919 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_SB
14920 && out_attr[Tag_ABI_PCS_R9_use].i != AEABI_R9_unused)
14921 {
14922 _bfd_error_handler
14923 (_("error: %pB: SB relative addressing conflicts with use of R9"),
14924 ibfd);
14925 result = false;
14926 }
14927 /* Use the smallest value specified. */
14928 if (in_attr[i].i < out_attr[i].i)
14929 out_attr[i].i = in_attr[i].i;
14930 break;
14931 case Tag_ABI_PCS_wchar_t:
14932 if (out_attr[i].i && in_attr[i].i && out_attr[i].i != in_attr[i].i
14933 && !elf_arm_tdata (obfd)->no_wchar_size_warning)
14934 {
14935 _bfd_error_handler
14936 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
14937 ibfd, in_attr[i].i, out_attr[i].i);
14938 }
14939 else if (in_attr[i].i && !out_attr[i].i)
14940 out_attr[i].i = in_attr[i].i;
14941 break;
14942 case Tag_ABI_enum_size:
14943 if (in_attr[i].i != AEABI_enum_unused)
14944 {
14945 if (out_attr[i].i == AEABI_enum_unused
14946 || out_attr[i].i == AEABI_enum_forced_wide)
14947 {
14948 /* The existing object is compatible with anything.
14949 Use whatever requirements the new object has. */
14950 out_attr[i].i = in_attr[i].i;
14951 }
14952 else if (in_attr[i].i != AEABI_enum_forced_wide
14953 && out_attr[i].i != in_attr[i].i
14954 && !elf_arm_tdata (obfd)->no_enum_size_warning)
14955 {
14956 static const char *aeabi_enum_names[] =
14957 { "", "variable-size", "32-bit", "" };
14958 const char *in_name =
14959 in_attr[i].i < ARRAY_SIZE (aeabi_enum_names)
14960 ? aeabi_enum_names[in_attr[i].i]
14961 : "<unknown>";
14962 const char *out_name =
14963 out_attr[i].i < ARRAY_SIZE (aeabi_enum_names)
14964 ? aeabi_enum_names[out_attr[i].i]
14965 : "<unknown>";
14966 _bfd_error_handler
14967 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
14968 ibfd, in_name, out_name);
14969 }
14970 }
14971 break;
14972 case Tag_ABI_VFP_args:
14973 /* Aready done. */
14974 break;
14975 case Tag_ABI_WMMX_args:
14976 if (in_attr[i].i != out_attr[i].i)
14977 {
14978 _bfd_error_handler
14979 (_("error: %pB uses iWMMXt register arguments, %pB does not"),
14980 ibfd, obfd);
14981 result = false;
14982 }
14983 break;
14984 case Tag_compatibility:
14985 /* Merged in target-independent code. */
14986 break;
14987 case Tag_ABI_HardFP_use:
14988 /* This is handled along with Tag_FP_arch. */
14989 break;
14990 case Tag_ABI_FP_16bit_format:
14991 if (in_attr[i].i != 0 && out_attr[i].i != 0)
14992 {
14993 if (in_attr[i].i != out_attr[i].i)
14994 {
14995 _bfd_error_handler
14996 (_("error: fp16 format mismatch between %pB and %pB"),
14997 ibfd, obfd);
14998 result = false;
14999 }
15000 }
15001 if (in_attr[i].i != 0)
15002 out_attr[i].i = in_attr[i].i;
15003 break;
15004
15005 case Tag_DIV_use:
15006 /* A value of zero on input means that the divide instruction may
15007 be used if available in the base architecture as specified via
15008 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15009 the user did not want divide instructions. A value of 2
15010 explicitly means that divide instructions were allowed in ARM
15011 and Thumb state. */
15012 if (in_attr[i].i == out_attr[i].i)
15013 /* Do nothing. */ ;
15014 else if (elf32_arm_attributes_forbid_div (in_attr)
15015 && !elf32_arm_attributes_accept_div (out_attr))
15016 out_attr[i].i = 1;
15017 else if (elf32_arm_attributes_forbid_div (out_attr)
15018 && elf32_arm_attributes_accept_div (in_attr))
15019 out_attr[i].i = in_attr[i].i;
15020 else if (in_attr[i].i == 2)
15021 out_attr[i].i = in_attr[i].i;
15022 break;
15023
15024 case Tag_MPextension_use_legacy:
15025 /* We don't output objects with Tag_MPextension_use_legacy - we
15026 move the value to Tag_MPextension_use. */
15027 if (in_attr[i].i != 0 && in_attr[Tag_MPextension_use].i != 0)
15028 {
15029 if (in_attr[Tag_MPextension_use].i != in_attr[i].i)
15030 {
15031 _bfd_error_handler
15032 (_("%pB has both the current and legacy "
15033 "Tag_MPextension_use attributes"),
15034 ibfd);
15035 result = false;
15036 }
15037 }
15038
15039 if (in_attr[i].i > out_attr[Tag_MPextension_use].i)
15040 out_attr[Tag_MPextension_use] = in_attr[i];
15041
15042 break;
15043
15044 case Tag_nodefaults:
15045 /* This tag is set if it exists, but the value is unused (and is
15046 typically zero). We don't actually need to do anything here -
15047 the merge happens automatically when the type flags are merged
15048 below. */
15049 break;
15050 case Tag_also_compatible_with:
15051 /* Already done in Tag_CPU_arch. */
15052 break;
15053 case Tag_conformance:
15054 /* Keep the attribute if it matches. Throw it away otherwise.
15055 No attribute means no claim to conform. */
15056 if (!in_attr[i].s || !out_attr[i].s
15057 || strcmp (in_attr[i].s, out_attr[i].s) != 0)
15058 out_attr[i].s = NULL;
15059 break;
15060
15061 default:
15062 result
15063 = result && _bfd_elf_merge_unknown_attribute_low (ibfd, obfd, i);
15064 }
15065
15066 /* If out_attr was copied from in_attr then it won't have a type yet. */
15067 if (in_attr[i].type && !out_attr[i].type)
15068 out_attr[i].type = in_attr[i].type;
15069 }
15070
15071 /* Merge Tag_compatibility attributes and any common GNU ones. */
15072 if (!_bfd_elf_merge_object_attributes (ibfd, info))
15073 return false;
15074
15075 /* Check for any attributes not known on ARM. */
15076 result &= _bfd_elf_merge_unknown_attribute_list (ibfd, obfd);
15077
15078 return result;
15079 }
15080
15081
15082 /* Return TRUE if the two EABI versions are incompatible. */
15083
15084 static bool
15085 elf32_arm_versions_compatible (unsigned iver, unsigned over)
15086 {
15087 /* v4 and v5 are the same spec before and after it was released,
15088 so allow mixing them. */
15089 if ((iver == EF_ARM_EABI_VER4 && over == EF_ARM_EABI_VER5)
15090 || (iver == EF_ARM_EABI_VER5 && over == EF_ARM_EABI_VER4))
15091 return true;
15092
15093 return (iver == over);
15094 }
15095
15096 /* Merge backend specific data from an object file to the output
15097 object file when linking. */
15098
15099 static bool
15100 elf32_arm_merge_private_bfd_data (bfd *, struct bfd_link_info *);
15101
15102 /* Display the flags field. */
15103
15104 static bool
15105 elf32_arm_print_private_bfd_data (bfd *abfd, void * ptr)
15106 {
15107 FILE * file = (FILE *) ptr;
15108 unsigned long flags;
15109
15110 BFD_ASSERT (abfd != NULL && ptr != NULL);
15111
15112 /* Print normal ELF private data. */
15113 _bfd_elf_print_private_bfd_data (abfd, ptr);
15114
15115 flags = elf_elfheader (abfd)->e_flags;
15116 /* Ignore init flag - it may not be set, despite the flags field
15117 containing valid data. */
15118
15119 fprintf (file, _("private flags = 0x%lx:"), elf_elfheader (abfd)->e_flags);
15120
15121 switch (EF_ARM_EABI_VERSION (flags))
15122 {
15123 case EF_ARM_EABI_UNKNOWN:
15124 /* The following flag bits are GNU extensions and not part of the
15125 official ARM ELF extended ABI. Hence they are only decoded if
15126 the EABI version is not set. */
15127 if (flags & EF_ARM_INTERWORK)
15128 fprintf (file, _(" [interworking enabled]"));
15129
15130 if (flags & EF_ARM_APCS_26)
15131 fprintf (file, " [APCS-26]");
15132 else
15133 fprintf (file, " [APCS-32]");
15134
15135 if (flags & EF_ARM_VFP_FLOAT)
15136 fprintf (file, _(" [VFP float format]"));
15137 else if (flags & EF_ARM_MAVERICK_FLOAT)
15138 fprintf (file, _(" [Maverick float format]"));
15139 else
15140 fprintf (file, _(" [FPA float format]"));
15141
15142 if (flags & EF_ARM_APCS_FLOAT)
15143 fprintf (file, _(" [floats passed in float registers]"));
15144
15145 if (flags & EF_ARM_PIC)
15146 fprintf (file, _(" [position independent]"));
15147
15148 if (flags & EF_ARM_NEW_ABI)
15149 fprintf (file, _(" [new ABI]"));
15150
15151 if (flags & EF_ARM_OLD_ABI)
15152 fprintf (file, _(" [old ABI]"));
15153
15154 if (flags & EF_ARM_SOFT_FLOAT)
15155 fprintf (file, _(" [software FP]"));
15156
15157 flags &= ~(EF_ARM_INTERWORK | EF_ARM_APCS_26 | EF_ARM_APCS_FLOAT
15158 | EF_ARM_PIC | EF_ARM_NEW_ABI | EF_ARM_OLD_ABI
15159 | EF_ARM_SOFT_FLOAT | EF_ARM_VFP_FLOAT
15160 | EF_ARM_MAVERICK_FLOAT);
15161 break;
15162
15163 case EF_ARM_EABI_VER1:
15164 fprintf (file, _(" [Version1 EABI]"));
15165
15166 if (flags & EF_ARM_SYMSARESORTED)
15167 fprintf (file, _(" [sorted symbol table]"));
15168 else
15169 fprintf (file, _(" [unsorted symbol table]"));
15170
15171 flags &= ~ EF_ARM_SYMSARESORTED;
15172 break;
15173
15174 case EF_ARM_EABI_VER2:
15175 fprintf (file, _(" [Version2 EABI]"));
15176
15177 if (flags & EF_ARM_SYMSARESORTED)
15178 fprintf (file, _(" [sorted symbol table]"));
15179 else
15180 fprintf (file, _(" [unsorted symbol table]"));
15181
15182 if (flags & EF_ARM_DYNSYMSUSESEGIDX)
15183 fprintf (file, _(" [dynamic symbols use segment index]"));
15184
15185 if (flags & EF_ARM_MAPSYMSFIRST)
15186 fprintf (file, _(" [mapping symbols precede others]"));
15187
15188 flags &= ~(EF_ARM_SYMSARESORTED | EF_ARM_DYNSYMSUSESEGIDX
15189 | EF_ARM_MAPSYMSFIRST);
15190 break;
15191
15192 case EF_ARM_EABI_VER3:
15193 fprintf (file, _(" [Version3 EABI]"));
15194 break;
15195
15196 case EF_ARM_EABI_VER4:
15197 fprintf (file, _(" [Version4 EABI]"));
15198 goto eabi;
15199
15200 case EF_ARM_EABI_VER5:
15201 fprintf (file, _(" [Version5 EABI]"));
15202
15203 if (flags & EF_ARM_ABI_FLOAT_SOFT)
15204 fprintf (file, _(" [soft-float ABI]"));
15205
15206 if (flags & EF_ARM_ABI_FLOAT_HARD)
15207 fprintf (file, _(" [hard-float ABI]"));
15208
15209 flags &= ~(EF_ARM_ABI_FLOAT_SOFT | EF_ARM_ABI_FLOAT_HARD);
15210
15211 eabi:
15212 if (flags & EF_ARM_BE8)
15213 fprintf (file, _(" [BE8]"));
15214
15215 if (flags & EF_ARM_LE8)
15216 fprintf (file, _(" [LE8]"));
15217
15218 flags &= ~(EF_ARM_LE8 | EF_ARM_BE8);
15219 break;
15220
15221 default:
15222 fprintf (file, _(" <EABI version unrecognised>"));
15223 break;
15224 }
15225
15226 flags &= ~ EF_ARM_EABIMASK;
15227
15228 if (flags & EF_ARM_RELEXEC)
15229 fprintf (file, _(" [relocatable executable]"));
15230
15231 if (flags & EF_ARM_PIC)
15232 fprintf (file, _(" [position independent]"));
15233
15234 if (elf_elfheader (abfd)->e_ident[EI_OSABI] == ELFOSABI_ARM_FDPIC)
15235 fprintf (file, _(" [FDPIC ABI supplement]"));
15236
15237 flags &= ~ (EF_ARM_RELEXEC | EF_ARM_PIC);
15238
15239 if (flags)
15240 fprintf (file, _(" <Unrecognised flag bits set>"));
15241
15242 fputc ('\n', file);
15243
15244 return true;
15245 }
15246
15247 static int
15248 elf32_arm_get_symbol_type (Elf_Internal_Sym * elf_sym, int type)
15249 {
15250 switch (ELF_ST_TYPE (elf_sym->st_info))
15251 {
15252 case STT_ARM_TFUNC:
15253 return ELF_ST_TYPE (elf_sym->st_info);
15254
15255 case STT_ARM_16BIT:
15256 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15257 This allows us to distinguish between data used by Thumb instructions
15258 and non-data (which is probably code) inside Thumb regions of an
15259 executable. */
15260 if (type != STT_OBJECT && type != STT_TLS)
15261 return ELF_ST_TYPE (elf_sym->st_info);
15262 break;
15263
15264 default:
15265 break;
15266 }
15267
15268 return type;
15269 }
15270
15271 static asection *
15272 elf32_arm_gc_mark_hook (asection *sec,
15273 struct bfd_link_info *info,
15274 Elf_Internal_Rela *rel,
15275 struct elf_link_hash_entry *h,
15276 Elf_Internal_Sym *sym)
15277 {
15278 if (h != NULL)
15279 switch (ELF32_R_TYPE (rel->r_info))
15280 {
15281 case R_ARM_GNU_VTINHERIT:
15282 case R_ARM_GNU_VTENTRY:
15283 return NULL;
15284 }
15285
15286 return _bfd_elf_gc_mark_hook (sec, info, rel, h, sym);
15287 }
15288
15289 /* Look through the relocs for a section during the first phase. */
15290
15291 static bool
15292 elf32_arm_check_relocs (bfd *abfd, struct bfd_link_info *info,
15293 asection *sec, const Elf_Internal_Rela *relocs)
15294 {
15295 Elf_Internal_Shdr *symtab_hdr;
15296 struct elf_link_hash_entry **sym_hashes;
15297 const Elf_Internal_Rela *rel;
15298 const Elf_Internal_Rela *rel_end;
15299 bfd *dynobj;
15300 asection *sreloc;
15301 struct elf32_arm_link_hash_table *htab;
15302 bool call_reloc_p;
15303 bool may_become_dynamic_p;
15304 bool may_need_local_target_p;
15305 unsigned long nsyms;
15306
15307 if (bfd_link_relocatable (info))
15308 return true;
15309
15310 BFD_ASSERT (is_arm_elf (abfd));
15311
15312 htab = elf32_arm_hash_table (info);
15313 if (htab == NULL)
15314 return false;
15315
15316 sreloc = NULL;
15317
15318 /* Create dynamic sections for relocatable executables so that we can
15319 copy relocations. */
15320 if (htab->root.is_relocatable_executable
15321 && ! htab->root.dynamic_sections_created)
15322 {
15323 if (! _bfd_elf_link_create_dynamic_sections (abfd, info))
15324 return false;
15325 }
15326
15327 if (htab->root.dynobj == NULL)
15328 htab->root.dynobj = abfd;
15329 if (!create_ifunc_sections (info))
15330 return false;
15331
15332 dynobj = htab->root.dynobj;
15333
15334 symtab_hdr = & elf_symtab_hdr (abfd);
15335 sym_hashes = elf_sym_hashes (abfd);
15336 nsyms = NUM_SHDR_ENTRIES (symtab_hdr);
15337
15338 rel_end = relocs + sec->reloc_count;
15339 for (rel = relocs; rel < rel_end; rel++)
15340 {
15341 Elf_Internal_Sym *isym;
15342 struct elf_link_hash_entry *h;
15343 struct elf32_arm_link_hash_entry *eh;
15344 unsigned int r_symndx;
15345 int r_type;
15346
15347 r_symndx = ELF32_R_SYM (rel->r_info);
15348 r_type = ELF32_R_TYPE (rel->r_info);
15349 r_type = arm_real_reloc_type (htab, r_type);
15350
15351 if (r_symndx >= nsyms
15352 /* PR 9934: It is possible to have relocations that do not
15353 refer to symbols, thus it is also possible to have an
15354 object file containing relocations but no symbol table. */
15355 && (r_symndx > STN_UNDEF || nsyms > 0))
15356 {
15357 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
15358 r_symndx);
15359 return false;
15360 }
15361
15362 h = NULL;
15363 isym = NULL;
15364 if (nsyms > 0)
15365 {
15366 if (r_symndx < symtab_hdr->sh_info)
15367 {
15368 /* A local symbol. */
15369 isym = bfd_sym_from_r_symndx (&htab->root.sym_cache,
15370 abfd, r_symndx);
15371 if (isym == NULL)
15372 return false;
15373 }
15374 else
15375 {
15376 h = sym_hashes[r_symndx - symtab_hdr->sh_info];
15377 while (h->root.type == bfd_link_hash_indirect
15378 || h->root.type == bfd_link_hash_warning)
15379 h = (struct elf_link_hash_entry *) h->root.u.i.link;
15380 }
15381 }
15382
15383 eh = (struct elf32_arm_link_hash_entry *) h;
15384
15385 call_reloc_p = false;
15386 may_become_dynamic_p = false;
15387 may_need_local_target_p = false;
15388
15389 /* Could be done earlier, if h were already available. */
15390 r_type = elf32_arm_tls_transition (info, r_type, h);
15391 switch (r_type)
15392 {
15393 case R_ARM_GOTOFFFUNCDESC:
15394 {
15395 if (h == NULL)
15396 {
15397 if (!elf32_arm_allocate_local_sym_info (abfd))
15398 return false;
15399 if (r_symndx >= elf32_arm_num_entries (abfd))
15400 return false;
15401 elf32_arm_local_fdpic_cnts (abfd) [r_symndx].gotofffuncdesc_cnt += 1;
15402 elf32_arm_local_fdpic_cnts (abfd) [r_symndx].funcdesc_offset = -1;
15403 }
15404 else
15405 {
15406 eh->fdpic_cnts.gotofffuncdesc_cnt++;
15407 }
15408 }
15409 break;
15410
15411 case R_ARM_GOTFUNCDESC:
15412 {
15413 if (h == NULL)
15414 {
15415 /* Such a relocation is not supposed to be generated
15416 by gcc on a static function. */
15417 /* Anyway if needed it could be handled. */
15418 return false;
15419 }
15420 else
15421 {
15422 eh->fdpic_cnts.gotfuncdesc_cnt++;
15423 }
15424 }
15425 break;
15426
15427 case R_ARM_FUNCDESC:
15428 {
15429 if (h == NULL)
15430 {
15431 if (!elf32_arm_allocate_local_sym_info (abfd))
15432 return false;
15433 if (r_symndx >= elf32_arm_num_entries (abfd))
15434 return false;
15435 elf32_arm_local_fdpic_cnts (abfd) [r_symndx].funcdesc_cnt += 1;
15436 elf32_arm_local_fdpic_cnts (abfd) [r_symndx].funcdesc_offset = -1;
15437 }
15438 else
15439 {
15440 eh->fdpic_cnts.funcdesc_cnt++;
15441 }
15442 }
15443 break;
15444
15445 case R_ARM_GOT32:
15446 case R_ARM_GOT_PREL:
15447 case R_ARM_TLS_GD32:
15448 case R_ARM_TLS_GD32_FDPIC:
15449 case R_ARM_TLS_IE32:
15450 case R_ARM_TLS_IE32_FDPIC:
15451 case R_ARM_TLS_GOTDESC:
15452 case R_ARM_TLS_DESCSEQ:
15453 case R_ARM_THM_TLS_DESCSEQ:
15454 case R_ARM_TLS_CALL:
15455 case R_ARM_THM_TLS_CALL:
15456 /* This symbol requires a global offset table entry. */
15457 {
15458 int tls_type, old_tls_type;
15459
15460 switch (r_type)
15461 {
15462 case R_ARM_TLS_GD32: tls_type = GOT_TLS_GD; break;
15463 case R_ARM_TLS_GD32_FDPIC: tls_type = GOT_TLS_GD; break;
15464
15465 case R_ARM_TLS_IE32: tls_type = GOT_TLS_IE; break;
15466 case R_ARM_TLS_IE32_FDPIC: tls_type = GOT_TLS_IE; break;
15467
15468 case R_ARM_TLS_GOTDESC:
15469 case R_ARM_TLS_CALL: case R_ARM_THM_TLS_CALL:
15470 case R_ARM_TLS_DESCSEQ: case R_ARM_THM_TLS_DESCSEQ:
15471 tls_type = GOT_TLS_GDESC; break;
15472
15473 default: tls_type = GOT_NORMAL; break;
15474 }
15475
15476 if (!bfd_link_executable (info) && (tls_type & GOT_TLS_IE))
15477 info->flags |= DF_STATIC_TLS;
15478
15479 if (h != NULL)
15480 {
15481 h->got.refcount++;
15482 old_tls_type = elf32_arm_hash_entry (h)->tls_type;
15483 }
15484 else
15485 {
15486 /* This is a global offset table entry for a local symbol. */
15487 if (!elf32_arm_allocate_local_sym_info (abfd))
15488 return false;
15489 if (r_symndx >= elf32_arm_num_entries (abfd))
15490 {
15491 _bfd_error_handler (_("%pB: bad symbol index: %d"), abfd,
15492 r_symndx);
15493 return false;
15494 }
15495
15496 elf_local_got_refcounts (abfd)[r_symndx] += 1;
15497 old_tls_type = elf32_arm_local_got_tls_type (abfd) [r_symndx];
15498 }
15499
15500 /* If a variable is accessed with both tls methods, two
15501 slots may be created. */
15502 if (GOT_TLS_GD_ANY_P (old_tls_type)
15503 && GOT_TLS_GD_ANY_P (tls_type))
15504 tls_type |= old_tls_type;
15505
15506 /* We will already have issued an error message if there
15507 is a TLS/non-TLS mismatch, based on the symbol
15508 type. So just combine any TLS types needed. */
15509 if (old_tls_type != GOT_UNKNOWN && old_tls_type != GOT_NORMAL
15510 && tls_type != GOT_NORMAL)
15511 tls_type |= old_tls_type;
15512
15513 /* If the symbol is accessed in both IE and GDESC
15514 method, we're able to relax. Turn off the GDESC flag,
15515 without messing up with any other kind of tls types
15516 that may be involved. */
15517 if ((tls_type & GOT_TLS_IE) && (tls_type & GOT_TLS_GDESC))
15518 tls_type &= ~GOT_TLS_GDESC;
15519
15520 if (old_tls_type != tls_type)
15521 {
15522 if (h != NULL)
15523 elf32_arm_hash_entry (h)->tls_type = tls_type;
15524 else
15525 elf32_arm_local_got_tls_type (abfd) [r_symndx] = tls_type;
15526 }
15527 }
15528 /* Fall through. */
15529
15530 case R_ARM_TLS_LDM32:
15531 case R_ARM_TLS_LDM32_FDPIC:
15532 if (r_type == R_ARM_TLS_LDM32 || r_type == R_ARM_TLS_LDM32_FDPIC)
15533 htab->tls_ldm_got.refcount++;
15534 /* Fall through. */
15535
15536 case R_ARM_GOTOFF32:
15537 case R_ARM_GOTPC:
15538 if (htab->root.sgot == NULL
15539 && !create_got_section (htab->root.dynobj, info))
15540 return false;
15541 break;
15542
15543 case R_ARM_PC24:
15544 case R_ARM_PLT32:
15545 case R_ARM_CALL:
15546 case R_ARM_JUMP24:
15547 case R_ARM_PREL31:
15548 case R_ARM_THM_CALL:
15549 case R_ARM_THM_JUMP24:
15550 case R_ARM_THM_JUMP19:
15551 call_reloc_p = true;
15552 may_need_local_target_p = true;
15553 break;
15554
15555 case R_ARM_ABS12:
15556 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15557 ldr __GOTT_INDEX__ offsets. */
15558 if (htab->root.target_os != is_vxworks)
15559 {
15560 may_need_local_target_p = true;
15561 break;
15562 }
15563 else goto jump_over;
15564
15565 /* Fall through. */
15566
15567 case R_ARM_MOVW_ABS_NC:
15568 case R_ARM_MOVT_ABS:
15569 case R_ARM_THM_MOVW_ABS_NC:
15570 case R_ARM_THM_MOVT_ABS:
15571 if (bfd_link_pic (info))
15572 {
15573 _bfd_error_handler
15574 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
15575 abfd, elf32_arm_howto_table_1[r_type].name,
15576 (h) ? h->root.root.string : "a local symbol");
15577 bfd_set_error (bfd_error_bad_value);
15578 return false;
15579 }
15580
15581 /* Fall through. */
15582 case R_ARM_ABS32:
15583 case R_ARM_ABS32_NOI:
15584 jump_over:
15585 if (h != NULL && bfd_link_executable (info))
15586 {
15587 h->pointer_equality_needed = 1;
15588 }
15589 /* Fall through. */
15590 case R_ARM_REL32:
15591 case R_ARM_REL32_NOI:
15592 case R_ARM_MOVW_PREL_NC:
15593 case R_ARM_MOVT_PREL:
15594 case R_ARM_THM_MOVW_PREL_NC:
15595 case R_ARM_THM_MOVT_PREL:
15596
15597 /* Should the interworking branches be listed here? */
15598 if ((bfd_link_pic (info) || htab->root.is_relocatable_executable
15599 || htab->fdpic_p)
15600 && (sec->flags & SEC_ALLOC) != 0)
15601 {
15602 if (h == NULL
15603 && elf32_arm_howto_from_type (r_type)->pc_relative)
15604 {
15605 /* In shared libraries and relocatable executables,
15606 we treat local relative references as calls;
15607 see the related SYMBOL_CALLS_LOCAL code in
15608 allocate_dynrelocs. */
15609 call_reloc_p = true;
15610 may_need_local_target_p = true;
15611 }
15612 else
15613 /* We are creating a shared library or relocatable
15614 executable, and this is a reloc against a global symbol,
15615 or a non-PC-relative reloc against a local symbol.
15616 We may need to copy the reloc into the output. */
15617 may_become_dynamic_p = true;
15618 }
15619 else
15620 may_need_local_target_p = true;
15621 break;
15622
15623 /* This relocation describes the C++ object vtable hierarchy.
15624 Reconstruct it for later use during GC. */
15625 case R_ARM_GNU_VTINHERIT:
15626 if (!bfd_elf_gc_record_vtinherit (abfd, sec, h, rel->r_offset))
15627 return false;
15628 break;
15629
15630 /* This relocation describes which C++ vtable entries are actually
15631 used. Record for later use during GC. */
15632 case R_ARM_GNU_VTENTRY:
15633 if (!bfd_elf_gc_record_vtentry (abfd, sec, h, rel->r_offset))
15634 return false;
15635 break;
15636 }
15637
15638 if (h != NULL)
15639 {
15640 if (call_reloc_p)
15641 /* We may need a .plt entry if the function this reloc
15642 refers to is in a different object, regardless of the
15643 symbol's type. We can't tell for sure yet, because
15644 something later might force the symbol local. */
15645 h->needs_plt = 1;
15646 else if (may_need_local_target_p)
15647 /* If this reloc is in a read-only section, we might
15648 need a copy reloc. We can't check reliably at this
15649 stage whether the section is read-only, as input
15650 sections have not yet been mapped to output sections.
15651 Tentatively set the flag for now, and correct in
15652 adjust_dynamic_symbol. */
15653 h->non_got_ref = 1;
15654 }
15655
15656 if (may_need_local_target_p
15657 && (h != NULL || ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC))
15658 {
15659 union gotplt_union *root_plt;
15660 struct arm_plt_info *arm_plt;
15661 struct arm_local_iplt_info *local_iplt;
15662
15663 if (h != NULL)
15664 {
15665 root_plt = &h->plt;
15666 arm_plt = &eh->plt;
15667 }
15668 else
15669 {
15670 local_iplt = elf32_arm_create_local_iplt (abfd, r_symndx);
15671 if (local_iplt == NULL)
15672 return false;
15673 root_plt = &local_iplt->root;
15674 arm_plt = &local_iplt->arm;
15675 }
15676
15677 /* If the symbol is a function that doesn't bind locally,
15678 this relocation will need a PLT entry. */
15679 if (root_plt->refcount != -1)
15680 root_plt->refcount += 1;
15681
15682 if (!call_reloc_p)
15683 arm_plt->noncall_refcount++;
15684
15685 /* It's too early to use htab->use_blx here, so we have to
15686 record possible blx references separately from
15687 relocs that definitely need a thumb stub. */
15688
15689 if (r_type == R_ARM_THM_CALL)
15690 arm_plt->maybe_thumb_refcount += 1;
15691
15692 if (r_type == R_ARM_THM_JUMP24
15693 || r_type == R_ARM_THM_JUMP19)
15694 arm_plt->thumb_refcount += 1;
15695 }
15696
15697 if (may_become_dynamic_p)
15698 {
15699 struct elf_dyn_relocs *p, **head;
15700
15701 /* Create a reloc section in dynobj. */
15702 if (sreloc == NULL)
15703 {
15704 sreloc = _bfd_elf_make_dynamic_reloc_section
15705 (sec, dynobj, 2, abfd, ! htab->use_rel);
15706
15707 if (sreloc == NULL)
15708 return false;
15709 }
15710
15711 /* If this is a global symbol, count the number of
15712 relocations we need for this symbol. */
15713 if (h != NULL)
15714 head = &h->dyn_relocs;
15715 else
15716 {
15717 head = elf32_arm_get_local_dynreloc_list (abfd, r_symndx, isym);
15718 if (head == NULL)
15719 return false;
15720 }
15721
15722 p = *head;
15723 if (p == NULL || p->sec != sec)
15724 {
15725 size_t amt = sizeof *p;
15726
15727 p = (struct elf_dyn_relocs *) bfd_alloc (htab->root.dynobj, amt);
15728 if (p == NULL)
15729 return false;
15730 p->next = *head;
15731 *head = p;
15732 p->sec = sec;
15733 p->count = 0;
15734 p->pc_count = 0;
15735 }
15736
15737 if (elf32_arm_howto_from_type (r_type)->pc_relative)
15738 p->pc_count += 1;
15739 p->count += 1;
15740 if (h == NULL && htab->fdpic_p && !bfd_link_pic (info)
15741 && r_type != R_ARM_ABS32 && r_type != R_ARM_ABS32_NOI)
15742 {
15743 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15744 that will become rofixup. */
15745 /* This is due to the fact that we suppose all will become rofixup. */
15746 _bfd_error_handler
15747 (_("FDPIC does not yet support %s relocation"
15748 " to become dynamic for executable"),
15749 elf32_arm_howto_table_1[r_type].name);
15750 abort ();
15751 }
15752 }
15753 }
15754
15755 return true;
15756 }
15757
15758 static void
15759 elf32_arm_update_relocs (asection *o,
15760 struct bfd_elf_section_reloc_data *reldata)
15761 {
15762 void (*swap_in) (bfd *, const bfd_byte *, Elf_Internal_Rela *);
15763 void (*swap_out) (bfd *, const Elf_Internal_Rela *, bfd_byte *);
15764 const struct elf_backend_data *bed;
15765 _arm_elf_section_data *eado;
15766 struct bfd_link_order *p;
15767 bfd_byte *erela_head, *erela;
15768 Elf_Internal_Rela *irela_head, *irela;
15769 Elf_Internal_Shdr *rel_hdr;
15770 bfd *abfd;
15771 unsigned int count;
15772
15773 eado = get_arm_elf_section_data (o);
15774
15775 if (!eado || eado->elf.this_hdr.sh_type != SHT_ARM_EXIDX)
15776 return;
15777
15778 abfd = o->owner;
15779 bed = get_elf_backend_data (abfd);
15780 rel_hdr = reldata->hdr;
15781
15782 if (rel_hdr->sh_entsize == bed->s->sizeof_rel)
15783 {
15784 swap_in = bed->s->swap_reloc_in;
15785 swap_out = bed->s->swap_reloc_out;
15786 }
15787 else if (rel_hdr->sh_entsize == bed->s->sizeof_rela)
15788 {
15789 swap_in = bed->s->swap_reloca_in;
15790 swap_out = bed->s->swap_reloca_out;
15791 }
15792 else
15793 abort ();
15794
15795 erela_head = rel_hdr->contents;
15796 irela_head = (Elf_Internal_Rela *) bfd_zmalloc
15797 ((NUM_SHDR_ENTRIES (rel_hdr) + 1) * sizeof (*irela_head));
15798
15799 erela = erela_head;
15800 irela = irela_head;
15801 count = 0;
15802
15803 for (p = o->map_head.link_order; p; p = p->next)
15804 {
15805 if (p->type == bfd_section_reloc_link_order
15806 || p->type == bfd_symbol_reloc_link_order)
15807 {
15808 (*swap_in) (abfd, erela, irela);
15809 erela += rel_hdr->sh_entsize;
15810 irela++;
15811 count++;
15812 }
15813 else if (p->type == bfd_indirect_link_order)
15814 {
15815 struct bfd_elf_section_reloc_data *input_reldata;
15816 arm_unwind_table_edit *edit_list, *edit_tail;
15817 _arm_elf_section_data *eadi;
15818 bfd_size_type j;
15819 bfd_vma offset;
15820 asection *i;
15821
15822 i = p->u.indirect.section;
15823
15824 eadi = get_arm_elf_section_data (i);
15825 edit_list = eadi->u.exidx.unwind_edit_list;
15826 edit_tail = eadi->u.exidx.unwind_edit_tail;
15827 offset = i->output_offset;
15828
15829 if (eadi->elf.rel.hdr &&
15830 eadi->elf.rel.hdr->sh_entsize == rel_hdr->sh_entsize)
15831 input_reldata = &eadi->elf.rel;
15832 else if (eadi->elf.rela.hdr &&
15833 eadi->elf.rela.hdr->sh_entsize == rel_hdr->sh_entsize)
15834 input_reldata = &eadi->elf.rela;
15835 else
15836 abort ();
15837
15838 if (edit_list)
15839 {
15840 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15841 {
15842 arm_unwind_table_edit *edit_node, *edit_next;
15843 bfd_vma bias;
15844 bfd_vma reloc_index;
15845
15846 (*swap_in) (abfd, erela, irela);
15847 reloc_index = (irela->r_offset - offset) / 8;
15848
15849 bias = 0;
15850 edit_node = edit_list;
15851 for (edit_next = edit_list;
15852 edit_next && edit_next->index <= reloc_index;
15853 edit_next = edit_node->next)
15854 {
15855 bias++;
15856 edit_node = edit_next;
15857 }
15858
15859 if (edit_node->type != DELETE_EXIDX_ENTRY
15860 || edit_node->index != reloc_index)
15861 {
15862 irela->r_offset -= bias * 8;
15863 irela++;
15864 count++;
15865 }
15866
15867 erela += rel_hdr->sh_entsize;
15868 }
15869
15870 if (edit_tail->type == INSERT_EXIDX_CANTUNWIND_AT_END)
15871 {
15872 /* New relocation entity. */
15873 asection *text_sec = edit_tail->linked_section;
15874 asection *text_out = text_sec->output_section;
15875 bfd_vma exidx_offset = offset + i->size - 8;
15876
15877 irela->r_addend = 0;
15878 irela->r_offset = exidx_offset;
15879 irela->r_info = ELF32_R_INFO
15880 (text_out->target_index, R_ARM_PREL31);
15881 irela++;
15882 count++;
15883 }
15884 }
15885 else
15886 {
15887 for (j = 0; j < NUM_SHDR_ENTRIES (input_reldata->hdr); j++)
15888 {
15889 (*swap_in) (abfd, erela, irela);
15890 erela += rel_hdr->sh_entsize;
15891 irela++;
15892 }
15893
15894 count += NUM_SHDR_ENTRIES (input_reldata->hdr);
15895 }
15896 }
15897 }
15898
15899 reldata->count = count;
15900 rel_hdr->sh_size = count * rel_hdr->sh_entsize;
15901
15902 erela = erela_head;
15903 irela = irela_head;
15904 while (count > 0)
15905 {
15906 (*swap_out) (abfd, irela, erela);
15907 erela += rel_hdr->sh_entsize;
15908 irela++;
15909 count--;
15910 }
15911
15912 free (irela_head);
15913
15914 /* Hashes are no longer valid. */
15915 free (reldata->hashes);
15916 reldata->hashes = NULL;
15917 }
15918
15919 /* Unwinding tables are not referenced directly. This pass marks them as
15920 required if the corresponding code section is marked. Similarly, ARMv8-M
15921 secure entry functions can only be referenced by SG veneers which are
15922 created after the GC process. They need to be marked in case they reside in
15923 their own section (as would be the case if code was compiled with
15924 -ffunction-sections). */
15925
15926 static bool
15927 elf32_arm_gc_mark_extra_sections (struct bfd_link_info *info,
15928 elf_gc_mark_hook_fn gc_mark_hook)
15929 {
15930 bfd *sub;
15931 Elf_Internal_Shdr **elf_shdrp;
15932 asection *cmse_sec;
15933 obj_attribute *out_attr;
15934 Elf_Internal_Shdr *symtab_hdr;
15935 unsigned i, sym_count, ext_start;
15936 const struct elf_backend_data *bed;
15937 struct elf_link_hash_entry **sym_hashes;
15938 struct elf32_arm_link_hash_entry *cmse_hash;
15939 bool again, is_v8m, first_bfd_browse = true;
15940 bool debug_sec_need_to_be_marked = false;
15941 asection *isec;
15942
15943 _bfd_elf_gc_mark_extra_sections (info, gc_mark_hook);
15944
15945 out_attr = elf_known_obj_attributes_proc (info->output_bfd);
15946 is_v8m = out_attr[Tag_CPU_arch].i >= TAG_CPU_ARCH_V8M_BASE
15947 && out_attr[Tag_CPU_arch_profile].i == 'M';
15948
15949 /* Marking EH data may cause additional code sections to be marked,
15950 requiring multiple passes. */
15951 again = true;
15952 while (again)
15953 {
15954 again = false;
15955 for (sub = info->input_bfds; sub != NULL; sub = sub->link.next)
15956 {
15957 asection *o;
15958
15959 if (! is_arm_elf (sub))
15960 continue;
15961
15962 elf_shdrp = elf_elfsections (sub);
15963 for (o = sub->sections; o != NULL; o = o->next)
15964 {
15965 Elf_Internal_Shdr *hdr;
15966
15967 hdr = &elf_section_data (o)->this_hdr;
15968 if (hdr->sh_type == SHT_ARM_EXIDX
15969 && hdr->sh_link
15970 && hdr->sh_link < elf_numsections (sub)
15971 && !o->gc_mark
15972 && elf_shdrp[hdr->sh_link]->bfd_section->gc_mark)
15973 {
15974 again = true;
15975 if (!_bfd_elf_gc_mark (info, o, gc_mark_hook))
15976 return false;
15977 }
15978 }
15979
15980 /* Mark section holding ARMv8-M secure entry functions. We mark all
15981 of them so no need for a second browsing. */
15982 if (is_v8m && first_bfd_browse)
15983 {
15984 sym_hashes = elf_sym_hashes (sub);
15985 bed = get_elf_backend_data (sub);
15986 symtab_hdr = &elf_tdata (sub)->symtab_hdr;
15987 sym_count = symtab_hdr->sh_size / bed->s->sizeof_sym;
15988 ext_start = symtab_hdr->sh_info;
15989
15990 /* Scan symbols. */
15991 for (i = ext_start; i < sym_count; i++)
15992 {
15993 cmse_hash = elf32_arm_hash_entry (sym_hashes[i - ext_start]);
15994 if (cmse_hash == NULL)
15995 continue;
15996
15997 /* Assume it is a special symbol. If not, cmse_scan will
15998 warn about it and user can do something about it. */
15999 if (startswith (cmse_hash->root.root.root.string,
16000 CMSE_PREFIX))
16001 {
16002 cmse_sec = cmse_hash->root.root.u.def.section;
16003 if (!cmse_sec->gc_mark
16004 && !_bfd_elf_gc_mark (info, cmse_sec, gc_mark_hook))
16005 return false;
16006 /* The debug sections related to these secure entry
16007 functions are marked on enabling below flag. */
16008 debug_sec_need_to_be_marked = true;
16009 }
16010 }
16011
16012 if (debug_sec_need_to_be_marked)
16013 {
16014 /* Looping over all the sections of the object file containing
16015 Armv8-M secure entry functions and marking all the debug
16016 sections. */
16017 for (isec = sub->sections; isec != NULL; isec = isec->next)
16018 {
16019 /* If not a debug sections, skip it. */
16020 if (!isec->gc_mark && (isec->flags & SEC_DEBUGGING))
16021 isec->gc_mark = 1 ;
16022 }
16023 debug_sec_need_to_be_marked = false;
16024 }
16025 }
16026 }
16027 first_bfd_browse = false;
16028 }
16029
16030 return true;
16031 }
16032
16033 /* Treat mapping symbols as special target symbols. */
16034
16035 static bool
16036 elf32_arm_is_target_special_symbol (bfd * abfd ATTRIBUTE_UNUSED, asymbol * sym)
16037 {
16038 return bfd_is_arm_special_symbol_name (sym->name,
16039 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
16040 }
16041
16042 /* If the ELF symbol SYM might be a function in SEC, return the
16043 function size and set *CODE_OFF to the function's entry point,
16044 otherwise return zero. */
16045
16046 static bfd_size_type
16047 elf32_arm_maybe_function_sym (const asymbol *sym, asection *sec,
16048 bfd_vma *code_off)
16049 {
16050 bfd_size_type size;
16051 elf_symbol_type * elf_sym = (elf_symbol_type *) sym;
16052
16053 if ((sym->flags & (BSF_SECTION_SYM | BSF_FILE | BSF_OBJECT
16054 | BSF_THREAD_LOCAL | BSF_RELC | BSF_SRELC)) != 0
16055 || sym->section != sec)
16056 return 0;
16057
16058 size = (sym->flags & BSF_SYNTHETIC) ? 0 : elf_sym->internal_elf_sym.st_size;
16059
16060 if (!(sym->flags & BSF_SYNTHETIC))
16061 switch (ELF_ST_TYPE (elf_sym->internal_elf_sym.st_info))
16062 {
16063 case STT_NOTYPE:
16064 /* Ignore symbols created by the annobin plugin for gcc and clang.
16065 These symbols are hidden, local, notype and have a size of 0. */
16066 if (size == 0
16067 && sym->flags & BSF_LOCAL
16068 && ELF_ST_VISIBILITY (elf_sym->internal_elf_sym.st_other) == STV_HIDDEN)
16069 return 0;
16070 /* Fall through. */
16071 case STT_FUNC:
16072 case STT_ARM_TFUNC:
16073 /* FIXME: Allow STT_GNU_IFUNC as well ? */
16074 break;
16075 default:
16076 return 0;
16077 }
16078
16079 if ((sym->flags & BSF_LOCAL)
16080 && bfd_is_arm_special_symbol_name (sym->name,
16081 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16082 return 0;
16083
16084 *code_off = sym->value;
16085
16086 /* Do not return 0 for the function's size. */
16087 return size ? size : 1;
16088
16089 }
16090
16091 static bool
16092 elf32_arm_find_inliner_info (bfd * abfd,
16093 const char ** filename_ptr,
16094 const char ** functionname_ptr,
16095 unsigned int * line_ptr)
16096 {
16097 bool found;
16098 found = _bfd_dwarf2_find_inliner_info (abfd, filename_ptr,
16099 functionname_ptr, line_ptr,
16100 & elf_tdata (abfd)->dwarf2_find_line_info);
16101 return found;
16102 }
16103
16104 /* Adjust a symbol defined by a dynamic object and referenced by a
16105 regular object. The current definition is in some section of the
16106 dynamic object, but we're not including those sections. We have to
16107 change the definition to something the rest of the link can
16108 understand. */
16109
16110 static bool
16111 elf32_arm_adjust_dynamic_symbol (struct bfd_link_info * info,
16112 struct elf_link_hash_entry * h)
16113 {
16114 bfd * dynobj;
16115 asection *s, *srel;
16116 struct elf32_arm_link_hash_entry * eh;
16117 struct elf32_arm_link_hash_table *globals;
16118
16119 globals = elf32_arm_hash_table (info);
16120 if (globals == NULL)
16121 return false;
16122
16123 dynobj = elf_hash_table (info)->dynobj;
16124
16125 /* Make sure we know what is going on here. */
16126 BFD_ASSERT (dynobj != NULL
16127 && (h->needs_plt
16128 || h->type == STT_GNU_IFUNC
16129 || h->is_weakalias
16130 || (h->def_dynamic
16131 && h->ref_regular
16132 && !h->def_regular)));
16133
16134 eh = (struct elf32_arm_link_hash_entry *) h;
16135
16136 /* If this is a function, put it in the procedure linkage table. We
16137 will fill in the contents of the procedure linkage table later,
16138 when we know the address of the .got section. */
16139 if (h->type == STT_FUNC || h->type == STT_GNU_IFUNC || h->needs_plt)
16140 {
16141 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16142 symbol binds locally. */
16143 if (h->plt.refcount <= 0
16144 || (h->type != STT_GNU_IFUNC
16145 && (SYMBOL_CALLS_LOCAL (info, h)
16146 || (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16147 && h->root.type == bfd_link_hash_undefweak))))
16148 {
16149 /* This case can occur if we saw a PLT32 reloc in an input
16150 file, but the symbol was never referred to by a dynamic
16151 object, or if all references were garbage collected. In
16152 such a case, we don't actually need to build a procedure
16153 linkage table, and we can just do a PC24 reloc instead. */
16154 h->plt.offset = (bfd_vma) -1;
16155 eh->plt.thumb_refcount = 0;
16156 eh->plt.maybe_thumb_refcount = 0;
16157 eh->plt.noncall_refcount = 0;
16158 h->needs_plt = 0;
16159 }
16160
16161 return true;
16162 }
16163 else
16164 {
16165 /* It's possible that we incorrectly decided a .plt reloc was
16166 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16167 in check_relocs. We can't decide accurately between function
16168 and non-function syms in check-relocs; Objects loaded later in
16169 the link may change h->type. So fix it now. */
16170 h->plt.offset = (bfd_vma) -1;
16171 eh->plt.thumb_refcount = 0;
16172 eh->plt.maybe_thumb_refcount = 0;
16173 eh->plt.noncall_refcount = 0;
16174 }
16175
16176 /* If this is a weak symbol, and there is a real definition, the
16177 processor independent code will have arranged for us to see the
16178 real definition first, and we can just use the same value. */
16179 if (h->is_weakalias)
16180 {
16181 struct elf_link_hash_entry *def = weakdef (h);
16182 BFD_ASSERT (def->root.type == bfd_link_hash_defined);
16183 h->root.u.def.section = def->root.u.def.section;
16184 h->root.u.def.value = def->root.u.def.value;
16185 return true;
16186 }
16187
16188 /* If there are no non-GOT references, we do not need a copy
16189 relocation. */
16190 if (!h->non_got_ref)
16191 return true;
16192
16193 /* This is a reference to a symbol defined by a dynamic object which
16194 is not a function. */
16195
16196 /* If we are creating a shared library, we must presume that the
16197 only references to the symbol are via the global offset table.
16198 For such cases we need not do anything here; the relocations will
16199 be handled correctly by relocate_section. Relocatable executables
16200 can reference data in shared objects directly, so we don't need to
16201 do anything here. */
16202 if (bfd_link_pic (info) || globals->root.is_relocatable_executable)
16203 return true;
16204
16205 /* We must allocate the symbol in our .dynbss section, which will
16206 become part of the .bss section of the executable. There will be
16207 an entry for this symbol in the .dynsym section. The dynamic
16208 object will contain position independent code, so all references
16209 from the dynamic object to this symbol will go through the global
16210 offset table. The dynamic linker will use the .dynsym entry to
16211 determine the address it must put in the global offset table, so
16212 both the dynamic object and the regular object will refer to the
16213 same memory location for the variable. */
16214 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16215 linker to copy the initial value out of the dynamic object and into
16216 the runtime process image. We need to remember the offset into the
16217 .rel(a).bss section we are going to use. */
16218 if ((h->root.u.def.section->flags & SEC_READONLY) != 0)
16219 {
16220 s = globals->root.sdynrelro;
16221 srel = globals->root.sreldynrelro;
16222 }
16223 else
16224 {
16225 s = globals->root.sdynbss;
16226 srel = globals->root.srelbss;
16227 }
16228 if (info->nocopyreloc == 0
16229 && (h->root.u.def.section->flags & SEC_ALLOC) != 0
16230 && h->size != 0)
16231 {
16232 elf32_arm_allocate_dynrelocs (info, srel, 1);
16233 h->needs_copy = 1;
16234 }
16235
16236 return _bfd_elf_adjust_dynamic_copy (info, h, s);
16237 }
16238
16239 /* Allocate space in .plt, .got and associated reloc sections for
16240 dynamic relocs. */
16241
16242 static bool
16243 allocate_dynrelocs_for_symbol (struct elf_link_hash_entry *h, void * inf)
16244 {
16245 struct bfd_link_info *info;
16246 struct elf32_arm_link_hash_table *htab;
16247 struct elf32_arm_link_hash_entry *eh;
16248 struct elf_dyn_relocs *p;
16249
16250 if (h->root.type == bfd_link_hash_indirect)
16251 return true;
16252
16253 eh = (struct elf32_arm_link_hash_entry *) h;
16254
16255 info = (struct bfd_link_info *) inf;
16256 htab = elf32_arm_hash_table (info);
16257 if (htab == NULL)
16258 return false;
16259
16260 if ((htab->root.dynamic_sections_created || h->type == STT_GNU_IFUNC)
16261 && h->plt.refcount > 0)
16262 {
16263 /* Make sure this symbol is output as a dynamic symbol.
16264 Undefined weak syms won't yet be marked as dynamic. */
16265 if (h->dynindx == -1 && !h->forced_local
16266 && h->root.type == bfd_link_hash_undefweak)
16267 {
16268 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16269 return false;
16270 }
16271
16272 /* If the call in the PLT entry binds locally, the associated
16273 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16274 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16275 than the .plt section. */
16276 if (h->type == STT_GNU_IFUNC && SYMBOL_CALLS_LOCAL (info, h))
16277 {
16278 eh->is_iplt = 1;
16279 if (eh->plt.noncall_refcount == 0
16280 && SYMBOL_REFERENCES_LOCAL (info, h))
16281 /* All non-call references can be resolved directly.
16282 This means that they can (and in some cases, must)
16283 resolve directly to the run-time target, rather than
16284 to the PLT. That in turns means that any .got entry
16285 would be equal to the .igot.plt entry, so there's
16286 no point having both. */
16287 h->got.refcount = 0;
16288 }
16289
16290 if (bfd_link_pic (info)
16291 || eh->is_iplt
16292 || WILL_CALL_FINISH_DYNAMIC_SYMBOL (1, 0, h))
16293 {
16294 elf32_arm_allocate_plt_entry (info, eh->is_iplt, &h->plt, &eh->plt);
16295
16296 /* If this symbol is not defined in a regular file, and we are
16297 not generating a shared library, then set the symbol to this
16298 location in the .plt. This is required to make function
16299 pointers compare as equal between the normal executable and
16300 the shared library. */
16301 if (! bfd_link_pic (info)
16302 && !h->def_regular)
16303 {
16304 h->root.u.def.section = htab->root.splt;
16305 h->root.u.def.value = h->plt.offset;
16306
16307 /* Make sure the function is not marked as Thumb, in case
16308 it is the target of an ABS32 relocation, which will
16309 point to the PLT entry. */
16310 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
16311 }
16312
16313 /* VxWorks executables have a second set of relocations for
16314 each PLT entry. They go in a separate relocation section,
16315 which is processed by the kernel loader. */
16316 if (htab->root.target_os == is_vxworks && !bfd_link_pic (info))
16317 {
16318 /* There is a relocation for the initial PLT entry:
16319 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16320 if (h->plt.offset == htab->plt_header_size)
16321 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 1);
16322
16323 /* There are two extra relocations for each subsequent
16324 PLT entry: an R_ARM_32 relocation for the GOT entry,
16325 and an R_ARM_32 relocation for the PLT entry. */
16326 elf32_arm_allocate_dynrelocs (info, htab->srelplt2, 2);
16327 }
16328 }
16329 else
16330 {
16331 h->plt.offset = (bfd_vma) -1;
16332 h->needs_plt = 0;
16333 }
16334 }
16335 else
16336 {
16337 h->plt.offset = (bfd_vma) -1;
16338 h->needs_plt = 0;
16339 }
16340
16341 eh = (struct elf32_arm_link_hash_entry *) h;
16342 eh->tlsdesc_got = (bfd_vma) -1;
16343
16344 if (h->got.refcount > 0)
16345 {
16346 asection *s;
16347 bool dyn;
16348 int tls_type = elf32_arm_hash_entry (h)->tls_type;
16349 int indx;
16350
16351 /* Make sure this symbol is output as a dynamic symbol.
16352 Undefined weak syms won't yet be marked as dynamic. */
16353 if (htab->root.dynamic_sections_created
16354 && h->dynindx == -1
16355 && !h->forced_local
16356 && h->root.type == bfd_link_hash_undefweak)
16357 {
16358 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16359 return false;
16360 }
16361
16362 s = htab->root.sgot;
16363 h->got.offset = s->size;
16364
16365 if (tls_type == GOT_UNKNOWN)
16366 abort ();
16367
16368 if (tls_type == GOT_NORMAL)
16369 /* Non-TLS symbols need one GOT slot. */
16370 s->size += 4;
16371 else
16372 {
16373 if (tls_type & GOT_TLS_GDESC)
16374 {
16375 /* R_ARM_TLS_DESC needs 2 GOT slots. */
16376 eh->tlsdesc_got
16377 = (htab->root.sgotplt->size
16378 - elf32_arm_compute_jump_table_size (htab));
16379 htab->root.sgotplt->size += 8;
16380 h->got.offset = (bfd_vma) -2;
16381 /* plt.got_offset needs to know there's a TLS_DESC
16382 reloc in the middle of .got.plt. */
16383 htab->num_tls_desc++;
16384 }
16385
16386 if (tls_type & GOT_TLS_GD)
16387 {
16388 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16389 consecutive GOT slots. If the symbol is both GD
16390 and GDESC, got.offset may have been
16391 overwritten. */
16392 h->got.offset = s->size;
16393 s->size += 8;
16394 }
16395
16396 if (tls_type & GOT_TLS_IE)
16397 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16398 slot. */
16399 s->size += 4;
16400 }
16401
16402 dyn = htab->root.dynamic_sections_created;
16403
16404 indx = 0;
16405 if (WILL_CALL_FINISH_DYNAMIC_SYMBOL (dyn, bfd_link_pic (info), h)
16406 && (!bfd_link_pic (info)
16407 || !SYMBOL_REFERENCES_LOCAL (info, h)))
16408 indx = h->dynindx;
16409
16410 if (tls_type != GOT_NORMAL
16411 && (bfd_link_dll (info) || indx != 0)
16412 && (ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
16413 || h->root.type != bfd_link_hash_undefweak))
16414 {
16415 if (tls_type & GOT_TLS_IE)
16416 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16417
16418 if (tls_type & GOT_TLS_GD)
16419 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16420
16421 if (tls_type & GOT_TLS_GDESC)
16422 {
16423 elf32_arm_allocate_dynrelocs (info, htab->root.srelplt, 1);
16424 /* GDESC needs a trampoline to jump to. */
16425 htab->tls_trampoline = -1;
16426 }
16427
16428 /* Only GD needs it. GDESC just emits one relocation per
16429 2 entries. */
16430 if ((tls_type & GOT_TLS_GD) && indx != 0)
16431 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16432 }
16433 else if (((indx != -1) || htab->fdpic_p)
16434 && !SYMBOL_REFERENCES_LOCAL (info, h))
16435 {
16436 if (htab->root.dynamic_sections_created)
16437 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16438 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16439 }
16440 else if (h->type == STT_GNU_IFUNC
16441 && eh->plt.noncall_refcount == 0)
16442 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16443 they all resolve dynamically instead. Reserve room for the
16444 GOT entry's R_ARM_IRELATIVE relocation. */
16445 elf32_arm_allocate_irelocs (info, htab->root.srelgot, 1);
16446 else if (bfd_link_pic (info)
16447 && !UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
16448 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
16449 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16450 else if (htab->fdpic_p && tls_type == GOT_NORMAL)
16451 /* Reserve room for rofixup for FDPIC executable. */
16452 /* TLS relocs do not need space since they are completely
16453 resolved. */
16454 htab->srofixup->size += 4;
16455 }
16456 else
16457 h->got.offset = (bfd_vma) -1;
16458
16459 /* FDPIC support. */
16460 if (eh->fdpic_cnts.gotofffuncdesc_cnt > 0)
16461 {
16462 /* Symbol musn't be exported. */
16463 if (h->dynindx != -1)
16464 abort ();
16465
16466 /* We only allocate one function descriptor with its associated
16467 relocation. */
16468 if (eh->fdpic_cnts.funcdesc_offset == -1)
16469 {
16470 asection *s = htab->root.sgot;
16471
16472 eh->fdpic_cnts.funcdesc_offset = s->size;
16473 s->size += 8;
16474 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16475 if (bfd_link_pic (info))
16476 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16477 else
16478 htab->srofixup->size += 8;
16479 }
16480 }
16481
16482 if (eh->fdpic_cnts.gotfuncdesc_cnt > 0)
16483 {
16484 asection *s = htab->root.sgot;
16485
16486 if (htab->root.dynamic_sections_created && h->dynindx == -1
16487 && !h->forced_local)
16488 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16489 return false;
16490
16491 if (h->dynindx == -1)
16492 {
16493 /* We only allocate one function descriptor with its
16494 associated relocation. */
16495 if (eh->fdpic_cnts.funcdesc_offset == -1)
16496 {
16497
16498 eh->fdpic_cnts.funcdesc_offset = s->size;
16499 s->size += 8;
16500 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16501 rofixups. */
16502 if (bfd_link_pic (info))
16503 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16504 else
16505 htab->srofixup->size += 8;
16506 }
16507 }
16508
16509 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16510 R_ARM_RELATIVE/rofixup relocation on it. */
16511 eh->fdpic_cnts.gotfuncdesc_offset = s->size;
16512 s->size += 4;
16513 if (h->dynindx == -1 && !bfd_link_pic (info))
16514 htab->srofixup->size += 4;
16515 else
16516 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16517 }
16518
16519 if (eh->fdpic_cnts.funcdesc_cnt > 0)
16520 {
16521 if (htab->root.dynamic_sections_created && h->dynindx == -1
16522 && !h->forced_local)
16523 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16524 return false;
16525
16526 if (h->dynindx == -1)
16527 {
16528 /* We only allocate one function descriptor with its
16529 associated relocation. */
16530 if (eh->fdpic_cnts.funcdesc_offset == -1)
16531 {
16532 asection *s = htab->root.sgot;
16533
16534 eh->fdpic_cnts.funcdesc_offset = s->size;
16535 s->size += 8;
16536 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16537 rofixups. */
16538 if (bfd_link_pic (info))
16539 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16540 else
16541 htab->srofixup->size += 8;
16542 }
16543 }
16544 if (h->dynindx == -1 && !bfd_link_pic (info))
16545 {
16546 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16547 htab->srofixup->size += 4 * eh->fdpic_cnts.funcdesc_cnt;
16548 }
16549 else
16550 {
16551 /* Will need one dynamic reloc per reference. will be either
16552 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16553 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot,
16554 eh->fdpic_cnts.funcdesc_cnt);
16555 }
16556 }
16557
16558 /* Allocate stubs for exported Thumb functions on v4t. */
16559 if (!htab->use_blx && h->dynindx != -1
16560 && h->def_regular
16561 && ARM_GET_SYM_BRANCH_TYPE (h->target_internal) == ST_BRANCH_TO_THUMB
16562 && ELF_ST_VISIBILITY (h->other) == STV_DEFAULT)
16563 {
16564 struct elf_link_hash_entry * th;
16565 struct bfd_link_hash_entry * bh;
16566 struct elf_link_hash_entry * myh;
16567 char name[1024];
16568 asection *s;
16569 bh = NULL;
16570 /* Create a new symbol to regist the real location of the function. */
16571 s = h->root.u.def.section;
16572 sprintf (name, "__real_%s", h->root.root.string);
16573 _bfd_generic_link_add_one_symbol (info, s->owner,
16574 name, BSF_GLOBAL, s,
16575 h->root.u.def.value,
16576 NULL, true, false, &bh);
16577
16578 myh = (struct elf_link_hash_entry *) bh;
16579 myh->type = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
16580 myh->forced_local = 1;
16581 ARM_SET_SYM_BRANCH_TYPE (myh->target_internal, ST_BRANCH_TO_THUMB);
16582 eh->export_glue = myh;
16583 th = record_arm_to_thumb_glue (info, h);
16584 /* Point the symbol at the stub. */
16585 h->type = ELF_ST_INFO (ELF_ST_BIND (h->type), STT_FUNC);
16586 ARM_SET_SYM_BRANCH_TYPE (h->target_internal, ST_BRANCH_TO_ARM);
16587 h->root.u.def.section = th->root.u.def.section;
16588 h->root.u.def.value = th->root.u.def.value & ~1;
16589 }
16590
16591 if (h->dyn_relocs == NULL)
16592 return true;
16593
16594 /* In the shared -Bsymbolic case, discard space allocated for
16595 dynamic pc-relative relocs against symbols which turn out to be
16596 defined in regular objects. For the normal shared case, discard
16597 space for pc-relative relocs that have become local due to symbol
16598 visibility changes. */
16599
16600 if (bfd_link_pic (info)
16601 || htab->root.is_relocatable_executable
16602 || htab->fdpic_p)
16603 {
16604 /* Relocs that use pc_count are PC-relative forms, which will appear
16605 on something like ".long foo - ." or "movw REG, foo - .". We want
16606 calls to protected symbols to resolve directly to the function
16607 rather than going via the plt. If people want function pointer
16608 comparisons to work as expected then they should avoid writing
16609 assembly like ".long foo - .". */
16610 if (SYMBOL_CALLS_LOCAL (info, h))
16611 {
16612 struct elf_dyn_relocs **pp;
16613
16614 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
16615 {
16616 p->count -= p->pc_count;
16617 p->pc_count = 0;
16618 if (p->count == 0)
16619 *pp = p->next;
16620 else
16621 pp = &p->next;
16622 }
16623 }
16624
16625 if (htab->root.target_os == is_vxworks)
16626 {
16627 struct elf_dyn_relocs **pp;
16628
16629 for (pp = &h->dyn_relocs; (p = *pp) != NULL; )
16630 {
16631 if (strcmp (p->sec->output_section->name, ".tls_vars") == 0)
16632 *pp = p->next;
16633 else
16634 pp = &p->next;
16635 }
16636 }
16637
16638 /* Also discard relocs on undefined weak syms with non-default
16639 visibility. */
16640 if (h->dyn_relocs != NULL
16641 && h->root.type == bfd_link_hash_undefweak)
16642 {
16643 if (ELF_ST_VISIBILITY (h->other) != STV_DEFAULT
16644 || UNDEFWEAK_NO_DYNAMIC_RELOC (info, h))
16645 h->dyn_relocs = NULL;
16646
16647 /* Make sure undefined weak symbols are output as a dynamic
16648 symbol in PIEs. */
16649 else if (htab->root.dynamic_sections_created && h->dynindx == -1
16650 && !h->forced_local)
16651 {
16652 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16653 return false;
16654 }
16655 }
16656
16657 else if (htab->root.is_relocatable_executable && h->dynindx == -1
16658 && h->root.type == bfd_link_hash_new)
16659 {
16660 /* Output absolute symbols so that we can create relocations
16661 against them. For normal symbols we output a relocation
16662 against the section that contains them. */
16663 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16664 return false;
16665 }
16666
16667 }
16668 else
16669 {
16670 /* For the non-shared case, discard space for relocs against
16671 symbols which turn out to need copy relocs or are not
16672 dynamic. */
16673
16674 if (!h->non_got_ref
16675 && ((h->def_dynamic
16676 && !h->def_regular)
16677 || (htab->root.dynamic_sections_created
16678 && (h->root.type == bfd_link_hash_undefweak
16679 || h->root.type == bfd_link_hash_undefined))))
16680 {
16681 /* Make sure this symbol is output as a dynamic symbol.
16682 Undefined weak syms won't yet be marked as dynamic. */
16683 if (h->dynindx == -1 && !h->forced_local
16684 && h->root.type == bfd_link_hash_undefweak)
16685 {
16686 if (! bfd_elf_link_record_dynamic_symbol (info, h))
16687 return false;
16688 }
16689
16690 /* If that succeeded, we know we'll be keeping all the
16691 relocs. */
16692 if (h->dynindx != -1)
16693 goto keep;
16694 }
16695
16696 h->dyn_relocs = NULL;
16697
16698 keep: ;
16699 }
16700
16701 /* Finally, allocate space. */
16702 for (p = h->dyn_relocs; p != NULL; p = p->next)
16703 {
16704 asection *sreloc = elf_section_data (p->sec)->sreloc;
16705
16706 if (h->type == STT_GNU_IFUNC
16707 && eh->plt.noncall_refcount == 0
16708 && SYMBOL_REFERENCES_LOCAL (info, h))
16709 elf32_arm_allocate_irelocs (info, sreloc, p->count);
16710 else if (h->dynindx != -1
16711 && (!bfd_link_pic (info) || !info->symbolic || !h->def_regular))
16712 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16713 else if (htab->fdpic_p && !bfd_link_pic (info))
16714 htab->srofixup->size += 4 * p->count;
16715 else
16716 elf32_arm_allocate_dynrelocs (info, sreloc, p->count);
16717 }
16718
16719 return true;
16720 }
16721
16722 void
16723 bfd_elf32_arm_set_byteswap_code (struct bfd_link_info *info,
16724 int byteswap_code)
16725 {
16726 struct elf32_arm_link_hash_table *globals;
16727
16728 globals = elf32_arm_hash_table (info);
16729 if (globals == NULL)
16730 return;
16731
16732 globals->byteswap_code = byteswap_code;
16733 }
16734
16735 /* Set the sizes of the dynamic sections. */
16736
16737 static bool
16738 elf32_arm_size_dynamic_sections (bfd * output_bfd ATTRIBUTE_UNUSED,
16739 struct bfd_link_info * info)
16740 {
16741 bfd * dynobj;
16742 asection * s;
16743 bool relocs;
16744 bfd *ibfd;
16745 struct elf32_arm_link_hash_table *htab;
16746
16747 htab = elf32_arm_hash_table (info);
16748 if (htab == NULL)
16749 return false;
16750
16751 dynobj = elf_hash_table (info)->dynobj;
16752 BFD_ASSERT (dynobj != NULL);
16753 check_use_blx (htab);
16754
16755 if (elf_hash_table (info)->dynamic_sections_created)
16756 {
16757 /* Set the contents of the .interp section to the interpreter. */
16758 if (bfd_link_executable (info) && !info->nointerp)
16759 {
16760 s = bfd_get_linker_section (dynobj, ".interp");
16761 BFD_ASSERT (s != NULL);
16762 s->size = sizeof ELF_DYNAMIC_INTERPRETER;
16763 s->contents = (unsigned char *) ELF_DYNAMIC_INTERPRETER;
16764 }
16765 }
16766
16767 /* Set up .got offsets for local syms, and space for local dynamic
16768 relocs. */
16769 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
16770 {
16771 bfd_signed_vma *local_got;
16772 bfd_signed_vma *end_local_got;
16773 struct arm_local_iplt_info **local_iplt_ptr, *local_iplt;
16774 char *local_tls_type;
16775 bfd_vma *local_tlsdesc_gotent;
16776 bfd_size_type locsymcount;
16777 Elf_Internal_Shdr *symtab_hdr;
16778 asection *srel;
16779 unsigned int symndx;
16780 struct fdpic_local *local_fdpic_cnts;
16781
16782 if (! is_arm_elf (ibfd))
16783 continue;
16784
16785 for (s = ibfd->sections; s != NULL; s = s->next)
16786 {
16787 struct elf_dyn_relocs *p;
16788
16789 for (p = (struct elf_dyn_relocs *)
16790 elf_section_data (s)->local_dynrel; p != NULL; p = p->next)
16791 {
16792 if (!bfd_is_abs_section (p->sec)
16793 && bfd_is_abs_section (p->sec->output_section))
16794 {
16795 /* Input section has been discarded, either because
16796 it is a copy of a linkonce section or due to
16797 linker script /DISCARD/, so we'll be discarding
16798 the relocs too. */
16799 }
16800 else if (htab->root.target_os == is_vxworks
16801 && strcmp (p->sec->output_section->name,
16802 ".tls_vars") == 0)
16803 {
16804 /* Relocations in vxworks .tls_vars sections are
16805 handled specially by the loader. */
16806 }
16807 else if (p->count != 0)
16808 {
16809 srel = elf_section_data (p->sec)->sreloc;
16810 if (htab->fdpic_p && !bfd_link_pic (info))
16811 htab->srofixup->size += 4 * p->count;
16812 else
16813 elf32_arm_allocate_dynrelocs (info, srel, p->count);
16814 if ((p->sec->output_section->flags & SEC_READONLY) != 0)
16815 info->flags |= DF_TEXTREL;
16816 }
16817 }
16818 }
16819
16820 local_got = elf_local_got_refcounts (ibfd);
16821 if (local_got == NULL)
16822 continue;
16823
16824 symtab_hdr = & elf_symtab_hdr (ibfd);
16825 locsymcount = symtab_hdr->sh_info;
16826 end_local_got = local_got + locsymcount;
16827 local_iplt_ptr = elf32_arm_local_iplt (ibfd);
16828 local_tls_type = elf32_arm_local_got_tls_type (ibfd);
16829 local_tlsdesc_gotent = elf32_arm_local_tlsdesc_gotent (ibfd);
16830 local_fdpic_cnts = elf32_arm_local_fdpic_cnts (ibfd);
16831 symndx = 0;
16832 s = htab->root.sgot;
16833 srel = htab->root.srelgot;
16834 for (; local_got < end_local_got;
16835 ++local_got, ++local_iplt_ptr, ++local_tls_type,
16836 ++local_tlsdesc_gotent, ++symndx, ++local_fdpic_cnts)
16837 {
16838 if (symndx >= elf32_arm_num_entries (ibfd))
16839 return false;
16840
16841 *local_tlsdesc_gotent = (bfd_vma) -1;
16842 local_iplt = *local_iplt_ptr;
16843
16844 /* FDPIC support. */
16845 if (local_fdpic_cnts->gotofffuncdesc_cnt > 0)
16846 {
16847 if (local_fdpic_cnts->funcdesc_offset == -1)
16848 {
16849 local_fdpic_cnts->funcdesc_offset = s->size;
16850 s->size += 8;
16851
16852 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16853 if (bfd_link_pic (info))
16854 elf32_arm_allocate_dynrelocs (info, srel, 1);
16855 else
16856 htab->srofixup->size += 8;
16857 }
16858 }
16859
16860 if (local_fdpic_cnts->funcdesc_cnt > 0)
16861 {
16862 if (local_fdpic_cnts->funcdesc_offset == -1)
16863 {
16864 local_fdpic_cnts->funcdesc_offset = s->size;
16865 s->size += 8;
16866
16867 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16868 if (bfd_link_pic (info))
16869 elf32_arm_allocate_dynrelocs (info, srel, 1);
16870 else
16871 htab->srofixup->size += 8;
16872 }
16873
16874 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16875 if (bfd_link_pic (info))
16876 elf32_arm_allocate_dynrelocs (info, srel, local_fdpic_cnts->funcdesc_cnt);
16877 else
16878 htab->srofixup->size += 4 * local_fdpic_cnts->funcdesc_cnt;
16879 }
16880
16881 if (local_iplt != NULL)
16882 {
16883 struct elf_dyn_relocs *p;
16884
16885 if (local_iplt->root.refcount > 0)
16886 {
16887 elf32_arm_allocate_plt_entry (info, true,
16888 &local_iplt->root,
16889 &local_iplt->arm);
16890 if (local_iplt->arm.noncall_refcount == 0)
16891 /* All references to the PLT are calls, so all
16892 non-call references can resolve directly to the
16893 run-time target. This means that the .got entry
16894 would be the same as the .igot.plt entry, so there's
16895 no point creating both. */
16896 *local_got = 0;
16897 }
16898 else
16899 {
16900 BFD_ASSERT (local_iplt->arm.noncall_refcount == 0);
16901 local_iplt->root.offset = (bfd_vma) -1;
16902 }
16903
16904 for (p = local_iplt->dyn_relocs; p != NULL; p = p->next)
16905 {
16906 asection *psrel;
16907
16908 psrel = elf_section_data (p->sec)->sreloc;
16909 if (local_iplt->arm.noncall_refcount == 0)
16910 elf32_arm_allocate_irelocs (info, psrel, p->count);
16911 else
16912 elf32_arm_allocate_dynrelocs (info, psrel, p->count);
16913 }
16914 }
16915 if (*local_got > 0)
16916 {
16917 Elf_Internal_Sym *isym;
16918
16919 *local_got = s->size;
16920 if (*local_tls_type & GOT_TLS_GD)
16921 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16922 s->size += 8;
16923 if (*local_tls_type & GOT_TLS_GDESC)
16924 {
16925 *local_tlsdesc_gotent = htab->root.sgotplt->size
16926 - elf32_arm_compute_jump_table_size (htab);
16927 htab->root.sgotplt->size += 8;
16928 *local_got = (bfd_vma) -2;
16929 /* plt.got_offset needs to know there's a TLS_DESC
16930 reloc in the middle of .got.plt. */
16931 htab->num_tls_desc++;
16932 }
16933 if (*local_tls_type & GOT_TLS_IE)
16934 s->size += 4;
16935
16936 if (*local_tls_type & GOT_NORMAL)
16937 {
16938 /* If the symbol is both GD and GDESC, *local_got
16939 may have been overwritten. */
16940 *local_got = s->size;
16941 s->size += 4;
16942 }
16943
16944 isym = bfd_sym_from_r_symndx (&htab->root.sym_cache, ibfd,
16945 symndx);
16946 if (isym == NULL)
16947 return false;
16948
16949 /* If all references to an STT_GNU_IFUNC PLT are calls,
16950 then all non-call references, including this GOT entry,
16951 resolve directly to the run-time target. */
16952 if (ELF32_ST_TYPE (isym->st_info) == STT_GNU_IFUNC
16953 && (local_iplt == NULL
16954 || local_iplt->arm.noncall_refcount == 0))
16955 elf32_arm_allocate_irelocs (info, srel, 1);
16956 else if (bfd_link_pic (info) || output_bfd->flags & DYNAMIC || htab->fdpic_p)
16957 {
16958 if ((bfd_link_pic (info) && !(*local_tls_type & GOT_TLS_GDESC)))
16959 elf32_arm_allocate_dynrelocs (info, srel, 1);
16960 else if (htab->fdpic_p && *local_tls_type & GOT_NORMAL)
16961 htab->srofixup->size += 4;
16962
16963 if ((bfd_link_pic (info) || htab->fdpic_p)
16964 && *local_tls_type & GOT_TLS_GDESC)
16965 {
16966 elf32_arm_allocate_dynrelocs (info,
16967 htab->root.srelplt, 1);
16968 htab->tls_trampoline = -1;
16969 }
16970 }
16971 }
16972 else
16973 *local_got = (bfd_vma) -1;
16974 }
16975 }
16976
16977 if (htab->tls_ldm_got.refcount > 0)
16978 {
16979 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16980 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
16981 htab->tls_ldm_got.offset = htab->root.sgot->size;
16982 htab->root.sgot->size += 8;
16983 if (bfd_link_pic (info))
16984 elf32_arm_allocate_dynrelocs (info, htab->root.srelgot, 1);
16985 }
16986 else
16987 htab->tls_ldm_got.offset = -1;
16988
16989 /* At the very end of the .rofixup section is a pointer to the GOT,
16990 reserve space for it. */
16991 if (htab->fdpic_p && htab->srofixup != NULL)
16992 htab->srofixup->size += 4;
16993
16994 /* Allocate global sym .plt and .got entries, and space for global
16995 sym dynamic relocs. */
16996 elf_link_hash_traverse (& htab->root, allocate_dynrelocs_for_symbol, info);
16997
16998 /* Here we rummage through the found bfds to collect glue information. */
16999 for (ibfd = info->input_bfds; ibfd != NULL; ibfd = ibfd->link.next)
17000 {
17001 if (! is_arm_elf (ibfd))
17002 continue;
17003
17004 /* Initialise mapping tables for code/data. */
17005 bfd_elf32_arm_init_maps (ibfd);
17006
17007 if (!bfd_elf32_arm_process_before_allocation (ibfd, info)
17008 || !bfd_elf32_arm_vfp11_erratum_scan (ibfd, info)
17009 || !bfd_elf32_arm_stm32l4xx_erratum_scan (ibfd, info))
17010 _bfd_error_handler (_("errors encountered processing file %pB"), ibfd);
17011 }
17012
17013 /* Allocate space for the glue sections now that we've sized them. */
17014 bfd_elf32_arm_allocate_interworking_sections (info);
17015
17016 /* For every jump slot reserved in the sgotplt, reloc_count is
17017 incremented. However, when we reserve space for TLS descriptors,
17018 it's not incremented, so in order to compute the space reserved
17019 for them, it suffices to multiply the reloc count by the jump
17020 slot size. */
17021 if (htab->root.srelplt)
17022 htab->sgotplt_jump_table_size = elf32_arm_compute_jump_table_size (htab);
17023
17024 if (htab->tls_trampoline)
17025 {
17026 if (htab->root.splt->size == 0)
17027 htab->root.splt->size += htab->plt_header_size;
17028
17029 htab->tls_trampoline = htab->root.splt->size;
17030 htab->root.splt->size += htab->plt_entry_size;
17031
17032 /* If we're not using lazy TLS relocations, don't generate the
17033 PLT and GOT entries they require. */
17034 if ((info->flags & DF_BIND_NOW))
17035 htab->root.tlsdesc_plt = 0;
17036 else
17037 {
17038 htab->root.tlsdesc_got = htab->root.sgot->size;
17039 htab->root.sgot->size += 4;
17040
17041 htab->root.tlsdesc_plt = htab->root.splt->size;
17042 htab->root.splt->size += 4 * ARRAY_SIZE (dl_tlsdesc_lazy_trampoline);
17043 }
17044 }
17045
17046 /* The check_relocs and adjust_dynamic_symbol entry points have
17047 determined the sizes of the various dynamic sections. Allocate
17048 memory for them. */
17049 relocs = false;
17050 for (s = dynobj->sections; s != NULL; s = s->next)
17051 {
17052 const char * name;
17053
17054 if ((s->flags & SEC_LINKER_CREATED) == 0)
17055 continue;
17056
17057 /* It's OK to base decisions on the section name, because none
17058 of the dynobj section names depend upon the input files. */
17059 name = bfd_section_name (s);
17060
17061 if (s == htab->root.splt)
17062 {
17063 /* Remember whether there is a PLT. */
17064 ;
17065 }
17066 else if (startswith (name, ".rel"))
17067 {
17068 if (s->size != 0)
17069 {
17070 /* Remember whether there are any reloc sections other
17071 than .rel(a).plt and .rela.plt.unloaded. */
17072 if (s != htab->root.srelplt && s != htab->srelplt2)
17073 relocs = true;
17074
17075 /* We use the reloc_count field as a counter if we need
17076 to copy relocs into the output file. */
17077 s->reloc_count = 0;
17078 }
17079 }
17080 else if (s != htab->root.sgot
17081 && s != htab->root.sgotplt
17082 && s != htab->root.iplt
17083 && s != htab->root.igotplt
17084 && s != htab->root.sdynbss
17085 && s != htab->root.sdynrelro
17086 && s != htab->srofixup)
17087 {
17088 /* It's not one of our sections, so don't allocate space. */
17089 continue;
17090 }
17091
17092 if (s->size == 0)
17093 {
17094 /* If we don't need this section, strip it from the
17095 output file. This is mostly to handle .rel(a).bss and
17096 .rel(a).plt. We must create both sections in
17097 create_dynamic_sections, because they must be created
17098 before the linker maps input sections to output
17099 sections. The linker does that before
17100 adjust_dynamic_symbol is called, and it is that
17101 function which decides whether anything needs to go
17102 into these sections. */
17103 s->flags |= SEC_EXCLUDE;
17104 continue;
17105 }
17106
17107 if ((s->flags & SEC_HAS_CONTENTS) == 0)
17108 continue;
17109
17110 /* Allocate memory for the section contents. */
17111 s->contents = (unsigned char *) bfd_zalloc (dynobj, s->size);
17112 if (s->contents == NULL)
17113 return false;
17114 }
17115
17116 return _bfd_elf_maybe_vxworks_add_dynamic_tags (output_bfd, info,
17117 relocs);
17118 }
17119
17120 /* Size sections even though they're not dynamic. We use it to setup
17121 _TLS_MODULE_BASE_, if needed. */
17122
17123 static bool
17124 elf32_arm_always_size_sections (bfd *output_bfd,
17125 struct bfd_link_info *info)
17126 {
17127 asection *tls_sec;
17128 struct elf32_arm_link_hash_table *htab;
17129
17130 htab = elf32_arm_hash_table (info);
17131
17132 if (bfd_link_relocatable (info))
17133 return true;
17134
17135 tls_sec = elf_hash_table (info)->tls_sec;
17136
17137 if (tls_sec)
17138 {
17139 struct elf_link_hash_entry *tlsbase;
17140
17141 tlsbase = elf_link_hash_lookup
17142 (elf_hash_table (info), "_TLS_MODULE_BASE_", true, true, false);
17143
17144 if (tlsbase)
17145 {
17146 struct bfd_link_hash_entry *bh = NULL;
17147 const struct elf_backend_data *bed
17148 = get_elf_backend_data (output_bfd);
17149
17150 if (!(_bfd_generic_link_add_one_symbol
17151 (info, output_bfd, "_TLS_MODULE_BASE_", BSF_LOCAL,
17152 tls_sec, 0, NULL, false,
17153 bed->collect, &bh)))
17154 return false;
17155
17156 tlsbase->type = STT_TLS;
17157 tlsbase = (struct elf_link_hash_entry *)bh;
17158 tlsbase->def_regular = 1;
17159 tlsbase->other = STV_HIDDEN;
17160 (*bed->elf_backend_hide_symbol) (info, tlsbase, true);
17161 }
17162 }
17163
17164 if (htab->fdpic_p && !bfd_link_relocatable (info)
17165 && !bfd_elf_stack_segment_size (output_bfd, info,
17166 "__stacksize", DEFAULT_STACK_SIZE))
17167 return false;
17168
17169 return true;
17170 }
17171
17172 /* Finish up dynamic symbol handling. We set the contents of various
17173 dynamic sections here. */
17174
17175 static bool
17176 elf32_arm_finish_dynamic_symbol (bfd * output_bfd,
17177 struct bfd_link_info * info,
17178 struct elf_link_hash_entry * h,
17179 Elf_Internal_Sym * sym)
17180 {
17181 struct elf32_arm_link_hash_table *htab;
17182 struct elf32_arm_link_hash_entry *eh;
17183
17184 htab = elf32_arm_hash_table (info);
17185 if (htab == NULL)
17186 return false;
17187
17188 eh = (struct elf32_arm_link_hash_entry *) h;
17189
17190 if (h->plt.offset != (bfd_vma) -1)
17191 {
17192 if (!eh->is_iplt)
17193 {
17194 BFD_ASSERT (h->dynindx != -1);
17195 if (! elf32_arm_populate_plt_entry (output_bfd, info, &h->plt, &eh->plt,
17196 h->dynindx, 0))
17197 return false;
17198 }
17199
17200 if (!h->def_regular)
17201 {
17202 /* Mark the symbol as undefined, rather than as defined in
17203 the .plt section. */
17204 sym->st_shndx = SHN_UNDEF;
17205 /* If the symbol is weak we need to clear the value.
17206 Otherwise, the PLT entry would provide a definition for
17207 the symbol even if the symbol wasn't defined anywhere,
17208 and so the symbol would never be NULL. Leave the value if
17209 there were any relocations where pointer equality matters
17210 (this is a clue for the dynamic linker, to make function
17211 pointer comparisons work between an application and shared
17212 library). */
17213 if (!h->ref_regular_nonweak || !h->pointer_equality_needed)
17214 sym->st_value = 0;
17215 }
17216 else if (eh->is_iplt && eh->plt.noncall_refcount != 0)
17217 {
17218 /* At least one non-call relocation references this .iplt entry,
17219 so the .iplt entry is the function's canonical address. */
17220 sym->st_info = ELF_ST_INFO (ELF_ST_BIND (sym->st_info), STT_FUNC);
17221 ARM_SET_SYM_BRANCH_TYPE (sym->st_target_internal, ST_BRANCH_TO_ARM);
17222 sym->st_shndx = (_bfd_elf_section_from_bfd_section
17223 (output_bfd, htab->root.iplt->output_section));
17224 sym->st_value = (h->plt.offset
17225 + htab->root.iplt->output_section->vma
17226 + htab->root.iplt->output_offset);
17227 }
17228 }
17229
17230 if (h->needs_copy)
17231 {
17232 asection * s;
17233 Elf_Internal_Rela rel;
17234
17235 /* This symbol needs a copy reloc. Set it up. */
17236 BFD_ASSERT (h->dynindx != -1
17237 && (h->root.type == bfd_link_hash_defined
17238 || h->root.type == bfd_link_hash_defweak));
17239
17240 rel.r_addend = 0;
17241 rel.r_offset = (h->root.u.def.value
17242 + h->root.u.def.section->output_section->vma
17243 + h->root.u.def.section->output_offset);
17244 rel.r_info = ELF32_R_INFO (h->dynindx, R_ARM_COPY);
17245 if (h->root.u.def.section == htab->root.sdynrelro)
17246 s = htab->root.sreldynrelro;
17247 else
17248 s = htab->root.srelbss;
17249 elf32_arm_add_dynreloc (output_bfd, info, s, &rel);
17250 }
17251
17252 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
17253 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17254 it is relative to the ".got" section. */
17255 if (h == htab->root.hdynamic
17256 || (!htab->fdpic_p
17257 && htab->root.target_os != is_vxworks
17258 && h == htab->root.hgot))
17259 sym->st_shndx = SHN_ABS;
17260
17261 return true;
17262 }
17263
17264 static void
17265 arm_put_trampoline (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17266 void *contents,
17267 const unsigned long *template, unsigned count)
17268 {
17269 unsigned ix;
17270
17271 for (ix = 0; ix != count; ix++)
17272 {
17273 unsigned long insn = template[ix];
17274
17275 /* Emit mov pc,rx if bx is not permitted. */
17276 if (htab->fix_v4bx == 1 && (insn & 0x0ffffff0) == 0x012fff10)
17277 insn = (insn & 0xf000000f) | 0x01a0f000;
17278 put_arm_insn (htab, output_bfd, insn, (char *)contents + ix*4);
17279 }
17280 }
17281
17282 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
17283 other variants, NaCl needs this entry in a static executable's
17284 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17285 zero. For .iplt really only the last bundle is useful, and .iplt
17286 could have a shorter first entry, with each individual PLT entry's
17287 relative branch calculated differently so it targets the last
17288 bundle instead of the instruction before it (labelled .Lplt_tail
17289 above). But it's simpler to keep the size and layout of PLT0
17290 consistent with the dynamic case, at the cost of some dead code at
17291 the start of .iplt and the one dead store to the stack at the start
17292 of .Lplt_tail. */
17293 static void
17294 arm_nacl_put_plt0 (struct elf32_arm_link_hash_table *htab, bfd *output_bfd,
17295 asection *plt, bfd_vma got_displacement)
17296 {
17297 unsigned int i;
17298
17299 put_arm_insn (htab, output_bfd,
17300 elf32_arm_nacl_plt0_entry[0]
17301 | arm_movw_immediate (got_displacement),
17302 plt->contents + 0);
17303 put_arm_insn (htab, output_bfd,
17304 elf32_arm_nacl_plt0_entry[1]
17305 | arm_movt_immediate (got_displacement),
17306 plt->contents + 4);
17307
17308 for (i = 2; i < ARRAY_SIZE (elf32_arm_nacl_plt0_entry); ++i)
17309 put_arm_insn (htab, output_bfd,
17310 elf32_arm_nacl_plt0_entry[i],
17311 plt->contents + (i * 4));
17312 }
17313
17314 /* Finish up the dynamic sections. */
17315
17316 static bool
17317 elf32_arm_finish_dynamic_sections (bfd * output_bfd, struct bfd_link_info * info)
17318 {
17319 bfd * dynobj;
17320 asection * sgot;
17321 asection * sdyn;
17322 struct elf32_arm_link_hash_table *htab;
17323
17324 htab = elf32_arm_hash_table (info);
17325 if (htab == NULL)
17326 return false;
17327
17328 dynobj = elf_hash_table (info)->dynobj;
17329
17330 sgot = htab->root.sgotplt;
17331 /* A broken linker script might have discarded the dynamic sections.
17332 Catch this here so that we do not seg-fault later on. */
17333 if (sgot != NULL && bfd_is_abs_section (sgot->output_section))
17334 return false;
17335 sdyn = bfd_get_linker_section (dynobj, ".dynamic");
17336
17337 if (elf_hash_table (info)->dynamic_sections_created)
17338 {
17339 asection *splt;
17340 Elf32_External_Dyn *dyncon, *dynconend;
17341
17342 splt = htab->root.splt;
17343 BFD_ASSERT (splt != NULL && sdyn != NULL);
17344 BFD_ASSERT (sgot != NULL);
17345
17346 dyncon = (Elf32_External_Dyn *) sdyn->contents;
17347 dynconend = (Elf32_External_Dyn *) (sdyn->contents + sdyn->size);
17348
17349 for (; dyncon < dynconend; dyncon++)
17350 {
17351 Elf_Internal_Dyn dyn;
17352 const char * name;
17353 asection * s;
17354
17355 bfd_elf32_swap_dyn_in (dynobj, dyncon, &dyn);
17356
17357 switch (dyn.d_tag)
17358 {
17359 default:
17360 if (htab->root.target_os == is_vxworks
17361 && elf_vxworks_finish_dynamic_entry (output_bfd, &dyn))
17362 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17363 break;
17364
17365 case DT_HASH:
17366 case DT_STRTAB:
17367 case DT_SYMTAB:
17368 case DT_VERSYM:
17369 case DT_VERDEF:
17370 case DT_VERNEED:
17371 break;
17372
17373 case DT_PLTGOT:
17374 name = ".got.plt";
17375 goto get_vma;
17376 case DT_JMPREL:
17377 name = RELOC_SECTION (htab, ".plt");
17378 get_vma:
17379 s = bfd_get_linker_section (dynobj, name);
17380 if (s == NULL)
17381 {
17382 _bfd_error_handler
17383 (_("could not find section %s"), name);
17384 bfd_set_error (bfd_error_invalid_operation);
17385 return false;
17386 }
17387 dyn.d_un.d_ptr = s->output_section->vma + s->output_offset;
17388 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17389 break;
17390
17391 case DT_PLTRELSZ:
17392 s = htab->root.srelplt;
17393 BFD_ASSERT (s != NULL);
17394 dyn.d_un.d_val = s->size;
17395 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17396 break;
17397
17398 case DT_RELSZ:
17399 case DT_RELASZ:
17400 case DT_REL:
17401 case DT_RELA:
17402 break;
17403
17404 case DT_TLSDESC_PLT:
17405 s = htab->root.splt;
17406 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17407 + htab->root.tlsdesc_plt);
17408 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17409 break;
17410
17411 case DT_TLSDESC_GOT:
17412 s = htab->root.sgot;
17413 dyn.d_un.d_ptr = (s->output_section->vma + s->output_offset
17414 + htab->root.tlsdesc_got);
17415 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17416 break;
17417
17418 /* Set the bottom bit of DT_INIT/FINI if the
17419 corresponding function is Thumb. */
17420 case DT_INIT:
17421 name = info->init_function;
17422 goto get_sym;
17423 case DT_FINI:
17424 name = info->fini_function;
17425 get_sym:
17426 /* If it wasn't set by elf_bfd_final_link
17427 then there is nothing to adjust. */
17428 if (dyn.d_un.d_val != 0)
17429 {
17430 struct elf_link_hash_entry * eh;
17431
17432 eh = elf_link_hash_lookup (elf_hash_table (info), name,
17433 false, false, true);
17434 if (eh != NULL
17435 && ARM_GET_SYM_BRANCH_TYPE (eh->target_internal)
17436 == ST_BRANCH_TO_THUMB)
17437 {
17438 dyn.d_un.d_val |= 1;
17439 bfd_elf32_swap_dyn_out (output_bfd, &dyn, dyncon);
17440 }
17441 }
17442 break;
17443 }
17444 }
17445
17446 /* Fill in the first entry in the procedure linkage table. */
17447 if (splt->size > 0 && htab->plt_header_size)
17448 {
17449 const bfd_vma *plt0_entry;
17450 bfd_vma got_address, plt_address, got_displacement;
17451
17452 /* Calculate the addresses of the GOT and PLT. */
17453 got_address = sgot->output_section->vma + sgot->output_offset;
17454 plt_address = splt->output_section->vma + splt->output_offset;
17455
17456 if (htab->root.target_os == is_vxworks)
17457 {
17458 /* The VxWorks GOT is relocated by the dynamic linker.
17459 Therefore, we must emit relocations rather than simply
17460 computing the values now. */
17461 Elf_Internal_Rela rel;
17462
17463 plt0_entry = elf32_arm_vxworks_exec_plt0_entry;
17464 put_arm_insn (htab, output_bfd, plt0_entry[0],
17465 splt->contents + 0);
17466 put_arm_insn (htab, output_bfd, plt0_entry[1],
17467 splt->contents + 4);
17468 put_arm_insn (htab, output_bfd, plt0_entry[2],
17469 splt->contents + 8);
17470 bfd_put_32 (output_bfd, got_address, splt->contents + 12);
17471
17472 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
17473 rel.r_offset = plt_address + 12;
17474 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17475 rel.r_addend = 0;
17476 SWAP_RELOC_OUT (htab) (output_bfd, &rel,
17477 htab->srelplt2->contents);
17478 }
17479 else if (htab->root.target_os == is_nacl)
17480 arm_nacl_put_plt0 (htab, output_bfd, splt,
17481 got_address + 8 - (plt_address + 16));
17482 else if (using_thumb_only (htab))
17483 {
17484 got_displacement = got_address - (plt_address + 12);
17485
17486 plt0_entry = elf32_thumb2_plt0_entry;
17487 put_arm_insn (htab, output_bfd, plt0_entry[0],
17488 splt->contents + 0);
17489 put_arm_insn (htab, output_bfd, plt0_entry[1],
17490 splt->contents + 4);
17491 put_arm_insn (htab, output_bfd, plt0_entry[2],
17492 splt->contents + 8);
17493
17494 bfd_put_32 (output_bfd, got_displacement, splt->contents + 12);
17495 }
17496 else
17497 {
17498 got_displacement = got_address - (plt_address + 16);
17499
17500 plt0_entry = elf32_arm_plt0_entry;
17501 put_arm_insn (htab, output_bfd, plt0_entry[0],
17502 splt->contents + 0);
17503 put_arm_insn (htab, output_bfd, plt0_entry[1],
17504 splt->contents + 4);
17505 put_arm_insn (htab, output_bfd, plt0_entry[2],
17506 splt->contents + 8);
17507 put_arm_insn (htab, output_bfd, plt0_entry[3],
17508 splt->contents + 12);
17509
17510 #ifdef FOUR_WORD_PLT
17511 /* The displacement value goes in the otherwise-unused
17512 last word of the second entry. */
17513 bfd_put_32 (output_bfd, got_displacement, splt->contents + 28);
17514 #else
17515 bfd_put_32 (output_bfd, got_displacement, splt->contents + 16);
17516 #endif
17517 }
17518 }
17519
17520 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17521 really seem like the right value. */
17522 if (splt->output_section->owner == output_bfd)
17523 elf_section_data (splt->output_section)->this_hdr.sh_entsize = 4;
17524
17525 if (htab->root.tlsdesc_plt)
17526 {
17527 bfd_vma got_address
17528 = sgot->output_section->vma + sgot->output_offset;
17529 bfd_vma gotplt_address = (htab->root.sgot->output_section->vma
17530 + htab->root.sgot->output_offset);
17531 bfd_vma plt_address
17532 = splt->output_section->vma + splt->output_offset;
17533
17534 arm_put_trampoline (htab, output_bfd,
17535 splt->contents + htab->root.tlsdesc_plt,
17536 dl_tlsdesc_lazy_trampoline, 6);
17537
17538 bfd_put_32 (output_bfd,
17539 gotplt_address + htab->root.tlsdesc_got
17540 - (plt_address + htab->root.tlsdesc_plt)
17541 - dl_tlsdesc_lazy_trampoline[6],
17542 splt->contents + htab->root.tlsdesc_plt + 24);
17543 bfd_put_32 (output_bfd,
17544 got_address - (plt_address + htab->root.tlsdesc_plt)
17545 - dl_tlsdesc_lazy_trampoline[7],
17546 splt->contents + htab->root.tlsdesc_plt + 24 + 4);
17547 }
17548
17549 if (htab->tls_trampoline)
17550 {
17551 arm_put_trampoline (htab, output_bfd,
17552 splt->contents + htab->tls_trampoline,
17553 tls_trampoline, 3);
17554 #ifdef FOUR_WORD_PLT
17555 bfd_put_32 (output_bfd, 0x00000000,
17556 splt->contents + htab->tls_trampoline + 12);
17557 #endif
17558 }
17559
17560 if (htab->root.target_os == is_vxworks
17561 && !bfd_link_pic (info)
17562 && htab->root.splt->size > 0)
17563 {
17564 /* Correct the .rel(a).plt.unloaded relocations. They will have
17565 incorrect symbol indexes. */
17566 int num_plts;
17567 unsigned char *p;
17568
17569 num_plts = ((htab->root.splt->size - htab->plt_header_size)
17570 / htab->plt_entry_size);
17571 p = htab->srelplt2->contents + RELOC_SIZE (htab);
17572
17573 for (; num_plts; num_plts--)
17574 {
17575 Elf_Internal_Rela rel;
17576
17577 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17578 rel.r_info = ELF32_R_INFO (htab->root.hgot->indx, R_ARM_ABS32);
17579 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17580 p += RELOC_SIZE (htab);
17581
17582 SWAP_RELOC_IN (htab) (output_bfd, p, &rel);
17583 rel.r_info = ELF32_R_INFO (htab->root.hplt->indx, R_ARM_ABS32);
17584 SWAP_RELOC_OUT (htab) (output_bfd, &rel, p);
17585 p += RELOC_SIZE (htab);
17586 }
17587 }
17588 }
17589
17590 if (htab->root.target_os == is_nacl
17591 && htab->root.iplt != NULL
17592 && htab->root.iplt->size > 0)
17593 /* NaCl uses a special first entry in .iplt too. */
17594 arm_nacl_put_plt0 (htab, output_bfd, htab->root.iplt, 0);
17595
17596 /* Fill in the first three entries in the global offset table. */
17597 if (sgot)
17598 {
17599 if (sgot->size > 0)
17600 {
17601 if (sdyn == NULL)
17602 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents);
17603 else
17604 bfd_put_32 (output_bfd,
17605 sdyn->output_section->vma + sdyn->output_offset,
17606 sgot->contents);
17607 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 4);
17608 bfd_put_32 (output_bfd, (bfd_vma) 0, sgot->contents + 8);
17609 }
17610
17611 elf_section_data (sgot->output_section)->this_hdr.sh_entsize = 4;
17612 }
17613
17614 /* At the very end of the .rofixup section is a pointer to the GOT. */
17615 if (htab->fdpic_p && htab->srofixup != NULL)
17616 {
17617 struct elf_link_hash_entry *hgot = htab->root.hgot;
17618
17619 bfd_vma got_value = hgot->root.u.def.value
17620 + hgot->root.u.def.section->output_section->vma
17621 + hgot->root.u.def.section->output_offset;
17622
17623 arm_elf_add_rofixup (output_bfd, htab->srofixup, got_value);
17624
17625 /* Make sure we allocated and generated the same number of fixups. */
17626 BFD_ASSERT (htab->srofixup->reloc_count * 4 == htab->srofixup->size);
17627 }
17628
17629 return true;
17630 }
17631
17632 static bool
17633 elf32_arm_init_file_header (bfd *abfd, struct bfd_link_info *link_info)
17634 {
17635 Elf_Internal_Ehdr * i_ehdrp; /* ELF file header, internal form. */
17636 struct elf32_arm_link_hash_table *globals;
17637 struct elf_segment_map *m;
17638
17639 if (!_bfd_elf_init_file_header (abfd, link_info))
17640 return false;
17641
17642 i_ehdrp = elf_elfheader (abfd);
17643
17644 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_UNKNOWN)
17645 i_ehdrp->e_ident[EI_OSABI] = ELFOSABI_ARM;
17646 i_ehdrp->e_ident[EI_ABIVERSION] = ARM_ELF_ABI_VERSION;
17647
17648 if (link_info)
17649 {
17650 globals = elf32_arm_hash_table (link_info);
17651 if (globals != NULL && globals->byteswap_code)
17652 i_ehdrp->e_flags |= EF_ARM_BE8;
17653
17654 if (globals->fdpic_p)
17655 i_ehdrp->e_ident[EI_OSABI] |= ELFOSABI_ARM_FDPIC;
17656 }
17657
17658 if (EF_ARM_EABI_VERSION (i_ehdrp->e_flags) == EF_ARM_EABI_VER5
17659 && ((i_ehdrp->e_type == ET_DYN) || (i_ehdrp->e_type == ET_EXEC)))
17660 {
17661 int abi = bfd_elf_get_obj_attr_int (abfd, OBJ_ATTR_PROC, Tag_ABI_VFP_args);
17662 if (abi == AEABI_VFP_args_vfp)
17663 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_HARD;
17664 else
17665 i_ehdrp->e_flags |= EF_ARM_ABI_FLOAT_SOFT;
17666 }
17667
17668 /* Scan segment to set p_flags attribute if it contains only sections with
17669 SHF_ARM_PURECODE flag. */
17670 for (m = elf_seg_map (abfd); m != NULL; m = m->next)
17671 {
17672 unsigned int j;
17673
17674 if (m->count == 0)
17675 continue;
17676 for (j = 0; j < m->count; j++)
17677 {
17678 if (!(elf_section_flags (m->sections[j]) & SHF_ARM_PURECODE))
17679 break;
17680 }
17681 if (j == m->count)
17682 {
17683 m->p_flags = PF_X;
17684 m->p_flags_valid = 1;
17685 }
17686 }
17687 return true;
17688 }
17689
17690 static enum elf_reloc_type_class
17691 elf32_arm_reloc_type_class (const struct bfd_link_info *info ATTRIBUTE_UNUSED,
17692 const asection *rel_sec ATTRIBUTE_UNUSED,
17693 const Elf_Internal_Rela *rela)
17694 {
17695 struct elf32_arm_link_hash_table *htab = elf32_arm_hash_table (info);
17696
17697 if (htab->root.dynsym != NULL
17698 && htab->root.dynsym->contents != NULL)
17699 {
17700 /* Check relocation against STT_GNU_IFUNC symbol if there are
17701 dynamic symbols. */
17702 bfd *abfd = info->output_bfd;
17703 const struct elf_backend_data *bed = get_elf_backend_data (abfd);
17704 unsigned long r_symndx = ELF32_R_SYM (rela->r_info);
17705 if (r_symndx != STN_UNDEF)
17706 {
17707 Elf_Internal_Sym sym;
17708 if (!bed->s->swap_symbol_in (abfd,
17709 (htab->root.dynsym->contents
17710 + r_symndx * bed->s->sizeof_sym),
17711 0, &sym))
17712 {
17713 /* xgettext:c-format */
17714 _bfd_error_handler (_("%pB symbol number %lu references"
17715 " nonexistent SHT_SYMTAB_SHNDX section"),
17716 abfd, r_symndx);
17717 /* Ideally an error class should be returned here. */
17718 }
17719 else if (ELF_ST_TYPE (sym.st_info) == STT_GNU_IFUNC)
17720 return reloc_class_ifunc;
17721 }
17722 }
17723
17724 switch ((int) ELF32_R_TYPE (rela->r_info))
17725 {
17726 case R_ARM_RELATIVE:
17727 return reloc_class_relative;
17728 case R_ARM_JUMP_SLOT:
17729 return reloc_class_plt;
17730 case R_ARM_COPY:
17731 return reloc_class_copy;
17732 case R_ARM_IRELATIVE:
17733 return reloc_class_ifunc;
17734 default:
17735 return reloc_class_normal;
17736 }
17737 }
17738
17739 static void
17740 arm_final_write_processing (bfd *abfd)
17741 {
17742 bfd_arm_update_notes (abfd, ARM_NOTE_SECTION);
17743 }
17744
17745 static bool
17746 elf32_arm_final_write_processing (bfd *abfd)
17747 {
17748 arm_final_write_processing (abfd);
17749 return _bfd_elf_final_write_processing (abfd);
17750 }
17751
17752 /* Return TRUE if this is an unwinding table entry. */
17753
17754 static bool
17755 is_arm_elf_unwind_section_name (bfd * abfd ATTRIBUTE_UNUSED, const char * name)
17756 {
17757 return (startswith (name, ELF_STRING_ARM_unwind)
17758 || startswith (name, ELF_STRING_ARM_unwind_once));
17759 }
17760
17761
17762 /* Set the type and flags for an ARM section. We do this by
17763 the section name, which is a hack, but ought to work. */
17764
17765 static bool
17766 elf32_arm_fake_sections (bfd * abfd, Elf_Internal_Shdr * hdr, asection * sec)
17767 {
17768 const char * name;
17769
17770 name = bfd_section_name (sec);
17771
17772 if (is_arm_elf_unwind_section_name (abfd, name))
17773 {
17774 hdr->sh_type = SHT_ARM_EXIDX;
17775 hdr->sh_flags |= SHF_LINK_ORDER;
17776 }
17777
17778 if (sec->flags & SEC_ELF_PURECODE)
17779 hdr->sh_flags |= SHF_ARM_PURECODE;
17780
17781 return true;
17782 }
17783
17784 /* Handle an ARM specific section when reading an object file. This is
17785 called when bfd_section_from_shdr finds a section with an unknown
17786 type. */
17787
17788 static bool
17789 elf32_arm_section_from_shdr (bfd *abfd,
17790 Elf_Internal_Shdr * hdr,
17791 const char *name,
17792 int shindex)
17793 {
17794 /* There ought to be a place to keep ELF backend specific flags, but
17795 at the moment there isn't one. We just keep track of the
17796 sections by their name, instead. Fortunately, the ABI gives
17797 names for all the ARM specific sections, so we will probably get
17798 away with this. */
17799 switch (hdr->sh_type)
17800 {
17801 case SHT_ARM_EXIDX:
17802 case SHT_ARM_PREEMPTMAP:
17803 case SHT_ARM_ATTRIBUTES:
17804 break;
17805
17806 default:
17807 return false;
17808 }
17809
17810 if (! _bfd_elf_make_section_from_shdr (abfd, hdr, name, shindex))
17811 return false;
17812
17813 return true;
17814 }
17815
17816 static _arm_elf_section_data *
17817 get_arm_elf_section_data (asection * sec)
17818 {
17819 if (sec && sec->owner && is_arm_elf (sec->owner))
17820 return elf32_arm_section_data (sec);
17821 else
17822 return NULL;
17823 }
17824
17825 typedef struct
17826 {
17827 void *flaginfo;
17828 struct bfd_link_info *info;
17829 asection *sec;
17830 int sec_shndx;
17831 int (*func) (void *, const char *, Elf_Internal_Sym *,
17832 asection *, struct elf_link_hash_entry *);
17833 } output_arch_syminfo;
17834
17835 enum map_symbol_type
17836 {
17837 ARM_MAP_ARM,
17838 ARM_MAP_THUMB,
17839 ARM_MAP_DATA
17840 };
17841
17842
17843 /* Output a single mapping symbol. */
17844
17845 static bool
17846 elf32_arm_output_map_sym (output_arch_syminfo *osi,
17847 enum map_symbol_type type,
17848 bfd_vma offset)
17849 {
17850 static const char *names[3] = {"$a", "$t", "$d"};
17851 Elf_Internal_Sym sym;
17852
17853 sym.st_value = osi->sec->output_section->vma
17854 + osi->sec->output_offset
17855 + offset;
17856 sym.st_size = 0;
17857 sym.st_other = 0;
17858 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_NOTYPE);
17859 sym.st_shndx = osi->sec_shndx;
17860 sym.st_target_internal = 0;
17861 elf32_arm_section_map_add (osi->sec, names[type][1], offset);
17862 return osi->func (osi->flaginfo, names[type], &sym, osi->sec, NULL) == 1;
17863 }
17864
17865 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17866 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
17867
17868 static bool
17869 elf32_arm_output_plt_map_1 (output_arch_syminfo *osi,
17870 bool is_iplt_entry_p,
17871 union gotplt_union *root_plt,
17872 struct arm_plt_info *arm_plt)
17873 {
17874 struct elf32_arm_link_hash_table *htab;
17875 bfd_vma addr, plt_header_size;
17876
17877 if (root_plt->offset == (bfd_vma) -1)
17878 return true;
17879
17880 htab = elf32_arm_hash_table (osi->info);
17881 if (htab == NULL)
17882 return false;
17883
17884 if (is_iplt_entry_p)
17885 {
17886 osi->sec = htab->root.iplt;
17887 plt_header_size = 0;
17888 }
17889 else
17890 {
17891 osi->sec = htab->root.splt;
17892 plt_header_size = htab->plt_header_size;
17893 }
17894 osi->sec_shndx = (_bfd_elf_section_from_bfd_section
17895 (osi->info->output_bfd, osi->sec->output_section));
17896
17897 addr = root_plt->offset & -2;
17898 if (htab->root.target_os == is_vxworks)
17899 {
17900 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17901 return false;
17902 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 8))
17903 return false;
17904 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr + 12))
17905 return false;
17906 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 20))
17907 return false;
17908 }
17909 else if (htab->root.target_os == is_nacl)
17910 {
17911 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17912 return false;
17913 }
17914 else if (htab->fdpic_p)
17915 {
17916 enum map_symbol_type type = using_thumb_only (htab)
17917 ? ARM_MAP_THUMB
17918 : ARM_MAP_ARM;
17919
17920 if (elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt))
17921 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
17922 return false;
17923 if (!elf32_arm_output_map_sym (osi, type, addr))
17924 return false;
17925 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 16))
17926 return false;
17927 if (htab->plt_entry_size == 4 * ARRAY_SIZE (elf32_arm_fdpic_plt_entry))
17928 if (!elf32_arm_output_map_sym (osi, type, addr + 24))
17929 return false;
17930 }
17931 else if (using_thumb_only (htab))
17932 {
17933 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr))
17934 return false;
17935 }
17936 else
17937 {
17938 bool thumb_stub_p;
17939
17940 thumb_stub_p = elf32_arm_plt_needs_thumb_stub_p (osi->info, arm_plt);
17941 if (thumb_stub_p)
17942 {
17943 if (!elf32_arm_output_map_sym (osi, ARM_MAP_THUMB, addr - 4))
17944 return false;
17945 }
17946 #ifdef FOUR_WORD_PLT
17947 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17948 return false;
17949 if (!elf32_arm_output_map_sym (osi, ARM_MAP_DATA, addr + 12))
17950 return false;
17951 #else
17952 /* A three-word PLT with no Thumb thunk contains only Arm code,
17953 so only need to output a mapping symbol for the first PLT entry and
17954 entries with thumb thunks. */
17955 if (thumb_stub_p || addr == plt_header_size)
17956 {
17957 if (!elf32_arm_output_map_sym (osi, ARM_MAP_ARM, addr))
17958 return false;
17959 }
17960 #endif
17961 }
17962
17963 return true;
17964 }
17965
17966 /* Output mapping symbols for PLT entries associated with H. */
17967
17968 static bool
17969 elf32_arm_output_plt_map (struct elf_link_hash_entry *h, void *inf)
17970 {
17971 output_arch_syminfo *osi = (output_arch_syminfo *) inf;
17972 struct elf32_arm_link_hash_entry *eh;
17973
17974 if (h->root.type == bfd_link_hash_indirect)
17975 return true;
17976
17977 if (h->root.type == bfd_link_hash_warning)
17978 /* When warning symbols are created, they **replace** the "real"
17979 entry in the hash table, thus we never get to see the real
17980 symbol in a hash traversal. So look at it now. */
17981 h = (struct elf_link_hash_entry *) h->root.u.i.link;
17982
17983 eh = (struct elf32_arm_link_hash_entry *) h;
17984 return elf32_arm_output_plt_map_1 (osi, SYMBOL_CALLS_LOCAL (osi->info, h),
17985 &h->plt, &eh->plt);
17986 }
17987
17988 /* Bind a veneered symbol to its veneer identified by its hash entry
17989 STUB_ENTRY. The veneered location thus loose its symbol. */
17990
17991 static void
17992 arm_stub_claim_sym (struct elf32_arm_stub_hash_entry *stub_entry)
17993 {
17994 struct elf32_arm_link_hash_entry *hash = stub_entry->h;
17995
17996 BFD_ASSERT (hash);
17997 hash->root.root.u.def.section = stub_entry->stub_sec;
17998 hash->root.root.u.def.value = stub_entry->stub_offset;
17999 hash->root.size = stub_entry->stub_size;
18000 }
18001
18002 /* Output a single local symbol for a generated stub. */
18003
18004 static bool
18005 elf32_arm_output_stub_sym (output_arch_syminfo *osi, const char *name,
18006 bfd_vma offset, bfd_vma size)
18007 {
18008 Elf_Internal_Sym sym;
18009
18010 sym.st_value = osi->sec->output_section->vma
18011 + osi->sec->output_offset
18012 + offset;
18013 sym.st_size = size;
18014 sym.st_other = 0;
18015 sym.st_info = ELF_ST_INFO (STB_LOCAL, STT_FUNC);
18016 sym.st_shndx = osi->sec_shndx;
18017 sym.st_target_internal = 0;
18018 return osi->func (osi->flaginfo, name, &sym, osi->sec, NULL) == 1;
18019 }
18020
18021 static bool
18022 arm_map_one_stub (struct bfd_hash_entry * gen_entry,
18023 void * in_arg)
18024 {
18025 struct elf32_arm_stub_hash_entry *stub_entry;
18026 asection *stub_sec;
18027 bfd_vma addr;
18028 char *stub_name;
18029 output_arch_syminfo *osi;
18030 const insn_sequence *template_sequence;
18031 enum stub_insn_type prev_type;
18032 int size;
18033 int i;
18034 enum map_symbol_type sym_type;
18035
18036 /* Massage our args to the form they really have. */
18037 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18038 osi = (output_arch_syminfo *) in_arg;
18039
18040 stub_sec = stub_entry->stub_sec;
18041
18042 /* Ensure this stub is attached to the current section being
18043 processed. */
18044 if (stub_sec != osi->sec)
18045 return true;
18046
18047 addr = (bfd_vma) stub_entry->stub_offset;
18048 template_sequence = stub_entry->stub_template;
18049
18050 if (arm_stub_sym_claimed (stub_entry->stub_type))
18051 arm_stub_claim_sym (stub_entry);
18052 else
18053 {
18054 stub_name = stub_entry->output_name;
18055 switch (template_sequence[0].type)
18056 {
18057 case ARM_TYPE:
18058 if (!elf32_arm_output_stub_sym (osi, stub_name, addr,
18059 stub_entry->stub_size))
18060 return false;
18061 break;
18062 case THUMB16_TYPE:
18063 case THUMB32_TYPE:
18064 if (!elf32_arm_output_stub_sym (osi, stub_name, addr | 1,
18065 stub_entry->stub_size))
18066 return false;
18067 break;
18068 default:
18069 BFD_FAIL ();
18070 return 0;
18071 }
18072 }
18073
18074 prev_type = DATA_TYPE;
18075 size = 0;
18076 for (i = 0; i < stub_entry->stub_template_size; i++)
18077 {
18078 switch (template_sequence[i].type)
18079 {
18080 case ARM_TYPE:
18081 sym_type = ARM_MAP_ARM;
18082 break;
18083
18084 case THUMB16_TYPE:
18085 case THUMB32_TYPE:
18086 sym_type = ARM_MAP_THUMB;
18087 break;
18088
18089 case DATA_TYPE:
18090 sym_type = ARM_MAP_DATA;
18091 break;
18092
18093 default:
18094 BFD_FAIL ();
18095 return false;
18096 }
18097
18098 if (template_sequence[i].type != prev_type)
18099 {
18100 prev_type = template_sequence[i].type;
18101 if (!elf32_arm_output_map_sym (osi, sym_type, addr + size))
18102 return false;
18103 }
18104
18105 switch (template_sequence[i].type)
18106 {
18107 case ARM_TYPE:
18108 case THUMB32_TYPE:
18109 size += 4;
18110 break;
18111
18112 case THUMB16_TYPE:
18113 size += 2;
18114 break;
18115
18116 case DATA_TYPE:
18117 size += 4;
18118 break;
18119
18120 default:
18121 BFD_FAIL ();
18122 return false;
18123 }
18124 }
18125
18126 return true;
18127 }
18128
18129 /* Output mapping symbols for linker generated sections,
18130 and for those data-only sections that do not have a
18131 $d. */
18132
18133 static bool
18134 elf32_arm_output_arch_local_syms (bfd *output_bfd,
18135 struct bfd_link_info *info,
18136 void *flaginfo,
18137 int (*func) (void *, const char *,
18138 Elf_Internal_Sym *,
18139 asection *,
18140 struct elf_link_hash_entry *))
18141 {
18142 output_arch_syminfo osi;
18143 struct elf32_arm_link_hash_table *htab;
18144 bfd_vma offset;
18145 bfd_size_type size;
18146 bfd *input_bfd;
18147
18148 if (info->strip == strip_all
18149 && !info->emitrelocations
18150 && !bfd_link_relocatable (info))
18151 return true;
18152
18153 htab = elf32_arm_hash_table (info);
18154 if (htab == NULL)
18155 return false;
18156
18157 check_use_blx (htab);
18158
18159 osi.flaginfo = flaginfo;
18160 osi.info = info;
18161 osi.func = func;
18162
18163 /* Add a $d mapping symbol to data-only sections that
18164 don't have any mapping symbol. This may result in (harmless) redundant
18165 mapping symbols. */
18166 for (input_bfd = info->input_bfds;
18167 input_bfd != NULL;
18168 input_bfd = input_bfd->link.next)
18169 {
18170 if ((input_bfd->flags & (BFD_LINKER_CREATED | HAS_SYMS)) == HAS_SYMS)
18171 for (osi.sec = input_bfd->sections;
18172 osi.sec != NULL;
18173 osi.sec = osi.sec->next)
18174 {
18175 if (osi.sec->output_section != NULL
18176 && ((osi.sec->output_section->flags & (SEC_ALLOC | SEC_CODE))
18177 != 0)
18178 && (osi.sec->flags & (SEC_HAS_CONTENTS | SEC_LINKER_CREATED))
18179 == SEC_HAS_CONTENTS
18180 && get_arm_elf_section_data (osi.sec) != NULL
18181 && get_arm_elf_section_data (osi.sec)->mapcount == 0
18182 && osi.sec->size > 0
18183 && (osi.sec->flags & SEC_EXCLUDE) == 0)
18184 {
18185 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18186 (output_bfd, osi.sec->output_section);
18187 if (osi.sec_shndx != (int)SHN_BAD)
18188 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 0);
18189 }
18190 }
18191 }
18192
18193 /* ARM->Thumb glue. */
18194 if (htab->arm_glue_size > 0)
18195 {
18196 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18197 ARM2THUMB_GLUE_SECTION_NAME);
18198
18199 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18200 (output_bfd, osi.sec->output_section);
18201 if (bfd_link_pic (info) || htab->root.is_relocatable_executable
18202 || htab->pic_veneer)
18203 size = ARM2THUMB_PIC_GLUE_SIZE;
18204 else if (htab->use_blx)
18205 size = ARM2THUMB_V5_STATIC_GLUE_SIZE;
18206 else
18207 size = ARM2THUMB_STATIC_GLUE_SIZE;
18208
18209 for (offset = 0; offset < htab->arm_glue_size; offset += size)
18210 {
18211 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset);
18212 elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, offset + size - 4);
18213 }
18214 }
18215
18216 /* Thumb->ARM glue. */
18217 if (htab->thumb_glue_size > 0)
18218 {
18219 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18220 THUMB2ARM_GLUE_SECTION_NAME);
18221
18222 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18223 (output_bfd, osi.sec->output_section);
18224 size = THUMB2ARM_GLUE_SIZE;
18225
18226 for (offset = 0; offset < htab->thumb_glue_size; offset += size)
18227 {
18228 elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, offset);
18229 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, offset + 4);
18230 }
18231 }
18232
18233 /* ARMv4 BX veneers. */
18234 if (htab->bx_glue_size > 0)
18235 {
18236 osi.sec = bfd_get_linker_section (htab->bfd_of_glue_owner,
18237 ARM_BX_GLUE_SECTION_NAME);
18238
18239 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18240 (output_bfd, osi.sec->output_section);
18241
18242 elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0);
18243 }
18244
18245 /* Long calls stubs. */
18246 if (htab->stub_bfd && htab->stub_bfd->sections)
18247 {
18248 asection* stub_sec;
18249
18250 for (stub_sec = htab->stub_bfd->sections;
18251 stub_sec != NULL;
18252 stub_sec = stub_sec->next)
18253 {
18254 /* Ignore non-stub sections. */
18255 if (!strstr (stub_sec->name, STUB_SUFFIX))
18256 continue;
18257
18258 osi.sec = stub_sec;
18259
18260 osi.sec_shndx = _bfd_elf_section_from_bfd_section
18261 (output_bfd, osi.sec->output_section);
18262
18263 bfd_hash_traverse (&htab->stub_hash_table, arm_map_one_stub, &osi);
18264 }
18265 }
18266
18267 /* Finally, output mapping symbols for the PLT. */
18268 if (htab->root.splt && htab->root.splt->size > 0)
18269 {
18270 osi.sec = htab->root.splt;
18271 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18272 (output_bfd, osi.sec->output_section));
18273
18274 /* Output mapping symbols for the plt header. */
18275 if (htab->root.target_os == is_vxworks)
18276 {
18277 /* VxWorks shared libraries have no PLT header. */
18278 if (!bfd_link_pic (info))
18279 {
18280 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18281 return false;
18282 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18283 return false;
18284 }
18285 }
18286 else if (htab->root.target_os == is_nacl)
18287 {
18288 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18289 return false;
18290 }
18291 else if (using_thumb_only (htab) && !htab->fdpic_p)
18292 {
18293 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 0))
18294 return false;
18295 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 12))
18296 return false;
18297 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_THUMB, 16))
18298 return false;
18299 }
18300 else if (!htab->fdpic_p)
18301 {
18302 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18303 return false;
18304 #ifndef FOUR_WORD_PLT
18305 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA, 16))
18306 return false;
18307 #endif
18308 }
18309 }
18310 if (htab->root.target_os == is_nacl
18311 && htab->root.iplt
18312 && htab->root.iplt->size > 0)
18313 {
18314 /* NaCl uses a special first entry in .iplt too. */
18315 osi.sec = htab->root.iplt;
18316 osi.sec_shndx = (_bfd_elf_section_from_bfd_section
18317 (output_bfd, osi.sec->output_section));
18318 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, 0))
18319 return false;
18320 }
18321 if ((htab->root.splt && htab->root.splt->size > 0)
18322 || (htab->root.iplt && htab->root.iplt->size > 0))
18323 {
18324 elf_link_hash_traverse (&htab->root, elf32_arm_output_plt_map, &osi);
18325 for (input_bfd = info->input_bfds;
18326 input_bfd != NULL;
18327 input_bfd = input_bfd->link.next)
18328 {
18329 struct arm_local_iplt_info **local_iplt;
18330 unsigned int i, num_syms;
18331
18332 local_iplt = elf32_arm_local_iplt (input_bfd);
18333 if (local_iplt != NULL)
18334 {
18335 num_syms = elf_symtab_hdr (input_bfd).sh_info;
18336 if (num_syms > elf32_arm_num_entries (input_bfd))
18337 {
18338 _bfd_error_handler (_("\
18339 %pB: Number of symbols in input file has increased from %lu to %u\n"),
18340 input_bfd,
18341 (unsigned long) elf32_arm_num_entries (input_bfd),
18342 num_syms);
18343 return false;
18344 }
18345 for (i = 0; i < num_syms; i++)
18346 if (local_iplt[i] != NULL
18347 && !elf32_arm_output_plt_map_1 (&osi, true,
18348 &local_iplt[i]->root,
18349 &local_iplt[i]->arm))
18350 return false;
18351 }
18352 }
18353 }
18354 if (htab->root.tlsdesc_plt != 0)
18355 {
18356 /* Mapping symbols for the lazy tls trampoline. */
18357 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM,
18358 htab->root.tlsdesc_plt))
18359 return false;
18360
18361 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18362 htab->root.tlsdesc_plt + 24))
18363 return false;
18364 }
18365 if (htab->tls_trampoline != 0)
18366 {
18367 /* Mapping symbols for the tls trampoline. */
18368 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_ARM, htab->tls_trampoline))
18369 return false;
18370 #ifdef FOUR_WORD_PLT
18371 if (!elf32_arm_output_map_sym (&osi, ARM_MAP_DATA,
18372 htab->tls_trampoline + 12))
18373 return false;
18374 #endif
18375 }
18376
18377 return true;
18378 }
18379
18380 /* Filter normal symbols of CMSE entry functions of ABFD to include in
18381 the import library. All SYMCOUNT symbols of ABFD can be examined
18382 from their pointers in SYMS. Pointers of symbols to keep should be
18383 stored continuously at the beginning of that array.
18384
18385 Returns the number of symbols to keep. */
18386
18387 static unsigned int
18388 elf32_arm_filter_cmse_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18389 struct bfd_link_info *info,
18390 asymbol **syms, long symcount)
18391 {
18392 size_t maxnamelen;
18393 char *cmse_name;
18394 long src_count, dst_count = 0;
18395 struct elf32_arm_link_hash_table *htab;
18396
18397 htab = elf32_arm_hash_table (info);
18398 if (!htab->stub_bfd || !htab->stub_bfd->sections)
18399 symcount = 0;
18400
18401 maxnamelen = 128;
18402 cmse_name = (char *) bfd_malloc (maxnamelen);
18403 BFD_ASSERT (cmse_name);
18404
18405 for (src_count = 0; src_count < symcount; src_count++)
18406 {
18407 struct elf32_arm_link_hash_entry *cmse_hash;
18408 asymbol *sym;
18409 flagword flags;
18410 char *name;
18411 size_t namelen;
18412
18413 sym = syms[src_count];
18414 flags = sym->flags;
18415 name = (char *) bfd_asymbol_name (sym);
18416
18417 if ((flags & BSF_FUNCTION) != BSF_FUNCTION)
18418 continue;
18419 if (!(flags & (BSF_GLOBAL | BSF_WEAK)))
18420 continue;
18421
18422 namelen = strlen (name) + sizeof (CMSE_PREFIX) + 1;
18423 if (namelen > maxnamelen)
18424 {
18425 cmse_name = (char *)
18426 bfd_realloc (cmse_name, namelen);
18427 maxnamelen = namelen;
18428 }
18429 snprintf (cmse_name, maxnamelen, "%s%s", CMSE_PREFIX, name);
18430 cmse_hash = (struct elf32_arm_link_hash_entry *)
18431 elf_link_hash_lookup (&(htab)->root, cmse_name, false, false, true);
18432
18433 if (!cmse_hash
18434 || (cmse_hash->root.root.type != bfd_link_hash_defined
18435 && cmse_hash->root.root.type != bfd_link_hash_defweak)
18436 || cmse_hash->root.type != STT_FUNC)
18437 continue;
18438
18439 syms[dst_count++] = sym;
18440 }
18441 free (cmse_name);
18442
18443 syms[dst_count] = NULL;
18444
18445 return dst_count;
18446 }
18447
18448 /* Filter symbols of ABFD to include in the import library. All
18449 SYMCOUNT symbols of ABFD can be examined from their pointers in
18450 SYMS. Pointers of symbols to keep should be stored continuously at
18451 the beginning of that array.
18452
18453 Returns the number of symbols to keep. */
18454
18455 static unsigned int
18456 elf32_arm_filter_implib_symbols (bfd *abfd ATTRIBUTE_UNUSED,
18457 struct bfd_link_info *info,
18458 asymbol **syms, long symcount)
18459 {
18460 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (info);
18461
18462 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18463 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18464 library to be a relocatable object file. */
18465 BFD_ASSERT (!(bfd_get_file_flags (info->out_implib_bfd) & EXEC_P));
18466 if (globals->cmse_implib)
18467 return elf32_arm_filter_cmse_symbols (abfd, info, syms, symcount);
18468 else
18469 return _bfd_elf_filter_global_symbols (abfd, info, syms, symcount);
18470 }
18471
18472 /* Allocate target specific section data. */
18473
18474 static bool
18475 elf32_arm_new_section_hook (bfd *abfd, asection *sec)
18476 {
18477 if (!sec->used_by_bfd)
18478 {
18479 _arm_elf_section_data *sdata;
18480 size_t amt = sizeof (*sdata);
18481
18482 sdata = (_arm_elf_section_data *) bfd_zalloc (abfd, amt);
18483 if (sdata == NULL)
18484 return false;
18485 sec->used_by_bfd = sdata;
18486 }
18487
18488 return _bfd_elf_new_section_hook (abfd, sec);
18489 }
18490
18491
18492 /* Used to order a list of mapping symbols by address. */
18493
18494 static int
18495 elf32_arm_compare_mapping (const void * a, const void * b)
18496 {
18497 const elf32_arm_section_map *amap = (const elf32_arm_section_map *) a;
18498 const elf32_arm_section_map *bmap = (const elf32_arm_section_map *) b;
18499
18500 if (amap->vma > bmap->vma)
18501 return 1;
18502 else if (amap->vma < bmap->vma)
18503 return -1;
18504 else if (amap->type > bmap->type)
18505 /* Ensure results do not depend on the host qsort for objects with
18506 multiple mapping symbols at the same address by sorting on type
18507 after vma. */
18508 return 1;
18509 else if (amap->type < bmap->type)
18510 return -1;
18511 else
18512 return 0;
18513 }
18514
18515 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18516
18517 static unsigned long
18518 offset_prel31 (unsigned long addr, bfd_vma offset)
18519 {
18520 return (addr & ~0x7ffffffful) | ((addr + offset) & 0x7ffffffful);
18521 }
18522
18523 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18524 relocations. */
18525
18526 static void
18527 copy_exidx_entry (bfd *output_bfd, bfd_byte *to, bfd_byte *from, bfd_vma offset)
18528 {
18529 unsigned long first_word = bfd_get_32 (output_bfd, from);
18530 unsigned long second_word = bfd_get_32 (output_bfd, from + 4);
18531
18532 /* High bit of first word is supposed to be zero. */
18533 if ((first_word & 0x80000000ul) == 0)
18534 first_word = offset_prel31 (first_word, offset);
18535
18536 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18537 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18538 if ((second_word != 0x1) && ((second_word & 0x80000000ul) == 0))
18539 second_word = offset_prel31 (second_word, offset);
18540
18541 bfd_put_32 (output_bfd, first_word, to);
18542 bfd_put_32 (output_bfd, second_word, to + 4);
18543 }
18544
18545 /* Data for make_branch_to_a8_stub(). */
18546
18547 struct a8_branch_to_stub_data
18548 {
18549 asection *writing_section;
18550 bfd_byte *contents;
18551 };
18552
18553
18554 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
18555 places for a particular section. */
18556
18557 static bool
18558 make_branch_to_a8_stub (struct bfd_hash_entry *gen_entry,
18559 void *in_arg)
18560 {
18561 struct elf32_arm_stub_hash_entry *stub_entry;
18562 struct a8_branch_to_stub_data *data;
18563 bfd_byte *contents;
18564 unsigned long branch_insn;
18565 bfd_vma veneered_insn_loc, veneer_entry_loc;
18566 bfd_signed_vma branch_offset;
18567 bfd *abfd;
18568 unsigned int loc;
18569
18570 stub_entry = (struct elf32_arm_stub_hash_entry *) gen_entry;
18571 data = (struct a8_branch_to_stub_data *) in_arg;
18572
18573 if (stub_entry->target_section != data->writing_section
18574 || stub_entry->stub_type < arm_stub_a8_veneer_lwm)
18575 return true;
18576
18577 contents = data->contents;
18578
18579 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18580 generated when both source and target are in the same section. */
18581 veneered_insn_loc = stub_entry->target_section->output_section->vma
18582 + stub_entry->target_section->output_offset
18583 + stub_entry->source_value;
18584
18585 veneer_entry_loc = stub_entry->stub_sec->output_section->vma
18586 + stub_entry->stub_sec->output_offset
18587 + stub_entry->stub_offset;
18588
18589 if (stub_entry->stub_type == arm_stub_a8_veneer_blx)
18590 veneered_insn_loc &= ~3u;
18591
18592 branch_offset = veneer_entry_loc - veneered_insn_loc - 4;
18593
18594 abfd = stub_entry->target_section->owner;
18595 loc = stub_entry->source_value;
18596
18597 /* We attempt to avoid this condition by setting stubs_always_after_branch
18598 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18599 This check is just to be on the safe side... */
18600 if ((veneered_insn_loc & ~0xfff) == (veneer_entry_loc & ~0xfff))
18601 {
18602 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub is "
18603 "allocated in unsafe location"), abfd);
18604 return false;
18605 }
18606
18607 switch (stub_entry->stub_type)
18608 {
18609 case arm_stub_a8_veneer_b:
18610 case arm_stub_a8_veneer_b_cond:
18611 branch_insn = 0xf0009000;
18612 goto jump24;
18613
18614 case arm_stub_a8_veneer_blx:
18615 branch_insn = 0xf000e800;
18616 goto jump24;
18617
18618 case arm_stub_a8_veneer_bl:
18619 {
18620 unsigned int i1, j1, i2, j2, s;
18621
18622 branch_insn = 0xf000d000;
18623
18624 jump24:
18625 if (branch_offset < -16777216 || branch_offset > 16777214)
18626 {
18627 /* There's not much we can do apart from complain if this
18628 happens. */
18629 _bfd_error_handler (_("%pB: error: Cortex-A8 erratum stub out "
18630 "of range (input file too large)"), abfd);
18631 return false;
18632 }
18633
18634 /* i1 = not(j1 eor s), so:
18635 not i1 = j1 eor s
18636 j1 = (not i1) eor s. */
18637
18638 branch_insn |= (branch_offset >> 1) & 0x7ff;
18639 branch_insn |= ((branch_offset >> 12) & 0x3ff) << 16;
18640 i2 = (branch_offset >> 22) & 1;
18641 i1 = (branch_offset >> 23) & 1;
18642 s = (branch_offset >> 24) & 1;
18643 j1 = (!i1) ^ s;
18644 j2 = (!i2) ^ s;
18645 branch_insn |= j2 << 11;
18646 branch_insn |= j1 << 13;
18647 branch_insn |= s << 26;
18648 }
18649 break;
18650
18651 default:
18652 BFD_FAIL ();
18653 return false;
18654 }
18655
18656 bfd_put_16 (abfd, (branch_insn >> 16) & 0xffff, &contents[loc]);
18657 bfd_put_16 (abfd, branch_insn & 0xffff, &contents[loc + 2]);
18658
18659 return true;
18660 }
18661
18662 /* Beginning of stm32l4xx work-around. */
18663
18664 /* Functions encoding instructions necessary for the emission of the
18665 fix-stm32l4xx-629360.
18666 Encoding is extracted from the
18667 ARM (C) Architecture Reference Manual
18668 ARMv7-A and ARMv7-R edition
18669 ARM DDI 0406C.b (ID072512). */
18670
18671 static inline bfd_vma
18672 create_instruction_branch_absolute (int branch_offset)
18673 {
18674 /* A8.8.18 B (A8-334)
18675 B target_address (Encoding T4). */
18676 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18677 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18678 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18679
18680 int s = ((branch_offset & 0x1000000) >> 24);
18681 int j1 = s ^ !((branch_offset & 0x800000) >> 23);
18682 int j2 = s ^ !((branch_offset & 0x400000) >> 22);
18683
18684 if (branch_offset < -(1 << 24) || branch_offset >= (1 << 24))
18685 BFD_ASSERT (0 && "Error: branch out of range. Cannot create branch.");
18686
18687 bfd_vma patched_inst = 0xf0009000
18688 | s << 26 /* S. */
18689 | (((unsigned long) (branch_offset) >> 12) & 0x3ff) << 16 /* imm10. */
18690 | j1 << 13 /* J1. */
18691 | j2 << 11 /* J2. */
18692 | (((unsigned long) (branch_offset) >> 1) & 0x7ff); /* imm11. */
18693
18694 return patched_inst;
18695 }
18696
18697 static inline bfd_vma
18698 create_instruction_ldmia (int base_reg, int wback, int reg_mask)
18699 {
18700 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18701 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18702 bfd_vma patched_inst = 0xe8900000
18703 | (/*W=*/wback << 21)
18704 | (base_reg << 16)
18705 | (reg_mask & 0x0000ffff);
18706
18707 return patched_inst;
18708 }
18709
18710 static inline bfd_vma
18711 create_instruction_ldmdb (int base_reg, int wback, int reg_mask)
18712 {
18713 /* A8.8.60 LDMDB/LDMEA (A8-402)
18714 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18715 bfd_vma patched_inst = 0xe9100000
18716 | (/*W=*/wback << 21)
18717 | (base_reg << 16)
18718 | (reg_mask & 0x0000ffff);
18719
18720 return patched_inst;
18721 }
18722
18723 static inline bfd_vma
18724 create_instruction_mov (int target_reg, int source_reg)
18725 {
18726 /* A8.8.103 MOV (register) (A8-486)
18727 MOV Rd, Rm (Encoding T1). */
18728 bfd_vma patched_inst = 0x4600
18729 | (target_reg & 0x7)
18730 | ((target_reg & 0x8) >> 3) << 7
18731 | (source_reg << 3);
18732
18733 return patched_inst;
18734 }
18735
18736 static inline bfd_vma
18737 create_instruction_sub (int target_reg, int source_reg, int value)
18738 {
18739 /* A8.8.221 SUB (immediate) (A8-708)
18740 SUB Rd, Rn, #value (Encoding T3). */
18741 bfd_vma patched_inst = 0xf1a00000
18742 | (target_reg << 8)
18743 | (source_reg << 16)
18744 | (/*S=*/0 << 20)
18745 | ((value & 0x800) >> 11) << 26
18746 | ((value & 0x700) >> 8) << 12
18747 | (value & 0x0ff);
18748
18749 return patched_inst;
18750 }
18751
18752 static inline bfd_vma
18753 create_instruction_vldmia (int base_reg, int is_dp, int wback, int num_words,
18754 int first_reg)
18755 {
18756 /* A8.8.332 VLDM (A8-922)
18757 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18758 bfd_vma patched_inst = (is_dp ? 0xec900b00 : 0xec900a00)
18759 | (/*W=*/wback << 21)
18760 | (base_reg << 16)
18761 | (num_words & 0x000000ff)
18762 | (((unsigned)first_reg >> 1) & 0x0000000f) << 12
18763 | (first_reg & 0x00000001) << 22;
18764
18765 return patched_inst;
18766 }
18767
18768 static inline bfd_vma
18769 create_instruction_vldmdb (int base_reg, int is_dp, int num_words,
18770 int first_reg)
18771 {
18772 /* A8.8.332 VLDM (A8-922)
18773 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18774 bfd_vma patched_inst = (is_dp ? 0xed300b00 : 0xed300a00)
18775 | (base_reg << 16)
18776 | (num_words & 0x000000ff)
18777 | (((unsigned)first_reg >>1 ) & 0x0000000f) << 12
18778 | (first_reg & 0x00000001) << 22;
18779
18780 return patched_inst;
18781 }
18782
18783 static inline bfd_vma
18784 create_instruction_udf_w (int value)
18785 {
18786 /* A8.8.247 UDF (A8-758)
18787 Undefined (Encoding T2). */
18788 bfd_vma patched_inst = 0xf7f0a000
18789 | (value & 0x00000fff)
18790 | (value & 0x000f0000) << 16;
18791
18792 return patched_inst;
18793 }
18794
18795 static inline bfd_vma
18796 create_instruction_udf (int value)
18797 {
18798 /* A8.8.247 UDF (A8-758)
18799 Undefined (Encoding T1). */
18800 bfd_vma patched_inst = 0xde00
18801 | (value & 0xff);
18802
18803 return patched_inst;
18804 }
18805
18806 /* Functions writing an instruction in memory, returning the next
18807 memory position to write to. */
18808
18809 static inline bfd_byte *
18810 push_thumb2_insn32 (struct elf32_arm_link_hash_table * htab,
18811 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18812 {
18813 put_thumb2_insn (htab, output_bfd, insn, pt);
18814 return pt + 4;
18815 }
18816
18817 static inline bfd_byte *
18818 push_thumb2_insn16 (struct elf32_arm_link_hash_table * htab,
18819 bfd * output_bfd, bfd_byte *pt, insn32 insn)
18820 {
18821 put_thumb_insn (htab, output_bfd, insn, pt);
18822 return pt + 2;
18823 }
18824
18825 /* Function filling up a region in memory with T1 and T2 UDFs taking
18826 care of alignment. */
18827
18828 static bfd_byte *
18829 stm32l4xx_fill_stub_udf (struct elf32_arm_link_hash_table * htab,
18830 bfd * output_bfd,
18831 const bfd_byte * const base_stub_contents,
18832 bfd_byte * const from_stub_contents,
18833 const bfd_byte * const end_stub_contents)
18834 {
18835 bfd_byte *current_stub_contents = from_stub_contents;
18836
18837 /* Fill the remaining of the stub with deterministic contents : UDF
18838 instructions.
18839 Check if realignment is needed on modulo 4 frontier using T1, to
18840 further use T2. */
18841 if ((current_stub_contents < end_stub_contents)
18842 && !((current_stub_contents - base_stub_contents) % 2)
18843 && ((current_stub_contents - base_stub_contents) % 4))
18844 current_stub_contents =
18845 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18846 create_instruction_udf (0));
18847
18848 for (; current_stub_contents < end_stub_contents;)
18849 current_stub_contents =
18850 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18851 create_instruction_udf_w (0));
18852
18853 return current_stub_contents;
18854 }
18855
18856 /* Functions writing the stream of instructions equivalent to the
18857 derived sequence for ldmia, ldmdb, vldm respectively. */
18858
18859 static void
18860 stm32l4xx_create_replacing_stub_ldmia (struct elf32_arm_link_hash_table * htab,
18861 bfd * output_bfd,
18862 const insn32 initial_insn,
18863 const bfd_byte *const initial_insn_addr,
18864 bfd_byte *const base_stub_contents)
18865 {
18866 int wback = (initial_insn & 0x00200000) >> 21;
18867 int ri, rn = (initial_insn & 0x000F0000) >> 16;
18868 int insn_all_registers = initial_insn & 0x0000ffff;
18869 int insn_low_registers, insn_high_registers;
18870 int usable_register_mask;
18871 int nb_registers = elf32_arm_popcount (insn_all_registers);
18872 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
18873 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
18874 bfd_byte *current_stub_contents = base_stub_contents;
18875
18876 BFD_ASSERT (is_thumb2_ldmia (initial_insn));
18877
18878 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18879 smaller than 8 registers load sequences that do not cause the
18880 hardware issue. */
18881 if (nb_registers <= 8)
18882 {
18883 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18884 current_stub_contents =
18885 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18886 initial_insn);
18887
18888 /* B initial_insn_addr+4. */
18889 if (!restore_pc)
18890 current_stub_contents =
18891 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18892 create_instruction_branch_absolute
18893 (initial_insn_addr - current_stub_contents));
18894
18895 /* Fill the remaining of the stub with deterministic contents. */
18896 current_stub_contents =
18897 stm32l4xx_fill_stub_udf (htab, output_bfd,
18898 base_stub_contents, current_stub_contents,
18899 base_stub_contents +
18900 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18901
18902 return;
18903 }
18904
18905 /* - reg_list[13] == 0. */
18906 BFD_ASSERT ((insn_all_registers & (1 << 13))==0);
18907
18908 /* - reg_list[14] & reg_list[15] != 1. */
18909 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
18910
18911 /* - if (wback==1) reg_list[rn] == 0. */
18912 BFD_ASSERT (!wback || !restore_rn);
18913
18914 /* - nb_registers > 8. */
18915 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
18916
18917 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18918
18919 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18920 - One with the 7 lowest registers (register mask 0x007F)
18921 This LDM will finally contain between 2 and 7 registers
18922 - One with the 7 highest registers (register mask 0xDF80)
18923 This ldm will finally contain between 2 and 7 registers. */
18924 insn_low_registers = insn_all_registers & 0x007F;
18925 insn_high_registers = insn_all_registers & 0xDF80;
18926
18927 /* A spare register may be needed during this veneer to temporarily
18928 handle the base register. This register will be restored with the
18929 last LDM operation.
18930 The usable register may be any general purpose register (that
18931 excludes PC, SP, LR : register mask is 0x1FFF). */
18932 usable_register_mask = 0x1FFF;
18933
18934 /* Generate the stub function. */
18935 if (wback)
18936 {
18937 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18938 current_stub_contents =
18939 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18940 create_instruction_ldmia
18941 (rn, /*wback=*/1, insn_low_registers));
18942
18943 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18944 current_stub_contents =
18945 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18946 create_instruction_ldmia
18947 (rn, /*wback=*/1, insn_high_registers));
18948 if (!restore_pc)
18949 {
18950 /* B initial_insn_addr+4. */
18951 current_stub_contents =
18952 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18953 create_instruction_branch_absolute
18954 (initial_insn_addr - current_stub_contents));
18955 }
18956 }
18957 else /* if (!wback). */
18958 {
18959 ri = rn;
18960
18961 /* If Rn is not part of the high-register-list, move it there. */
18962 if (!(insn_high_registers & (1 << rn)))
18963 {
18964 /* Choose a Ri in the high-register-list that will be restored. */
18965 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
18966
18967 /* MOV Ri, Rn. */
18968 current_stub_contents =
18969 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
18970 create_instruction_mov (ri, rn));
18971 }
18972
18973 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18974 current_stub_contents =
18975 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18976 create_instruction_ldmia
18977 (ri, /*wback=*/1, insn_low_registers));
18978
18979 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18980 current_stub_contents =
18981 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18982 create_instruction_ldmia
18983 (ri, /*wback=*/0, insn_high_registers));
18984
18985 if (!restore_pc)
18986 {
18987 /* B initial_insn_addr+4. */
18988 current_stub_contents =
18989 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
18990 create_instruction_branch_absolute
18991 (initial_insn_addr - current_stub_contents));
18992 }
18993 }
18994
18995 /* Fill the remaining of the stub with deterministic contents. */
18996 current_stub_contents =
18997 stm32l4xx_fill_stub_udf (htab, output_bfd,
18998 base_stub_contents, current_stub_contents,
18999 base_stub_contents +
19000 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19001 }
19002
19003 static void
19004 stm32l4xx_create_replacing_stub_ldmdb (struct elf32_arm_link_hash_table * htab,
19005 bfd * output_bfd,
19006 const insn32 initial_insn,
19007 const bfd_byte *const initial_insn_addr,
19008 bfd_byte *const base_stub_contents)
19009 {
19010 int wback = (initial_insn & 0x00200000) >> 21;
19011 int ri, rn = (initial_insn & 0x000f0000) >> 16;
19012 int insn_all_registers = initial_insn & 0x0000ffff;
19013 int insn_low_registers, insn_high_registers;
19014 int usable_register_mask;
19015 int restore_pc = (insn_all_registers & (1 << 15)) ? 1 : 0;
19016 int restore_rn = (insn_all_registers & (1 << rn)) ? 1 : 0;
19017 int nb_registers = elf32_arm_popcount (insn_all_registers);
19018 bfd_byte *current_stub_contents = base_stub_contents;
19019
19020 BFD_ASSERT (is_thumb2_ldmdb (initial_insn));
19021
19022 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19023 smaller than 8 registers load sequences that do not cause the
19024 hardware issue. */
19025 if (nb_registers <= 8)
19026 {
19027 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19028 current_stub_contents =
19029 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19030 initial_insn);
19031
19032 /* B initial_insn_addr+4. */
19033 current_stub_contents =
19034 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19035 create_instruction_branch_absolute
19036 (initial_insn_addr - current_stub_contents));
19037
19038 /* Fill the remaining of the stub with deterministic contents. */
19039 current_stub_contents =
19040 stm32l4xx_fill_stub_udf (htab, output_bfd,
19041 base_stub_contents, current_stub_contents,
19042 base_stub_contents +
19043 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19044
19045 return;
19046 }
19047
19048 /* - reg_list[13] == 0. */
19049 BFD_ASSERT ((insn_all_registers & (1 << 13)) == 0);
19050
19051 /* - reg_list[14] & reg_list[15] != 1. */
19052 BFD_ASSERT ((insn_all_registers & 0xC000) != 0xC000);
19053
19054 /* - if (wback==1) reg_list[rn] == 0. */
19055 BFD_ASSERT (!wback || !restore_rn);
19056
19057 /* - nb_registers > 8. */
19058 BFD_ASSERT (elf32_arm_popcount (insn_all_registers) > 8);
19059
19060 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19061
19062 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19063 - One with the 7 lowest registers (register mask 0x007F)
19064 This LDM will finally contain between 2 and 7 registers
19065 - One with the 7 highest registers (register mask 0xDF80)
19066 This ldm will finally contain between 2 and 7 registers. */
19067 insn_low_registers = insn_all_registers & 0x007F;
19068 insn_high_registers = insn_all_registers & 0xDF80;
19069
19070 /* A spare register may be needed during this veneer to temporarily
19071 handle the base register. This register will be restored with
19072 the last LDM operation.
19073 The usable register may be any general purpose register (that excludes
19074 PC, SP, LR : register mask is 0x1FFF). */
19075 usable_register_mask = 0x1FFF;
19076
19077 /* Generate the stub function. */
19078 if (!wback && !restore_pc && !restore_rn)
19079 {
19080 /* Choose a Ri in the low-register-list that will be restored. */
19081 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19082
19083 /* MOV Ri, Rn. */
19084 current_stub_contents =
19085 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19086 create_instruction_mov (ri, rn));
19087
19088 /* LDMDB Ri!, {R-high-register-list}. */
19089 current_stub_contents =
19090 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19091 create_instruction_ldmdb
19092 (ri, /*wback=*/1, insn_high_registers));
19093
19094 /* LDMDB Ri, {R-low-register-list}. */
19095 current_stub_contents =
19096 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19097 create_instruction_ldmdb
19098 (ri, /*wback=*/0, insn_low_registers));
19099
19100 /* B initial_insn_addr+4. */
19101 current_stub_contents =
19102 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19103 create_instruction_branch_absolute
19104 (initial_insn_addr - current_stub_contents));
19105 }
19106 else if (wback && !restore_pc && !restore_rn)
19107 {
19108 /* LDMDB Rn!, {R-high-register-list}. */
19109 current_stub_contents =
19110 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19111 create_instruction_ldmdb
19112 (rn, /*wback=*/1, insn_high_registers));
19113
19114 /* LDMDB Rn!, {R-low-register-list}. */
19115 current_stub_contents =
19116 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19117 create_instruction_ldmdb
19118 (rn, /*wback=*/1, insn_low_registers));
19119
19120 /* B initial_insn_addr+4. */
19121 current_stub_contents =
19122 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19123 create_instruction_branch_absolute
19124 (initial_insn_addr - current_stub_contents));
19125 }
19126 else if (!wback && restore_pc && !restore_rn)
19127 {
19128 /* Choose a Ri in the high-register-list that will be restored. */
19129 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19130
19131 /* SUB Ri, Rn, #(4*nb_registers). */
19132 current_stub_contents =
19133 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19134 create_instruction_sub (ri, rn, (4 * nb_registers)));
19135
19136 /* LDMIA Ri!, {R-low-register-list}. */
19137 current_stub_contents =
19138 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19139 create_instruction_ldmia
19140 (ri, /*wback=*/1, insn_low_registers));
19141
19142 /* LDMIA Ri, {R-high-register-list}. */
19143 current_stub_contents =
19144 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19145 create_instruction_ldmia
19146 (ri, /*wback=*/0, insn_high_registers));
19147 }
19148 else if (wback && restore_pc && !restore_rn)
19149 {
19150 /* Choose a Ri in the high-register-list that will be restored. */
19151 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19152
19153 /* SUB Rn, Rn, #(4*nb_registers) */
19154 current_stub_contents =
19155 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19156 create_instruction_sub (rn, rn, (4 * nb_registers)));
19157
19158 /* MOV Ri, Rn. */
19159 current_stub_contents =
19160 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19161 create_instruction_mov (ri, rn));
19162
19163 /* LDMIA Ri!, {R-low-register-list}. */
19164 current_stub_contents =
19165 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19166 create_instruction_ldmia
19167 (ri, /*wback=*/1, insn_low_registers));
19168
19169 /* LDMIA Ri, {R-high-register-list}. */
19170 current_stub_contents =
19171 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19172 create_instruction_ldmia
19173 (ri, /*wback=*/0, insn_high_registers));
19174 }
19175 else if (!wback && !restore_pc && restore_rn)
19176 {
19177 ri = rn;
19178 if (!(insn_low_registers & (1 << rn)))
19179 {
19180 /* Choose a Ri in the low-register-list that will be restored. */
19181 ri = ctz (insn_low_registers & usable_register_mask & ~(1 << rn));
19182
19183 /* MOV Ri, Rn. */
19184 current_stub_contents =
19185 push_thumb2_insn16 (htab, output_bfd, current_stub_contents,
19186 create_instruction_mov (ri, rn));
19187 }
19188
19189 /* LDMDB Ri!, {R-high-register-list}. */
19190 current_stub_contents =
19191 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19192 create_instruction_ldmdb
19193 (ri, /*wback=*/1, insn_high_registers));
19194
19195 /* LDMDB Ri, {R-low-register-list}. */
19196 current_stub_contents =
19197 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19198 create_instruction_ldmdb
19199 (ri, /*wback=*/0, insn_low_registers));
19200
19201 /* B initial_insn_addr+4. */
19202 current_stub_contents =
19203 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19204 create_instruction_branch_absolute
19205 (initial_insn_addr - current_stub_contents));
19206 }
19207 else if (!wback && restore_pc && restore_rn)
19208 {
19209 ri = rn;
19210 if (!(insn_high_registers & (1 << rn)))
19211 {
19212 /* Choose a Ri in the high-register-list that will be restored. */
19213 ri = ctz (insn_high_registers & usable_register_mask & ~(1 << rn));
19214 }
19215
19216 /* SUB Ri, Rn, #(4*nb_registers). */
19217 current_stub_contents =
19218 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19219 create_instruction_sub (ri, rn, (4 * nb_registers)));
19220
19221 /* LDMIA Ri!, {R-low-register-list}. */
19222 current_stub_contents =
19223 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19224 create_instruction_ldmia
19225 (ri, /*wback=*/1, insn_low_registers));
19226
19227 /* LDMIA Ri, {R-high-register-list}. */
19228 current_stub_contents =
19229 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19230 create_instruction_ldmia
19231 (ri, /*wback=*/0, insn_high_registers));
19232 }
19233 else if (wback && restore_rn)
19234 {
19235 /* The assembler should not have accepted to encode this. */
19236 BFD_ASSERT (0 && "Cannot patch an instruction that has an "
19237 "undefined behavior.\n");
19238 }
19239
19240 /* Fill the remaining of the stub with deterministic contents. */
19241 current_stub_contents =
19242 stm32l4xx_fill_stub_udf (htab, output_bfd,
19243 base_stub_contents, current_stub_contents,
19244 base_stub_contents +
19245 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19246
19247 }
19248
19249 static void
19250 stm32l4xx_create_replacing_stub_vldm (struct elf32_arm_link_hash_table * htab,
19251 bfd * output_bfd,
19252 const insn32 initial_insn,
19253 const bfd_byte *const initial_insn_addr,
19254 bfd_byte *const base_stub_contents)
19255 {
19256 int num_words = initial_insn & 0xff;
19257 bfd_byte *current_stub_contents = base_stub_contents;
19258
19259 BFD_ASSERT (is_thumb2_vldm (initial_insn));
19260
19261 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19262 smaller than 8 words load sequences that do not cause the
19263 hardware issue. */
19264 if (num_words <= 8)
19265 {
19266 /* Untouched instruction. */
19267 current_stub_contents =
19268 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19269 initial_insn);
19270
19271 /* B initial_insn_addr+4. */
19272 current_stub_contents =
19273 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19274 create_instruction_branch_absolute
19275 (initial_insn_addr - current_stub_contents));
19276 }
19277 else
19278 {
19279 bool is_dp = /* DP encoding. */
19280 (initial_insn & 0xfe100f00) == 0xec100b00;
19281 bool is_ia_nobang = /* (IA without !). */
19282 (((initial_insn << 7) >> 28) & 0xd) == 0x4;
19283 bool is_ia_bang = /* (IA with !) - includes VPOP. */
19284 (((initial_insn << 7) >> 28) & 0xd) == 0x5;
19285 bool is_db_bang = /* (DB with !). */
19286 (((initial_insn << 7) >> 28) & 0xd) == 0x9;
19287 int base_reg = ((unsigned int) initial_insn << 12) >> 28;
19288 /* d = UInt (Vd:D);. */
19289 int first_reg = ((((unsigned int) initial_insn << 16) >> 28) << 1)
19290 | (((unsigned int)initial_insn << 9) >> 31);
19291
19292 /* Compute the number of 8-words chunks needed to split. */
19293 int chunks = (num_words % 8) ? (num_words / 8 + 1) : (num_words / 8);
19294 int chunk;
19295
19296 /* The test coverage has been done assuming the following
19297 hypothesis that exactly one of the previous is_ predicates is
19298 true. */
19299 BFD_ASSERT ( (is_ia_nobang ^ is_ia_bang ^ is_db_bang)
19300 && !(is_ia_nobang & is_ia_bang & is_db_bang));
19301
19302 /* We treat the cutting of the words in one pass for all
19303 cases, then we emit the adjustments:
19304
19305 vldm rx, {...}
19306 -> vldm rx!, {8_words_or_less} for each needed 8_word
19307 -> sub rx, rx, #size (list)
19308
19309 vldm rx!, {...}
19310 -> vldm rx!, {8_words_or_less} for each needed 8_word
19311 This also handles vpop instruction (when rx is sp)
19312
19313 vldmd rx!, {...}
19314 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
19315 for (chunk = 0; chunk < chunks; ++chunk)
19316 {
19317 bfd_vma new_insn = 0;
19318
19319 if (is_ia_nobang || is_ia_bang)
19320 {
19321 new_insn = create_instruction_vldmia
19322 (base_reg,
19323 is_dp,
19324 /*wback= . */1,
19325 chunks - (chunk + 1) ?
19326 8 : num_words - chunk * 8,
19327 first_reg + chunk * 8);
19328 }
19329 else if (is_db_bang)
19330 {
19331 new_insn = create_instruction_vldmdb
19332 (base_reg,
19333 is_dp,
19334 chunks - (chunk + 1) ?
19335 8 : num_words - chunk * 8,
19336 first_reg + chunk * 8);
19337 }
19338
19339 if (new_insn)
19340 current_stub_contents =
19341 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19342 new_insn);
19343 }
19344
19345 /* Only this case requires the base register compensation
19346 subtract. */
19347 if (is_ia_nobang)
19348 {
19349 current_stub_contents =
19350 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19351 create_instruction_sub
19352 (base_reg, base_reg, 4*num_words));
19353 }
19354
19355 /* B initial_insn_addr+4. */
19356 current_stub_contents =
19357 push_thumb2_insn32 (htab, output_bfd, current_stub_contents,
19358 create_instruction_branch_absolute
19359 (initial_insn_addr - current_stub_contents));
19360 }
19361
19362 /* Fill the remaining of the stub with deterministic contents. */
19363 current_stub_contents =
19364 stm32l4xx_fill_stub_udf (htab, output_bfd,
19365 base_stub_contents, current_stub_contents,
19366 base_stub_contents +
19367 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19368 }
19369
19370 static void
19371 stm32l4xx_create_replacing_stub (struct elf32_arm_link_hash_table * htab,
19372 bfd * output_bfd,
19373 const insn32 wrong_insn,
19374 const bfd_byte *const wrong_insn_addr,
19375 bfd_byte *const stub_contents)
19376 {
19377 if (is_thumb2_ldmia (wrong_insn))
19378 stm32l4xx_create_replacing_stub_ldmia (htab, output_bfd,
19379 wrong_insn, wrong_insn_addr,
19380 stub_contents);
19381 else if (is_thumb2_ldmdb (wrong_insn))
19382 stm32l4xx_create_replacing_stub_ldmdb (htab, output_bfd,
19383 wrong_insn, wrong_insn_addr,
19384 stub_contents);
19385 else if (is_thumb2_vldm (wrong_insn))
19386 stm32l4xx_create_replacing_stub_vldm (htab, output_bfd,
19387 wrong_insn, wrong_insn_addr,
19388 stub_contents);
19389 }
19390
19391 /* End of stm32l4xx work-around. */
19392
19393
19394 /* Do code byteswapping. Return FALSE afterwards so that the section is
19395 written out as normal. */
19396
19397 static bool
19398 elf32_arm_write_section (bfd *output_bfd,
19399 struct bfd_link_info *link_info,
19400 asection *sec,
19401 bfd_byte *contents)
19402 {
19403 unsigned int mapcount, errcount;
19404 _arm_elf_section_data *arm_data;
19405 struct elf32_arm_link_hash_table *globals = elf32_arm_hash_table (link_info);
19406 elf32_arm_section_map *map;
19407 elf32_vfp11_erratum_list *errnode;
19408 elf32_stm32l4xx_erratum_list *stm32l4xx_errnode;
19409 bfd_vma ptr;
19410 bfd_vma end;
19411 bfd_vma offset = sec->output_section->vma + sec->output_offset;
19412 bfd_byte tmp;
19413 unsigned int i;
19414
19415 if (globals == NULL)
19416 return false;
19417
19418 /* If this section has not been allocated an _arm_elf_section_data
19419 structure then we cannot record anything. */
19420 arm_data = get_arm_elf_section_data (sec);
19421 if (arm_data == NULL)
19422 return false;
19423
19424 mapcount = arm_data->mapcount;
19425 map = arm_data->map;
19426 errcount = arm_data->erratumcount;
19427
19428 if (errcount != 0)
19429 {
19430 unsigned int endianflip = bfd_big_endian (output_bfd) ? 3 : 0;
19431
19432 for (errnode = arm_data->erratumlist; errnode != 0;
19433 errnode = errnode->next)
19434 {
19435 bfd_vma target = errnode->vma - offset;
19436
19437 switch (errnode->type)
19438 {
19439 case VFP11_ERRATUM_BRANCH_TO_ARM_VENEER:
19440 {
19441 bfd_vma branch_to_veneer;
19442 /* Original condition code of instruction, plus bit mask for
19443 ARM B instruction. */
19444 unsigned int insn = (errnode->u.b.vfp_insn & 0xf0000000)
19445 | 0x0a000000;
19446
19447 /* The instruction is before the label. */
19448 target -= 4;
19449
19450 /* Above offset included in -4 below. */
19451 branch_to_veneer = errnode->u.b.veneer->vma
19452 - errnode->vma - 4;
19453
19454 if ((signed) branch_to_veneer < -(1 << 25)
19455 || (signed) branch_to_veneer >= (1 << 25))
19456 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
19457 "range"), output_bfd);
19458
19459 insn |= (branch_to_veneer >> 2) & 0xffffff;
19460 contents[endianflip ^ target] = insn & 0xff;
19461 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19462 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19463 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19464 }
19465 break;
19466
19467 case VFP11_ERRATUM_ARM_VENEER:
19468 {
19469 bfd_vma branch_from_veneer;
19470 unsigned int insn;
19471
19472 /* Take size of veneer into account. */
19473 branch_from_veneer = errnode->u.v.branch->vma
19474 - errnode->vma - 12;
19475
19476 if ((signed) branch_from_veneer < -(1 << 25)
19477 || (signed) branch_from_veneer >= (1 << 25))
19478 _bfd_error_handler (_("%pB: error: VFP11 veneer out of "
19479 "range"), output_bfd);
19480
19481 /* Original instruction. */
19482 insn = errnode->u.v.branch->u.b.vfp_insn;
19483 contents[endianflip ^ target] = insn & 0xff;
19484 contents[endianflip ^ (target + 1)] = (insn >> 8) & 0xff;
19485 contents[endianflip ^ (target + 2)] = (insn >> 16) & 0xff;
19486 contents[endianflip ^ (target + 3)] = (insn >> 24) & 0xff;
19487
19488 /* Branch back to insn after original insn. */
19489 insn = 0xea000000 | ((branch_from_veneer >> 2) & 0xffffff);
19490 contents[endianflip ^ (target + 4)] = insn & 0xff;
19491 contents[endianflip ^ (target + 5)] = (insn >> 8) & 0xff;
19492 contents[endianflip ^ (target + 6)] = (insn >> 16) & 0xff;
19493 contents[endianflip ^ (target + 7)] = (insn >> 24) & 0xff;
19494 }
19495 break;
19496
19497 default:
19498 abort ();
19499 }
19500 }
19501 }
19502
19503 if (arm_data->stm32l4xx_erratumcount != 0)
19504 {
19505 for (stm32l4xx_errnode = arm_data->stm32l4xx_erratumlist;
19506 stm32l4xx_errnode != 0;
19507 stm32l4xx_errnode = stm32l4xx_errnode->next)
19508 {
19509 bfd_vma target = stm32l4xx_errnode->vma - offset;
19510
19511 switch (stm32l4xx_errnode->type)
19512 {
19513 case STM32L4XX_ERRATUM_BRANCH_TO_VENEER:
19514 {
19515 unsigned int insn;
19516 bfd_vma branch_to_veneer =
19517 stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma;
19518
19519 if ((signed) branch_to_veneer < -(1 << 24)
19520 || (signed) branch_to_veneer >= (1 << 24))
19521 {
19522 bfd_vma out_of_range =
19523 ((signed) branch_to_veneer < -(1 << 24)) ?
19524 - branch_to_veneer - (1 << 24) :
19525 ((signed) branch_to_veneer >= (1 << 24)) ?
19526 branch_to_veneer - (1 << 24) : 0;
19527
19528 _bfd_error_handler
19529 (_("%pB(%#" PRIx64 "): error: "
19530 "cannot create STM32L4XX veneer; "
19531 "jump out of range by %" PRId64 " bytes; "
19532 "cannot encode branch instruction"),
19533 output_bfd,
19534 (uint64_t) (stm32l4xx_errnode->vma - 4),
19535 (int64_t) out_of_range);
19536 continue;
19537 }
19538
19539 insn = create_instruction_branch_absolute
19540 (stm32l4xx_errnode->u.b.veneer->vma - stm32l4xx_errnode->vma);
19541
19542 /* The instruction is before the label. */
19543 target -= 4;
19544
19545 put_thumb2_insn (globals, output_bfd,
19546 (bfd_vma) insn, contents + target);
19547 }
19548 break;
19549
19550 case STM32L4XX_ERRATUM_VENEER:
19551 {
19552 bfd_byte * veneer;
19553 bfd_byte * veneer_r;
19554 unsigned int insn;
19555
19556 veneer = contents + target;
19557 veneer_r = veneer
19558 + stm32l4xx_errnode->u.b.veneer->vma
19559 - stm32l4xx_errnode->vma - 4;
19560
19561 if ((signed) (veneer_r - veneer -
19562 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19563 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19564 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19565 STM32L4XX_ERRATUM_LDM_VENEER_SIZE) < -(1 << 24)
19566 || (signed) (veneer_r - veneer) >= (1 << 24))
19567 {
19568 _bfd_error_handler (_("%pB: error: cannot create STM32L4XX "
19569 "veneer"), output_bfd);
19570 continue;
19571 }
19572
19573 /* Original instruction. */
19574 insn = stm32l4xx_errnode->u.v.branch->u.b.insn;
19575
19576 stm32l4xx_create_replacing_stub
19577 (globals, output_bfd, insn, (void*)veneer_r, (void*)veneer);
19578 }
19579 break;
19580
19581 default:
19582 abort ();
19583 }
19584 }
19585 }
19586
19587 if (arm_data->elf.this_hdr.sh_type == SHT_ARM_EXIDX)
19588 {
19589 arm_unwind_table_edit *edit_node
19590 = arm_data->u.exidx.unwind_edit_list;
19591 /* Now, sec->size is the size of the section we will write. The original
19592 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
19593 markers) was sec->rawsize. (This isn't the case if we perform no
19594 edits, then rawsize will be zero and we should use size). */
19595 bfd_byte *edited_contents = (bfd_byte *) bfd_malloc (sec->size);
19596 unsigned int input_size = sec->rawsize ? sec->rawsize : sec->size;
19597 unsigned int in_index, out_index;
19598 bfd_vma add_to_offsets = 0;
19599
19600 if (edited_contents == NULL)
19601 return false;
19602 for (in_index = 0, out_index = 0; in_index * 8 < input_size || edit_node;)
19603 {
19604 if (edit_node)
19605 {
19606 unsigned int edit_index = edit_node->index;
19607
19608 if (in_index < edit_index && in_index * 8 < input_size)
19609 {
19610 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19611 contents + in_index * 8, add_to_offsets);
19612 out_index++;
19613 in_index++;
19614 }
19615 else if (in_index == edit_index
19616 || (in_index * 8 >= input_size
19617 && edit_index == UINT_MAX))
19618 {
19619 switch (edit_node->type)
19620 {
19621 case DELETE_EXIDX_ENTRY:
19622 in_index++;
19623 add_to_offsets += 8;
19624 break;
19625
19626 case INSERT_EXIDX_CANTUNWIND_AT_END:
19627 {
19628 asection *text_sec = edit_node->linked_section;
19629 bfd_vma text_offset = text_sec->output_section->vma
19630 + text_sec->output_offset
19631 + text_sec->size;
19632 bfd_vma exidx_offset = offset + out_index * 8;
19633 unsigned long prel31_offset;
19634
19635 /* Note: this is meant to be equivalent to an
19636 R_ARM_PREL31 relocation. These synthetic
19637 EXIDX_CANTUNWIND markers are not relocated by the
19638 usual BFD method. */
19639 prel31_offset = (text_offset - exidx_offset)
19640 & 0x7ffffffful;
19641 if (bfd_link_relocatable (link_info))
19642 {
19643 /* Here relocation for new EXIDX_CANTUNWIND is
19644 created, so there is no need to
19645 adjust offset by hand. */
19646 prel31_offset = text_sec->output_offset
19647 + text_sec->size;
19648 }
19649
19650 /* First address we can't unwind. */
19651 bfd_put_32 (output_bfd, prel31_offset,
19652 &edited_contents[out_index * 8]);
19653
19654 /* Code for EXIDX_CANTUNWIND. */
19655 bfd_put_32 (output_bfd, 0x1,
19656 &edited_contents[out_index * 8 + 4]);
19657
19658 out_index++;
19659 add_to_offsets -= 8;
19660 }
19661 break;
19662 }
19663
19664 edit_node = edit_node->next;
19665 }
19666 }
19667 else
19668 {
19669 /* No more edits, copy remaining entries verbatim. */
19670 copy_exidx_entry (output_bfd, edited_contents + out_index * 8,
19671 contents + in_index * 8, add_to_offsets);
19672 out_index++;
19673 in_index++;
19674 }
19675 }
19676
19677 if (!(sec->flags & SEC_EXCLUDE) && !(sec->flags & SEC_NEVER_LOAD))
19678 bfd_set_section_contents (output_bfd, sec->output_section,
19679 edited_contents,
19680 (file_ptr) sec->output_offset, sec->size);
19681
19682 return true;
19683 }
19684
19685 /* Fix code to point to Cortex-A8 erratum stubs. */
19686 if (globals->fix_cortex_a8)
19687 {
19688 struct a8_branch_to_stub_data data;
19689
19690 data.writing_section = sec;
19691 data.contents = contents;
19692
19693 bfd_hash_traverse (& globals->stub_hash_table, make_branch_to_a8_stub,
19694 & data);
19695 }
19696
19697 if (mapcount == 0)
19698 return false;
19699
19700 if (globals->byteswap_code)
19701 {
19702 qsort (map, mapcount, sizeof (* map), elf32_arm_compare_mapping);
19703
19704 ptr = map[0].vma;
19705 for (i = 0; i < mapcount; i++)
19706 {
19707 if (i == mapcount - 1)
19708 end = sec->size;
19709 else
19710 end = map[i + 1].vma;
19711
19712 switch (map[i].type)
19713 {
19714 case 'a':
19715 /* Byte swap code words. */
19716 while (ptr + 3 < end)
19717 {
19718 tmp = contents[ptr];
19719 contents[ptr] = contents[ptr + 3];
19720 contents[ptr + 3] = tmp;
19721 tmp = contents[ptr + 1];
19722 contents[ptr + 1] = contents[ptr + 2];
19723 contents[ptr + 2] = tmp;
19724 ptr += 4;
19725 }
19726 break;
19727
19728 case 't':
19729 /* Byte swap code halfwords. */
19730 while (ptr + 1 < end)
19731 {
19732 tmp = contents[ptr];
19733 contents[ptr] = contents[ptr + 1];
19734 contents[ptr + 1] = tmp;
19735 ptr += 2;
19736 }
19737 break;
19738
19739 case 'd':
19740 /* Leave data alone. */
19741 break;
19742 }
19743 ptr = end;
19744 }
19745 }
19746
19747 free (map);
19748 arm_data->mapcount = -1;
19749 arm_data->mapsize = 0;
19750 arm_data->map = NULL;
19751
19752 return false;
19753 }
19754
19755 /* Mangle thumb function symbols as we read them in. */
19756
19757 static bool
19758 elf32_arm_swap_symbol_in (bfd * abfd,
19759 const void *psrc,
19760 const void *pshn,
19761 Elf_Internal_Sym *dst)
19762 {
19763 if (!bfd_elf32_swap_symbol_in (abfd, psrc, pshn, dst))
19764 return false;
19765 dst->st_target_internal = 0;
19766
19767 /* New EABI objects mark thumb function symbols by setting the low bit of
19768 the address. */
19769 if (ELF_ST_TYPE (dst->st_info) == STT_FUNC
19770 || ELF_ST_TYPE (dst->st_info) == STT_GNU_IFUNC)
19771 {
19772 if (dst->st_value & 1)
19773 {
19774 dst->st_value &= ~(bfd_vma) 1;
19775 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal,
19776 ST_BRANCH_TO_THUMB);
19777 }
19778 else
19779 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_ARM);
19780 }
19781 else if (ELF_ST_TYPE (dst->st_info) == STT_ARM_TFUNC)
19782 {
19783 dst->st_info = ELF_ST_INFO (ELF_ST_BIND (dst->st_info), STT_FUNC);
19784 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_TO_THUMB);
19785 }
19786 else if (ELF_ST_TYPE (dst->st_info) == STT_SECTION)
19787 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_LONG);
19788 else
19789 ARM_SET_SYM_BRANCH_TYPE (dst->st_target_internal, ST_BRANCH_UNKNOWN);
19790
19791 return true;
19792 }
19793
19794
19795 /* Mangle thumb function symbols as we write them out. */
19796
19797 static void
19798 elf32_arm_swap_symbol_out (bfd *abfd,
19799 const Elf_Internal_Sym *src,
19800 void *cdst,
19801 void *shndx)
19802 {
19803 Elf_Internal_Sym newsym;
19804
19805 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19806 of the address set, as per the new EABI. We do this unconditionally
19807 because objcopy does not set the elf header flags until after
19808 it writes out the symbol table. */
19809 if (ARM_GET_SYM_BRANCH_TYPE (src->st_target_internal) == ST_BRANCH_TO_THUMB)
19810 {
19811 newsym = *src;
19812 if (ELF_ST_TYPE (src->st_info) != STT_GNU_IFUNC)
19813 newsym.st_info = ELF_ST_INFO (ELF_ST_BIND (src->st_info), STT_FUNC);
19814 if (newsym.st_shndx != SHN_UNDEF)
19815 {
19816 /* Do this only for defined symbols. At link type, the static
19817 linker will simulate the work of dynamic linker of resolving
19818 symbols and will carry over the thumbness of found symbols to
19819 the output symbol table. It's not clear how it happens, but
19820 the thumbness of undefined symbols can well be different at
19821 runtime, and writing '1' for them will be confusing for users
19822 and possibly for dynamic linker itself.
19823 */
19824 newsym.st_value |= 1;
19825 }
19826
19827 src = &newsym;
19828 }
19829 bfd_elf32_swap_symbol_out (abfd, src, cdst, shndx);
19830 }
19831
19832 /* Add the PT_ARM_EXIDX program header. */
19833
19834 static bool
19835 elf32_arm_modify_segment_map (bfd *abfd,
19836 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19837 {
19838 struct elf_segment_map *m;
19839 asection *sec;
19840
19841 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19842 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19843 {
19844 /* If there is already a PT_ARM_EXIDX header, then we do not
19845 want to add another one. This situation arises when running
19846 "strip"; the input binary already has the header. */
19847 m = elf_seg_map (abfd);
19848 while (m && m->p_type != PT_ARM_EXIDX)
19849 m = m->next;
19850 if (!m)
19851 {
19852 m = (struct elf_segment_map *)
19853 bfd_zalloc (abfd, sizeof (struct elf_segment_map));
19854 if (m == NULL)
19855 return false;
19856 m->p_type = PT_ARM_EXIDX;
19857 m->count = 1;
19858 m->sections[0] = sec;
19859
19860 m->next = elf_seg_map (abfd);
19861 elf_seg_map (abfd) = m;
19862 }
19863 }
19864
19865 return true;
19866 }
19867
19868 /* We may add a PT_ARM_EXIDX program header. */
19869
19870 static int
19871 elf32_arm_additional_program_headers (bfd *abfd,
19872 struct bfd_link_info *info ATTRIBUTE_UNUSED)
19873 {
19874 asection *sec;
19875
19876 sec = bfd_get_section_by_name (abfd, ".ARM.exidx");
19877 if (sec != NULL && (sec->flags & SEC_LOAD) != 0)
19878 return 1;
19879 else
19880 return 0;
19881 }
19882
19883 /* Hook called by the linker routine which adds symbols from an object
19884 file. */
19885
19886 static bool
19887 elf32_arm_add_symbol_hook (bfd *abfd, struct bfd_link_info *info,
19888 Elf_Internal_Sym *sym, const char **namep,
19889 flagword *flagsp, asection **secp, bfd_vma *valp)
19890 {
19891 if (elf32_arm_hash_table (info) == NULL)
19892 return false;
19893
19894 if (elf32_arm_hash_table (info)->root.target_os == is_vxworks
19895 && !elf_vxworks_add_symbol_hook (abfd, info, sym, namep,
19896 flagsp, secp, valp))
19897 return false;
19898
19899 return true;
19900 }
19901
19902 /* We use this to override swap_symbol_in and swap_symbol_out. */
19903 const struct elf_size_info elf32_arm_size_info =
19904 {
19905 sizeof (Elf32_External_Ehdr),
19906 sizeof (Elf32_External_Phdr),
19907 sizeof (Elf32_External_Shdr),
19908 sizeof (Elf32_External_Rel),
19909 sizeof (Elf32_External_Rela),
19910 sizeof (Elf32_External_Sym),
19911 sizeof (Elf32_External_Dyn),
19912 sizeof (Elf_External_Note),
19913 4,
19914 1,
19915 32, 2,
19916 ELFCLASS32, EV_CURRENT,
19917 bfd_elf32_write_out_phdrs,
19918 bfd_elf32_write_shdrs_and_ehdr,
19919 bfd_elf32_checksum_contents,
19920 bfd_elf32_write_relocs,
19921 elf32_arm_swap_symbol_in,
19922 elf32_arm_swap_symbol_out,
19923 bfd_elf32_slurp_reloc_table,
19924 bfd_elf32_slurp_symbol_table,
19925 bfd_elf32_swap_dyn_in,
19926 bfd_elf32_swap_dyn_out,
19927 bfd_elf32_swap_reloc_in,
19928 bfd_elf32_swap_reloc_out,
19929 bfd_elf32_swap_reloca_in,
19930 bfd_elf32_swap_reloca_out
19931 };
19932
19933 static bfd_vma
19934 read_code32 (const bfd *abfd, const bfd_byte *addr)
19935 {
19936 /* V7 BE8 code is always little endian. */
19937 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19938 return bfd_getl32 (addr);
19939
19940 return bfd_get_32 (abfd, addr);
19941 }
19942
19943 static bfd_vma
19944 read_code16 (const bfd *abfd, const bfd_byte *addr)
19945 {
19946 /* V7 BE8 code is always little endian. */
19947 if ((elf_elfheader (abfd)->e_flags & EF_ARM_BE8) != 0)
19948 return bfd_getl16 (addr);
19949
19950 return bfd_get_16 (abfd, addr);
19951 }
19952
19953 /* Return size of plt0 entry starting at ADDR
19954 or (bfd_vma) -1 if size can not be determined. */
19955
19956 static bfd_vma
19957 elf32_arm_plt0_size (const bfd *abfd, const bfd_byte *addr)
19958 {
19959 bfd_vma first_word;
19960 bfd_vma plt0_size;
19961
19962 first_word = read_code32 (abfd, addr);
19963
19964 if (first_word == elf32_arm_plt0_entry[0])
19965 plt0_size = 4 * ARRAY_SIZE (elf32_arm_plt0_entry);
19966 else if (first_word == elf32_thumb2_plt0_entry[0])
19967 plt0_size = 4 * ARRAY_SIZE (elf32_thumb2_plt0_entry);
19968 else
19969 /* We don't yet handle this PLT format. */
19970 return (bfd_vma) -1;
19971
19972 return plt0_size;
19973 }
19974
19975 /* Return size of plt entry starting at offset OFFSET
19976 of plt section located at address START
19977 or (bfd_vma) -1 if size can not be determined. */
19978
19979 static bfd_vma
19980 elf32_arm_plt_size (const bfd *abfd, const bfd_byte *start, bfd_vma offset)
19981 {
19982 bfd_vma first_insn;
19983 bfd_vma plt_size = 0;
19984 const bfd_byte *addr = start + offset;
19985
19986 /* PLT entry size if fixed on Thumb-only platforms. */
19987 if (read_code32 (abfd, start) == elf32_thumb2_plt0_entry[0])
19988 return 4 * ARRAY_SIZE (elf32_thumb2_plt_entry);
19989
19990 /* Respect Thumb stub if necessary. */
19991 if (read_code16 (abfd, addr) == elf32_arm_plt_thumb_stub[0])
19992 {
19993 plt_size += 2 * ARRAY_SIZE (elf32_arm_plt_thumb_stub);
19994 }
19995
19996 /* Strip immediate from first add. */
19997 first_insn = read_code32 (abfd, addr + plt_size) & 0xffffff00;
19998
19999 #ifdef FOUR_WORD_PLT
20000 if (first_insn == elf32_arm_plt_entry[0])
20001 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry);
20002 #else
20003 if (first_insn == elf32_arm_plt_entry_long[0])
20004 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_long);
20005 else if (first_insn == elf32_arm_plt_entry_short[0])
20006 plt_size += 4 * ARRAY_SIZE (elf32_arm_plt_entry_short);
20007 #endif
20008 else
20009 /* We don't yet handle this PLT format. */
20010 return (bfd_vma) -1;
20011
20012 return plt_size;
20013 }
20014
20015 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20016
20017 static long
20018 elf32_arm_get_synthetic_symtab (bfd *abfd,
20019 long symcount ATTRIBUTE_UNUSED,
20020 asymbol **syms ATTRIBUTE_UNUSED,
20021 long dynsymcount,
20022 asymbol **dynsyms,
20023 asymbol **ret)
20024 {
20025 asection *relplt;
20026 asymbol *s;
20027 arelent *p;
20028 long count, i, n;
20029 size_t size;
20030 Elf_Internal_Shdr *hdr;
20031 char *names;
20032 asection *plt;
20033 bfd_vma offset;
20034 bfd_byte *data;
20035
20036 *ret = NULL;
20037
20038 if ((abfd->flags & (DYNAMIC | EXEC_P)) == 0)
20039 return 0;
20040
20041 if (dynsymcount <= 0)
20042 return 0;
20043
20044 relplt = bfd_get_section_by_name (abfd, ".rel.plt");
20045 if (relplt == NULL)
20046 return 0;
20047
20048 hdr = &elf_section_data (relplt)->this_hdr;
20049 if (hdr->sh_link != elf_dynsymtab (abfd)
20050 || (hdr->sh_type != SHT_REL && hdr->sh_type != SHT_RELA))
20051 return 0;
20052
20053 plt = bfd_get_section_by_name (abfd, ".plt");
20054 if (plt == NULL)
20055 return 0;
20056
20057 if (!elf32_arm_size_info.slurp_reloc_table (abfd, relplt, dynsyms, true))
20058 return -1;
20059
20060 data = plt->contents;
20061 if (data == NULL)
20062 {
20063 if (!bfd_get_full_section_contents (abfd, plt, &data)
20064 || data == NULL)
20065 return -1;
20066 plt->contents = data;
20067 plt->flags |= SEC_IN_MEMORY;
20068 }
20069
20070 count = NUM_SHDR_ENTRIES (hdr);
20071 size = count * sizeof (asymbol);
20072 p = relplt->relocation;
20073 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20074 {
20075 size += strlen ((*p->sym_ptr_ptr)->name) + sizeof ("@plt");
20076 if (p->addend != 0)
20077 size += sizeof ("+0x") - 1 + 8;
20078 }
20079
20080 s = *ret = (asymbol *) bfd_malloc (size);
20081 if (s == NULL)
20082 return -1;
20083
20084 offset = elf32_arm_plt0_size (abfd, data);
20085 if (offset == (bfd_vma) -1)
20086 return -1;
20087
20088 names = (char *) (s + count);
20089 p = relplt->relocation;
20090 n = 0;
20091 for (i = 0; i < count; i++, p += elf32_arm_size_info.int_rels_per_ext_rel)
20092 {
20093 size_t len;
20094
20095 bfd_vma plt_size = elf32_arm_plt_size (abfd, data, offset);
20096 if (plt_size == (bfd_vma) -1)
20097 break;
20098
20099 *s = **p->sym_ptr_ptr;
20100 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20101 we are defining a symbol, ensure one of them is set. */
20102 if ((s->flags & BSF_LOCAL) == 0)
20103 s->flags |= BSF_GLOBAL;
20104 s->flags |= BSF_SYNTHETIC;
20105 s->section = plt;
20106 s->value = offset;
20107 s->name = names;
20108 s->udata.p = NULL;
20109 len = strlen ((*p->sym_ptr_ptr)->name);
20110 memcpy (names, (*p->sym_ptr_ptr)->name, len);
20111 names += len;
20112 if (p->addend != 0)
20113 {
20114 char buf[30], *a;
20115
20116 memcpy (names, "+0x", sizeof ("+0x") - 1);
20117 names += sizeof ("+0x") - 1;
20118 bfd_sprintf_vma (abfd, buf, p->addend);
20119 for (a = buf; *a == '0'; ++a)
20120 ;
20121 len = strlen (a);
20122 memcpy (names, a, len);
20123 names += len;
20124 }
20125 memcpy (names, "@plt", sizeof ("@plt"));
20126 names += sizeof ("@plt");
20127 ++s, ++n;
20128 offset += plt_size;
20129 }
20130
20131 return n;
20132 }
20133
20134 static bool
20135 elf32_arm_section_flags (const Elf_Internal_Shdr *hdr)
20136 {
20137 if (hdr->sh_flags & SHF_ARM_PURECODE)
20138 hdr->bfd_section->flags |= SEC_ELF_PURECODE;
20139 return true;
20140 }
20141
20142 static flagword
20143 elf32_arm_lookup_section_flags (char *flag_name)
20144 {
20145 if (!strcmp (flag_name, "SHF_ARM_PURECODE"))
20146 return SHF_ARM_PURECODE;
20147
20148 return SEC_NO_FLAGS;
20149 }
20150
20151 static unsigned int
20152 elf32_arm_count_additional_relocs (asection *sec)
20153 {
20154 struct _arm_elf_section_data *arm_data;
20155 arm_data = get_arm_elf_section_data (sec);
20156
20157 return arm_data == NULL ? 0 : arm_data->additional_reloc_count;
20158 }
20159
20160 /* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
20161 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
20162 FALSE otherwise. ISECTION is the best guess matching section from the
20163 input bfd IBFD, but it might be NULL. */
20164
20165 static bool
20166 elf32_arm_copy_special_section_fields (const bfd *ibfd ATTRIBUTE_UNUSED,
20167 bfd *obfd ATTRIBUTE_UNUSED,
20168 const Elf_Internal_Shdr *isection ATTRIBUTE_UNUSED,
20169 Elf_Internal_Shdr *osection)
20170 {
20171 switch (osection->sh_type)
20172 {
20173 case SHT_ARM_EXIDX:
20174 {
20175 Elf_Internal_Shdr **oheaders = elf_elfsections (obfd);
20176 Elf_Internal_Shdr **iheaders = elf_elfsections (ibfd);
20177 unsigned i = 0;
20178
20179 osection->sh_flags = SHF_ALLOC | SHF_LINK_ORDER;
20180 osection->sh_info = 0;
20181
20182 /* The sh_link field must be set to the text section associated with
20183 this index section. Unfortunately the ARM EHABI does not specify
20184 exactly how to determine this association. Our caller does try
20185 to match up OSECTION with its corresponding input section however
20186 so that is a good first guess. */
20187 if (isection != NULL
20188 && osection->bfd_section != NULL
20189 && isection->bfd_section != NULL
20190 && isection->bfd_section->output_section != NULL
20191 && isection->bfd_section->output_section == osection->bfd_section
20192 && iheaders != NULL
20193 && isection->sh_link > 0
20194 && isection->sh_link < elf_numsections (ibfd)
20195 && iheaders[isection->sh_link]->bfd_section != NULL
20196 && iheaders[isection->sh_link]->bfd_section->output_section != NULL
20197 )
20198 {
20199 for (i = elf_numsections (obfd); i-- > 0;)
20200 if (oheaders[i]->bfd_section
20201 == iheaders[isection->sh_link]->bfd_section->output_section)
20202 break;
20203 }
20204
20205 if (i == 0)
20206 {
20207 /* Failing that we have to find a matching section ourselves. If
20208 we had the output section name available we could compare that
20209 with input section names. Unfortunately we don't. So instead
20210 we use a simple heuristic and look for the nearest executable
20211 section before this one. */
20212 for (i = elf_numsections (obfd); i-- > 0;)
20213 if (oheaders[i] == osection)
20214 break;
20215 if (i == 0)
20216 break;
20217
20218 while (i-- > 0)
20219 if (oheaders[i]->sh_type == SHT_PROGBITS
20220 && (oheaders[i]->sh_flags & (SHF_ALLOC | SHF_EXECINSTR))
20221 == (SHF_ALLOC | SHF_EXECINSTR))
20222 break;
20223 }
20224
20225 if (i)
20226 {
20227 osection->sh_link = i;
20228 /* If the text section was part of a group
20229 then the index section should be too. */
20230 if (oheaders[i]->sh_flags & SHF_GROUP)
20231 osection->sh_flags |= SHF_GROUP;
20232 return true;
20233 }
20234 }
20235 break;
20236
20237 case SHT_ARM_PREEMPTMAP:
20238 osection->sh_flags = SHF_ALLOC;
20239 break;
20240
20241 case SHT_ARM_ATTRIBUTES:
20242 case SHT_ARM_DEBUGOVERLAY:
20243 case SHT_ARM_OVERLAYSECTION:
20244 default:
20245 break;
20246 }
20247
20248 return false;
20249 }
20250
20251 /* Returns TRUE if NAME is an ARM mapping symbol.
20252 Traditionally the symbols $a, $d and $t have been used.
20253 The ARM ELF standard also defines $x (for A64 code). It also allows a
20254 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20255 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20256 not support them here. $t.x indicates the start of ThumbEE instructions. */
20257
20258 static bool
20259 is_arm_mapping_symbol (const char * name)
20260 {
20261 return name != NULL /* Paranoia. */
20262 && name[0] == '$' /* Note: if objcopy --prefix-symbols has been used then
20263 the mapping symbols could have acquired a prefix.
20264 We do not support this here, since such symbols no
20265 longer conform to the ARM ELF ABI. */
20266 && (name[1] == 'a' || name[1] == 'd' || name[1] == 't' || name[1] == 'x')
20267 && (name[2] == 0 || name[2] == '.');
20268 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20269 any characters that follow the period are legal characters for the body
20270 of a symbol's name. For now we just assume that this is the case. */
20271 }
20272
20273 /* Make sure that mapping symbols in object files are not removed via the
20274 "strip --strip-unneeded" tool. These symbols are needed in order to
20275 correctly generate interworking veneers, and for byte swapping code
20276 regions. Once an object file has been linked, it is safe to remove the
20277 symbols as they will no longer be needed. */
20278
20279 static void
20280 elf32_arm_backend_symbol_processing (bfd *abfd, asymbol *sym)
20281 {
20282 if (((abfd->flags & (EXEC_P | DYNAMIC)) == 0)
20283 && sym->section != bfd_abs_section_ptr
20284 && is_arm_mapping_symbol (sym->name))
20285 sym->flags |= BSF_KEEP;
20286 }
20287
20288 #undef elf_backend_copy_special_section_fields
20289 #define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20290
20291 #define ELF_ARCH bfd_arch_arm
20292 #define ELF_TARGET_ID ARM_ELF_DATA
20293 #define ELF_MACHINE_CODE EM_ARM
20294 #define ELF_MAXPAGESIZE 0x1000
20295 #define ELF_COMMONPAGESIZE 0x1000
20296
20297 #define bfd_elf32_mkobject elf32_arm_mkobject
20298
20299 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20300 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
20301 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20302 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
20303 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
20304 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
20305 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
20306 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
20307 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
20308 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
20309 #define bfd_elf32_bfd_final_link elf32_arm_final_link
20310 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
20311
20312 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20313 #define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
20314 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
20315 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
20316 #define elf_backend_check_relocs elf32_arm_check_relocs
20317 #define elf_backend_update_relocs elf32_arm_update_relocs
20318 #define elf_backend_relocate_section elf32_arm_relocate_section
20319 #define elf_backend_write_section elf32_arm_write_section
20320 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
20321 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
20322 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20323 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20324 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
20325 #define elf_backend_always_size_sections elf32_arm_always_size_sections
20326 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
20327 #define elf_backend_init_file_header elf32_arm_init_file_header
20328 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
20329 #define elf_backend_object_p elf32_arm_object_p
20330 #define elf_backend_fake_sections elf32_arm_fake_sections
20331 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20332 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20333 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
20334 #define elf_backend_size_info elf32_arm_size_info
20335 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20336 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20337 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
20338 #define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
20339 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
20340 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
20341 #define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
20342 #define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
20343
20344 #define elf_backend_can_refcount 1
20345 #define elf_backend_can_gc_sections 1
20346 #define elf_backend_plt_readonly 1
20347 #define elf_backend_want_got_plt 1
20348 #define elf_backend_want_plt_sym 0
20349 #define elf_backend_want_dynrelro 1
20350 #define elf_backend_may_use_rel_p 1
20351 #define elf_backend_may_use_rela_p 0
20352 #define elf_backend_default_use_rela_p 0
20353 #define elf_backend_dtrel_excludes_plt 1
20354
20355 #define elf_backend_got_header_size 12
20356 #define elf_backend_extern_protected_data 0
20357
20358 #undef elf_backend_obj_attrs_vendor
20359 #define elf_backend_obj_attrs_vendor "aeabi"
20360 #undef elf_backend_obj_attrs_section
20361 #define elf_backend_obj_attrs_section ".ARM.attributes"
20362 #undef elf_backend_obj_attrs_arg_type
20363 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
20364 #undef elf_backend_obj_attrs_section_type
20365 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
20366 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
20367 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
20368
20369 #undef elf_backend_section_flags
20370 #define elf_backend_section_flags elf32_arm_section_flags
20371 #undef elf_backend_lookup_section_flags_hook
20372 #define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
20373
20374 #define elf_backend_linux_prpsinfo32_ugid16 true
20375
20376 #include "elf32-target.h"
20377
20378 /* Native Client targets. */
20379
20380 #undef TARGET_LITTLE_SYM
20381 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
20382 #undef TARGET_LITTLE_NAME
20383 #define TARGET_LITTLE_NAME "elf32-littlearm-nacl"
20384 #undef TARGET_BIG_SYM
20385 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
20386 #undef TARGET_BIG_NAME
20387 #define TARGET_BIG_NAME "elf32-bigarm-nacl"
20388
20389 /* Like elf32_arm_link_hash_table_create -- but overrides
20390 appropriately for NaCl. */
20391
20392 static struct bfd_link_hash_table *
20393 elf32_arm_nacl_link_hash_table_create (bfd *abfd)
20394 {
20395 struct bfd_link_hash_table *ret;
20396
20397 ret = elf32_arm_link_hash_table_create (abfd);
20398 if (ret)
20399 {
20400 struct elf32_arm_link_hash_table *htab
20401 = (struct elf32_arm_link_hash_table *) ret;
20402
20403 htab->plt_header_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt0_entry);
20404 htab->plt_entry_size = 4 * ARRAY_SIZE (elf32_arm_nacl_plt_entry);
20405 }
20406 return ret;
20407 }
20408
20409 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
20410 really need to use elf32_arm_modify_segment_map. But we do it
20411 anyway just to reduce gratuitous differences with the stock ARM backend. */
20412
20413 static bool
20414 elf32_arm_nacl_modify_segment_map (bfd *abfd, struct bfd_link_info *info)
20415 {
20416 return (elf32_arm_modify_segment_map (abfd, info)
20417 && nacl_modify_segment_map (abfd, info));
20418 }
20419
20420 static bool
20421 elf32_arm_nacl_final_write_processing (bfd *abfd)
20422 {
20423 arm_final_write_processing (abfd);
20424 return nacl_final_write_processing (abfd);
20425 }
20426
20427 static bfd_vma
20428 elf32_arm_nacl_plt_sym_val (bfd_vma i, const asection *plt,
20429 const arelent *rel ATTRIBUTE_UNUSED)
20430 {
20431 return plt->vma
20432 + 4 * (ARRAY_SIZE (elf32_arm_nacl_plt0_entry) +
20433 i * ARRAY_SIZE (elf32_arm_nacl_plt_entry));
20434 }
20435
20436 #undef elf32_bed
20437 #define elf32_bed elf32_arm_nacl_bed
20438 #undef bfd_elf32_bfd_link_hash_table_create
20439 #define bfd_elf32_bfd_link_hash_table_create \
20440 elf32_arm_nacl_link_hash_table_create
20441 #undef elf_backend_plt_alignment
20442 #define elf_backend_plt_alignment 4
20443 #undef elf_backend_modify_segment_map
20444 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20445 #undef elf_backend_modify_headers
20446 #define elf_backend_modify_headers nacl_modify_headers
20447 #undef elf_backend_final_write_processing
20448 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
20449 #undef bfd_elf32_get_synthetic_symtab
20450 #undef elf_backend_plt_sym_val
20451 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
20452 #undef elf_backend_copy_special_section_fields
20453
20454 #undef ELF_MINPAGESIZE
20455 #undef ELF_COMMONPAGESIZE
20456
20457 #undef ELF_TARGET_OS
20458 #define ELF_TARGET_OS is_nacl
20459
20460 #include "elf32-target.h"
20461
20462 /* Reset to defaults. */
20463 #undef elf_backend_plt_alignment
20464 #undef elf_backend_modify_segment_map
20465 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20466 #undef elf_backend_modify_headers
20467 #undef elf_backend_final_write_processing
20468 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20469 #undef ELF_MINPAGESIZE
20470 #undef ELF_COMMONPAGESIZE
20471 #define ELF_COMMONPAGESIZE 0x1000
20472
20473
20474 /* FDPIC Targets. */
20475
20476 #undef TARGET_LITTLE_SYM
20477 #define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20478 #undef TARGET_LITTLE_NAME
20479 #define TARGET_LITTLE_NAME "elf32-littlearm-fdpic"
20480 #undef TARGET_BIG_SYM
20481 #define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20482 #undef TARGET_BIG_NAME
20483 #define TARGET_BIG_NAME "elf32-bigarm-fdpic"
20484 #undef elf_match_priority
20485 #define elf_match_priority 128
20486 #undef ELF_OSABI
20487 #define ELF_OSABI ELFOSABI_ARM_FDPIC
20488
20489 /* Like elf32_arm_link_hash_table_create -- but overrides
20490 appropriately for FDPIC. */
20491
20492 static struct bfd_link_hash_table *
20493 elf32_arm_fdpic_link_hash_table_create (bfd *abfd)
20494 {
20495 struct bfd_link_hash_table *ret;
20496
20497 ret = elf32_arm_link_hash_table_create (abfd);
20498 if (ret)
20499 {
20500 struct elf32_arm_link_hash_table *htab = (struct elf32_arm_link_hash_table *) ret;
20501
20502 htab->fdpic_p = 1;
20503 }
20504 return ret;
20505 }
20506
20507 /* We need dynamic symbols for every section, since segments can
20508 relocate independently. */
20509 static bool
20510 elf32_arm_fdpic_omit_section_dynsym (bfd *output_bfd ATTRIBUTE_UNUSED,
20511 struct bfd_link_info *info
20512 ATTRIBUTE_UNUSED,
20513 asection *p ATTRIBUTE_UNUSED)
20514 {
20515 switch (elf_section_data (p)->this_hdr.sh_type)
20516 {
20517 case SHT_PROGBITS:
20518 case SHT_NOBITS:
20519 /* If sh_type is yet undecided, assume it could be
20520 SHT_PROGBITS/SHT_NOBITS. */
20521 case SHT_NULL:
20522 return false;
20523
20524 /* There shouldn't be section relative relocations
20525 against any other section. */
20526 default:
20527 return true;
20528 }
20529 }
20530
20531 #undef elf32_bed
20532 #define elf32_bed elf32_arm_fdpic_bed
20533
20534 #undef bfd_elf32_bfd_link_hash_table_create
20535 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20536
20537 #undef elf_backend_omit_section_dynsym
20538 #define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20539
20540 #undef ELF_TARGET_OS
20541
20542 #include "elf32-target.h"
20543
20544 #undef elf_match_priority
20545 #undef ELF_OSABI
20546 #undef elf_backend_omit_section_dynsym
20547
20548 /* VxWorks Targets. */
20549
20550 #undef TARGET_LITTLE_SYM
20551 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20552 #undef TARGET_LITTLE_NAME
20553 #define TARGET_LITTLE_NAME "elf32-littlearm-vxworks"
20554 #undef TARGET_BIG_SYM
20555 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20556 #undef TARGET_BIG_NAME
20557 #define TARGET_BIG_NAME "elf32-bigarm-vxworks"
20558
20559 /* Like elf32_arm_link_hash_table_create -- but overrides
20560 appropriately for VxWorks. */
20561
20562 static struct bfd_link_hash_table *
20563 elf32_arm_vxworks_link_hash_table_create (bfd *abfd)
20564 {
20565 struct bfd_link_hash_table *ret;
20566
20567 ret = elf32_arm_link_hash_table_create (abfd);
20568 if (ret)
20569 {
20570 struct elf32_arm_link_hash_table *htab
20571 = (struct elf32_arm_link_hash_table *) ret;
20572 htab->use_rel = 0;
20573 }
20574 return ret;
20575 }
20576
20577 static bool
20578 elf32_arm_vxworks_final_write_processing (bfd *abfd)
20579 {
20580 arm_final_write_processing (abfd);
20581 return elf_vxworks_final_write_processing (abfd);
20582 }
20583
20584 #undef elf32_bed
20585 #define elf32_bed elf32_arm_vxworks_bed
20586
20587 #undef bfd_elf32_bfd_link_hash_table_create
20588 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
20589 #undef elf_backend_final_write_processing
20590 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20591 #undef elf_backend_emit_relocs
20592 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
20593
20594 #undef elf_backend_may_use_rel_p
20595 #define elf_backend_may_use_rel_p 0
20596 #undef elf_backend_may_use_rela_p
20597 #define elf_backend_may_use_rela_p 1
20598 #undef elf_backend_default_use_rela_p
20599 #define elf_backend_default_use_rela_p 1
20600 #undef elf_backend_want_plt_sym
20601 #define elf_backend_want_plt_sym 1
20602 #undef ELF_MAXPAGESIZE
20603 #define ELF_MAXPAGESIZE 0x1000
20604 #undef ELF_TARGET_OS
20605 #define ELF_TARGET_OS is_vxworks
20606
20607 #include "elf32-target.h"
20608
20609
20610 /* Merge backend specific data from an object file to the output
20611 object file when linking. */
20612
20613 static bool
20614 elf32_arm_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
20615 {
20616 bfd *obfd = info->output_bfd;
20617 flagword out_flags;
20618 flagword in_flags;
20619 bool flags_compatible = true;
20620 asection *sec;
20621
20622 /* Check if we have the same endianness. */
20623 if (! _bfd_generic_verify_endian_match (ibfd, info))
20624 return false;
20625
20626 if (! is_arm_elf (ibfd) || ! is_arm_elf (obfd))
20627 return true;
20628
20629 if (!elf32_arm_merge_eabi_attributes (ibfd, info))
20630 return false;
20631
20632 /* The input BFD must have had its flags initialised. */
20633 /* The following seems bogus to me -- The flags are initialized in
20634 the assembler but I don't think an elf_flags_init field is
20635 written into the object. */
20636 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20637
20638 in_flags = elf_elfheader (ibfd)->e_flags;
20639 out_flags = elf_elfheader (obfd)->e_flags;
20640
20641 /* In theory there is no reason why we couldn't handle this. However
20642 in practice it isn't even close to working and there is no real
20643 reason to want it. */
20644 if (EF_ARM_EABI_VERSION (in_flags) >= EF_ARM_EABI_VER4
20645 && !(ibfd->flags & DYNAMIC)
20646 && (in_flags & EF_ARM_BE8))
20647 {
20648 _bfd_error_handler (_("error: %pB is already in final BE8 format"),
20649 ibfd);
20650 return false;
20651 }
20652
20653 if (!elf_flags_init (obfd))
20654 {
20655 /* If the input is the default architecture and had the default
20656 flags then do not bother setting the flags for the output
20657 architecture, instead allow future merges to do this. If no
20658 future merges ever set these flags then they will retain their
20659 uninitialised values, which surprise surprise, correspond
20660 to the default values. */
20661 if (bfd_get_arch_info (ibfd)->the_default
20662 && elf_elfheader (ibfd)->e_flags == 0)
20663 return true;
20664
20665 elf_flags_init (obfd) = true;
20666 elf_elfheader (obfd)->e_flags = in_flags;
20667
20668 if (bfd_get_arch (obfd) == bfd_get_arch (ibfd)
20669 && bfd_get_arch_info (obfd)->the_default)
20670 return bfd_set_arch_mach (obfd, bfd_get_arch (ibfd), bfd_get_mach (ibfd));
20671
20672 return true;
20673 }
20674
20675 /* Determine what should happen if the input ARM architecture
20676 does not match the output ARM architecture. */
20677 if (! bfd_arm_merge_machines (ibfd, obfd))
20678 return false;
20679
20680 /* Identical flags must be compatible. */
20681 if (in_flags == out_flags)
20682 return true;
20683
20684 /* Check to see if the input BFD actually contains any sections. If
20685 not, its flags may not have been initialised either, but it
20686 cannot actually cause any incompatiblity. Do not short-circuit
20687 dynamic objects; their section list may be emptied by
20688 elf_link_add_object_symbols.
20689
20690 Also check to see if there are no code sections in the input.
20691 In this case there is no need to check for code specific flags.
20692 XXX - do we need to worry about floating-point format compatability
20693 in data sections ? */
20694 if (!(ibfd->flags & DYNAMIC))
20695 {
20696 bool null_input_bfd = true;
20697 bool only_data_sections = true;
20698
20699 for (sec = ibfd->sections; sec != NULL; sec = sec->next)
20700 {
20701 /* Ignore synthetic glue sections. */
20702 if (strcmp (sec->name, ".glue_7")
20703 && strcmp (sec->name, ".glue_7t"))
20704 {
20705 if ((bfd_section_flags (sec)
20706 & (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20707 == (SEC_LOAD | SEC_CODE | SEC_HAS_CONTENTS))
20708 only_data_sections = false;
20709
20710 null_input_bfd = false;
20711 break;
20712 }
20713 }
20714
20715 if (null_input_bfd || only_data_sections)
20716 return true;
20717 }
20718
20719 /* Complain about various flag mismatches. */
20720 if (!elf32_arm_versions_compatible (EF_ARM_EABI_VERSION (in_flags),
20721 EF_ARM_EABI_VERSION (out_flags)))
20722 {
20723 _bfd_error_handler
20724 (_("error: source object %pB has EABI version %d, but target %pB has EABI version %d"),
20725 ibfd, (in_flags & EF_ARM_EABIMASK) >> 24,
20726 obfd, (out_flags & EF_ARM_EABIMASK) >> 24);
20727 return false;
20728 }
20729
20730 /* Not sure what needs to be checked for EABI versions >= 1. */
20731 /* VxWorks libraries do not use these flags. */
20732 if (get_elf_backend_data (obfd) != &elf32_arm_vxworks_bed
20733 && get_elf_backend_data (ibfd) != &elf32_arm_vxworks_bed
20734 && EF_ARM_EABI_VERSION (in_flags) == EF_ARM_EABI_UNKNOWN)
20735 {
20736 if ((in_flags & EF_ARM_APCS_26) != (out_flags & EF_ARM_APCS_26))
20737 {
20738 _bfd_error_handler
20739 (_("error: %pB is compiled for APCS-%d, whereas target %pB uses APCS-%d"),
20740 ibfd, in_flags & EF_ARM_APCS_26 ? 26 : 32,
20741 obfd, out_flags & EF_ARM_APCS_26 ? 26 : 32);
20742 flags_compatible = false;
20743 }
20744
20745 if ((in_flags & EF_ARM_APCS_FLOAT) != (out_flags & EF_ARM_APCS_FLOAT))
20746 {
20747 if (in_flags & EF_ARM_APCS_FLOAT)
20748 _bfd_error_handler
20749 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
20750 ibfd, obfd);
20751 else
20752 _bfd_error_handler
20753 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
20754 ibfd, obfd);
20755
20756 flags_compatible = false;
20757 }
20758
20759 if ((in_flags & EF_ARM_VFP_FLOAT) != (out_flags & EF_ARM_VFP_FLOAT))
20760 {
20761 if (in_flags & EF_ARM_VFP_FLOAT)
20762 _bfd_error_handler
20763 (_("error: %pB uses %s instructions, whereas %pB does not"),
20764 ibfd, "VFP", obfd);
20765 else
20766 _bfd_error_handler
20767 (_("error: %pB uses %s instructions, whereas %pB does not"),
20768 ibfd, "FPA", obfd);
20769
20770 flags_compatible = false;
20771 }
20772
20773 if ((in_flags & EF_ARM_MAVERICK_FLOAT) != (out_flags & EF_ARM_MAVERICK_FLOAT))
20774 {
20775 if (in_flags & EF_ARM_MAVERICK_FLOAT)
20776 _bfd_error_handler
20777 (_("error: %pB uses %s instructions, whereas %pB does not"),
20778 ibfd, "Maverick", obfd);
20779 else
20780 _bfd_error_handler
20781 (_("error: %pB does not use %s instructions, whereas %pB does"),
20782 ibfd, "Maverick", obfd);
20783
20784 flags_compatible = false;
20785 }
20786
20787 #ifdef EF_ARM_SOFT_FLOAT
20788 if ((in_flags & EF_ARM_SOFT_FLOAT) != (out_flags & EF_ARM_SOFT_FLOAT))
20789 {
20790 /* We can allow interworking between code that is VFP format
20791 layout, and uses either soft float or integer regs for
20792 passing floating point arguments and results. We already
20793 know that the APCS_FLOAT flags match; similarly for VFP
20794 flags. */
20795 if ((in_flags & EF_ARM_APCS_FLOAT) != 0
20796 || (in_flags & EF_ARM_VFP_FLOAT) == 0)
20797 {
20798 if (in_flags & EF_ARM_SOFT_FLOAT)
20799 _bfd_error_handler
20800 (_("error: %pB uses software FP, whereas %pB uses hardware FP"),
20801 ibfd, obfd);
20802 else
20803 _bfd_error_handler
20804 (_("error: %pB uses hardware FP, whereas %pB uses software FP"),
20805 ibfd, obfd);
20806
20807 flags_compatible = false;
20808 }
20809 }
20810 #endif
20811
20812 /* Interworking mismatch is only a warning. */
20813 if ((in_flags & EF_ARM_INTERWORK) != (out_flags & EF_ARM_INTERWORK))
20814 {
20815 if (in_flags & EF_ARM_INTERWORK)
20816 {
20817 _bfd_error_handler
20818 (_("warning: %pB supports interworking, whereas %pB does not"),
20819 ibfd, obfd);
20820 }
20821 else
20822 {
20823 _bfd_error_handler
20824 (_("warning: %pB does not support interworking, whereas %pB does"),
20825 ibfd, obfd);
20826 }
20827 }
20828 }
20829
20830 return flags_compatible;
20831 }