1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2022 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
58 typedef arelent, howto manager, Relocations, Relocations
63 This is the structure of a relocation entry:
67 .typedef enum bfd_reloc_status
69 . {* No errors detected. Note - the value 2 is used so that it
70 . will not be mistaken for the boolean TRUE or FALSE values. *}
73 . {* The relocation was performed, but there was an overflow. *}
76 . {* The address to relocate was not within the section supplied. *}
77 . bfd_reloc_outofrange,
79 . {* Used by special functions. *}
82 . {* Unsupported relocation size requested. *}
83 . bfd_reloc_notsupported,
85 . {* Target specific meaning. *}
88 . {* The symbol to relocate against was undefined. *}
89 . bfd_reloc_undefined,
91 . {* The relocation was performed, but may not be ok. If this type is
92 . returned, the error_message argument to bfd_perform_relocation
96 . bfd_reloc_status_type;
98 .typedef const struct reloc_howto_struct reloc_howto_type;
100 .typedef struct reloc_cache_entry
102 . {* A pointer into the canonical table of pointers. *}
103 . struct bfd_symbol **sym_ptr_ptr;
105 . {* offset in section. *}
106 . bfd_size_type address;
108 . {* addend for relocation value. *}
111 . {* Pointer to how to perform the required relocation. *}
112 . reloc_howto_type *howto;
122 Here is a description of each of the fields within an <<arelent>>:
126 The symbol table pointer points to a pointer to the symbol
127 associated with the relocation request. It is the pointer
128 into the table returned by the back end's
129 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
130 referenced through a pointer to a pointer so that tools like
131 the linker can fix up all the symbols of the same name by
132 modifying only one pointer. The relocation routine looks in
133 the symbol and uses the base of the section the symbol is
134 attached to and the value of the symbol as the initial
135 relocation offset. If the symbol pointer is zero, then the
136 section provided is looked up.
140 The <<address>> field gives the offset in bytes from the base of
141 the section data which owns the relocation record to the first
142 byte of relocatable information. The actual data relocated
143 will be relative to this point; for example, a relocation
144 type which modifies the bottom two bytes of a four byte word
145 would not touch the first byte pointed to in a big endian
150 The <<addend>> is a value provided by the back end to be added (!)
151 to the relocation offset. Its interpretation is dependent upon
152 the howto. For example, on the 68k the code:
157 | return foo[0x12345678];
160 Could be compiled into:
163 | moveb @@#12345678,d0
168 This could create a reloc pointing to <<foo>>, but leave the
169 offset in the data, something like:
171 |RELOCATION RECORDS FOR [.text]:
175 |00000000 4e56 fffc ; linkw fp,#-4
176 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
177 |0000000a 49c0 ; extbl d0
178 |0000000c 4e5e ; unlk fp
181 Using coff and an 88k, some instructions don't have enough
182 space in them to represent the full address range, and
183 pointers have to be loaded in two parts. So you'd get something like:
185 | or.u r13,r0,hi16(_foo+0x12345678)
186 | ld.b r2,r13,lo16(_foo+0x12345678)
189 This should create two relocs, both pointing to <<_foo>>, and with
190 0x12340000 in their addend field. The data would consist of:
192 |RELOCATION RECORDS FOR [.text]:
194 |00000002 HVRT16 _foo+0x12340000
195 |00000006 LVRT16 _foo+0x12340000
197 |00000000 5da05678 ; or.u r13,r0,0x5678
198 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
199 |00000008 f400c001 ; jmp r1
201 The relocation routine digs out the value from the data, adds
202 it to the addend to get the original offset, and then adds the
203 value of <<_foo>>. Note that all 32 bits have to be kept around
204 somewhere, to cope with carry from bit 15 to bit 16.
206 One further example is the sparc and the a.out format. The
207 sparc has a similar problem to the 88k, in that some
208 instructions don't have room for an entire offset, but on the
209 sparc the parts are created in odd sized lumps. The designers of
210 the a.out format chose to not use the data within the section
211 for storing part of the offset; all the offset is kept within
212 the reloc. Anything in the data should be ignored.
215 | sethi %hi(_foo+0x12345678),%g2
216 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
220 Both relocs contain a pointer to <<foo>>, and the offsets
223 |RELOCATION RECORDS FOR [.text]:
225 |00000004 HI22 _foo+0x12345678
226 |00000008 LO10 _foo+0x12345678
228 |00000000 9de3bf90 ; save %sp,-112,%sp
229 |00000004 05000000 ; sethi %hi(_foo+0),%g2
230 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
231 |0000000c 81c7e008 ; ret
232 |00000010 81e80000 ; restore
236 The <<howto>> field can be imagined as a
237 relocation instruction. It is a pointer to a structure which
238 contains information on what to do with all of the other
239 information in the reloc record and data section. A back end
240 would normally have a relocation instruction set and turn
241 relocations into pointers to the correct structure on input -
242 but it would be possible to create each howto field on demand.
248 <<enum complain_overflow>>
250 Indicates what sort of overflow checking should be done when
251 performing a relocation.
255 .enum complain_overflow
257 . {* Do not complain on overflow. *}
258 . complain_overflow_dont,
260 . {* Complain if the value overflows when considered as a signed
261 . number one bit larger than the field. ie. A bitfield of N bits
262 . is allowed to represent -2**n to 2**n-1. *}
263 . complain_overflow_bitfield,
265 . {* Complain if the value overflows when considered as a signed
267 . complain_overflow_signed,
269 . {* Complain if the value overflows when considered as an
270 . unsigned number. *}
271 . complain_overflow_unsigned
280 The <<reloc_howto_type>> is a structure which contains all the
281 information that libbfd needs to know to tie up a back end's data.
284 .struct reloc_howto_struct
286 . {* The type field has mainly a documentary use - the back end can
287 . do what it wants with it, though normally the back end's idea of
288 . an external reloc number is stored in this field. *}
291 . {* The size of the item to be relocated in bytes. *}
292 . unsigned int size:4;
294 . {* The number of bits in the field to be relocated. This is used
295 . when doing overflow checking. *}
296 . unsigned int bitsize:7;
298 . {* The value the final relocation is shifted right by. This drops
299 . unwanted data from the relocation. *}
300 . unsigned int rightshift:6;
302 . {* The bit position of the reloc value in the destination.
303 . The relocated value is left shifted by this amount. *}
304 . unsigned int bitpos:6;
306 . {* What type of overflow error should be checked for when
308 . ENUM_BITFIELD (complain_overflow) complain_on_overflow:2;
310 . {* The relocation value should be negated before applying. *}
311 . unsigned int negate:1;
313 . {* The relocation is relative to the item being relocated. *}
314 . unsigned int pc_relative:1;
316 . {* Some formats record a relocation addend in the section contents
317 . rather than with the relocation. For ELF formats this is the
318 . distinction between USE_REL and USE_RELA (though the code checks
319 . for USE_REL == 1/0). The value of this field is TRUE if the
320 . addend is recorded with the section contents; when performing a
321 . partial link (ld -r) the section contents (the data) will be
322 . modified. The value of this field is FALSE if addends are
323 . recorded with the relocation (in arelent.addend); when performing
324 . a partial link the relocation will be modified.
325 . All relocations for all ELF USE_RELA targets should set this field
326 . to FALSE (values of TRUE should be looked on with suspicion).
327 . However, the converse is not true: not all relocations of all ELF
328 . USE_REL targets set this field to TRUE. Why this is so is peculiar
329 . to each particular target. For relocs that aren't used in partial
330 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
331 . unsigned int partial_inplace:1;
333 . {* When some formats create PC relative instructions, they leave
334 . the value of the pc of the place being relocated in the offset
335 . slot of the instruction, so that a PC relative relocation can
336 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
337 . Some formats leave the displacement part of an instruction
338 . empty (e.g., ELF); this flag signals the fact. *}
339 . unsigned int pcrel_offset:1;
341 . {* src_mask selects the part of the instruction (or data) to be used
342 . in the relocation sum. If the target relocations don't have an
343 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
344 . dst_mask to extract the addend from the section contents. If
345 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
346 . field should normally be zero. Non-zero values for ELF USE_RELA
347 . targets should be viewed with suspicion as normally the value in
348 . the dst_mask part of the section contents should be ignored. *}
351 . {* dst_mask selects which parts of the instruction (or data) are
352 . replaced with a relocated value. *}
355 . {* If this field is non null, then the supplied function is
356 . called rather than the normal function. This allows really
357 . strange relocation methods to be accommodated. *}
358 . bfd_reloc_status_type (*special_function)
359 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
362 . {* The textual name of the relocation type. *}
373 The HOWTO macro fills in a reloc_howto_type (a typedef for
374 const struct reloc_howto_struct).
376 .#define HOWTO_RSIZE(sz) ((sz) < 0 ? -(sz) : (sz))
377 .#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \
378 . inplace, src_mask, dst_mask, pcrel_off) \
379 . { (unsigned) type, HOWTO_RSIZE (size), bits, right, left, ovf, \
380 . size < 0, pcrel, inplace, pcrel_off, src_mask, dst_mask, func, name }
383 This is used to fill in an empty howto entry in an array.
385 .#define EMPTY_HOWTO(C) \
386 . HOWTO ((C), 0, 1, 0, false, 0, complain_overflow_dont, NULL, \
387 . NULL, false, 0, 0, false)
389 .static inline unsigned int
390 .bfd_get_reloc_size (reloc_howto_type *howto)
392 . return howto->size;
403 How relocs are tied together in an <<asection>>:
405 .typedef struct relent_chain
408 . struct relent_chain *next;
414 /* N_ONES produces N one bits, without undefined behaviour for N
415 between zero and the number of bits in a bfd_vma. */
416 #define N_ONES(n) ((n) == 0 ? 0 : ((bfd_vma) 1 << ((n) - 1) << 1) - 1)
423 bfd_reloc_status_type bfd_check_overflow
424 (enum complain_overflow how,
425 unsigned int bitsize,
426 unsigned int rightshift,
427 unsigned int addrsize,
431 Perform overflow checking on @var{relocation} which has
432 @var{bitsize} significant bits and will be shifted right by
433 @var{rightshift} bits, on a machine with addresses containing
434 @var{addrsize} significant bits. The result is either of
435 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
439 bfd_reloc_status_type
440 bfd_check_overflow (enum complain_overflow how
,
441 unsigned int bitsize
,
442 unsigned int rightshift
,
443 unsigned int addrsize
,
446 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
447 bfd_reloc_status_type flag
= bfd_reloc_ok
;
452 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
453 we'll be permissive: extra bits in the field mask will
454 automatically extend the address mask for purposes of the
456 fieldmask
= N_ONES (bitsize
);
457 signmask
= ~fieldmask
;
458 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
459 a
= (relocation
& addrmask
) >> rightshift
;
463 case complain_overflow_dont
:
466 case complain_overflow_signed
:
467 /* If any sign bits are set, all sign bits must be set. That
468 is, A must be a valid negative address after shifting. */
469 signmask
= ~ (fieldmask
>> 1);
472 case complain_overflow_bitfield
:
473 /* Bitfields are sometimes signed, sometimes unsigned. We
474 explicitly allow an address wrap too, which means a bitfield
475 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
476 if the value has some, but not all, bits set outside the
479 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
480 flag
= bfd_reloc_overflow
;
483 case complain_overflow_unsigned
:
484 /* We have an overflow if the address does not fit in the field. */
485 if ((a
& signmask
) != 0)
486 flag
= bfd_reloc_overflow
;
498 bfd_reloc_offset_in_range
501 bool bfd_reloc_offset_in_range
502 (reloc_howto_type *howto,
505 bfd_size_type offset);
508 Returns TRUE if the reloc described by @var{HOWTO} can be
509 applied at @var{OFFSET} octets in @var{SECTION}.
513 /* HOWTO describes a relocation, at offset OCTET. Return whether the
514 relocation field is within SECTION of ABFD. */
517 bfd_reloc_offset_in_range (reloc_howto_type
*howto
,
522 bfd_size_type octet_end
= bfd_get_section_limit_octets (abfd
, section
);
523 bfd_size_type reloc_size
= bfd_get_reloc_size (howto
);
525 /* The reloc field must be contained entirely within the section.
526 Allow zero length fields (marker relocs or NONE relocs where no
527 relocation will be performed) at the end of the section. */
528 return octet
<= octet_end
&& reloc_size
<= octet_end
- octet
;
531 /* Read and return the section contents at DATA converted to a host
532 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
535 read_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
)
537 switch (bfd_get_reloc_size (howto
))
543 return bfd_get_8 (abfd
, data
);
546 return bfd_get_16 (abfd
, data
);
549 return bfd_get_24 (abfd
, data
);
552 return bfd_get_32 (abfd
, data
);
556 return bfd_get_64 (abfd
, data
);
565 /* Convert VAL to target format and write to DATA. The number of
566 bytes written is given by the HOWTO. */
569 write_reloc (bfd
*abfd
, bfd_vma val
, bfd_byte
*data
, reloc_howto_type
*howto
)
571 switch (bfd_get_reloc_size (howto
))
577 bfd_put_8 (abfd
, val
, data
);
581 bfd_put_16 (abfd
, val
, data
);
585 bfd_put_24 (abfd
, val
, data
);
589 bfd_put_32 (abfd
, val
, data
);
594 bfd_put_64 (abfd
, val
, data
);
603 /* Apply RELOCATION value to target bytes at DATA, according to
607 apply_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
,
610 bfd_vma val
= read_reloc (abfd
, data
, howto
);
613 relocation
= -relocation
;
615 val
= ((val
& ~howto
->dst_mask
)
616 | (((val
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
618 write_reloc (abfd
, val
, data
, howto
);
623 bfd_perform_relocation
626 bfd_reloc_status_type bfd_perform_relocation
628 arelent *reloc_entry,
630 asection *input_section,
632 char **error_message);
635 If @var{output_bfd} is supplied to this function, the
636 generated image will be relocatable; the relocations are
637 copied to the output file after they have been changed to
638 reflect the new state of the world. There are two ways of
639 reflecting the results of partial linkage in an output file:
640 by modifying the output data in place, and by modifying the
641 relocation record. Some native formats (e.g., basic a.out and
642 basic coff) have no way of specifying an addend in the
643 relocation type, so the addend has to go in the output data.
644 This is no big deal since in these formats the output data
645 slot will always be big enough for the addend. Complex reloc
646 types with addends were invented to solve just this problem.
647 The @var{error_message} argument is set to an error message if
648 this return @code{bfd_reloc_dangerous}.
652 bfd_reloc_status_type
653 bfd_perform_relocation (bfd
*abfd
,
654 arelent
*reloc_entry
,
656 asection
*input_section
,
658 char **error_message
)
661 bfd_reloc_status_type flag
= bfd_reloc_ok
;
662 bfd_size_type octets
;
663 bfd_vma output_base
= 0;
664 reloc_howto_type
*howto
= reloc_entry
->howto
;
665 asection
*reloc_target_output_section
;
668 symbol
= *(reloc_entry
->sym_ptr_ptr
);
670 /* If we are not producing relocatable output, return an error if
671 the symbol is not defined. An undefined weak symbol is
672 considered to have a value of zero (SVR4 ABI, p. 4-27). */
673 if (bfd_is_und_section (symbol
->section
)
674 && (symbol
->flags
& BSF_WEAK
) == 0
675 && output_bfd
== NULL
)
676 flag
= bfd_reloc_undefined
;
678 /* If there is a function supplied to handle this relocation type,
679 call it. It'll return `bfd_reloc_continue' if further processing
681 if (howto
&& howto
->special_function
)
683 bfd_reloc_status_type cont
;
685 /* Note - we do not call bfd_reloc_offset_in_range here as the
686 reloc_entry->address field might actually be valid for the
687 backend concerned. It is up to the special_function itself
688 to call bfd_reloc_offset_in_range if needed. */
689 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
690 input_section
, output_bfd
,
692 if (cont
!= bfd_reloc_continue
)
696 if (bfd_is_abs_section (symbol
->section
)
697 && output_bfd
!= NULL
)
699 reloc_entry
->address
+= input_section
->output_offset
;
703 /* PR 17512: file: 0f67f69d. */
705 return bfd_reloc_undefined
;
707 /* Is the address of the relocation really within the section? */
708 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
709 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
710 return bfd_reloc_outofrange
;
712 /* Work out which section the relocation is targeted at and the
713 initial relocation command value. */
715 /* Get symbol value. (Common symbols are special.) */
716 if (bfd_is_com_section (symbol
->section
))
719 relocation
= symbol
->value
;
721 reloc_target_output_section
= symbol
->section
->output_section
;
723 /* Convert input-section-relative symbol value to absolute. */
724 if ((output_bfd
&& ! howto
->partial_inplace
)
725 || reloc_target_output_section
== NULL
)
728 output_base
= reloc_target_output_section
->vma
;
730 output_base
+= symbol
->section
->output_offset
;
732 /* If symbol addresses are in octets, convert to bytes. */
733 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
734 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
735 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
737 relocation
+= output_base
;
739 /* Add in supplied addend. */
740 relocation
+= reloc_entry
->addend
;
742 /* Here the variable relocation holds the final address of the
743 symbol we are relocating against, plus any addend. */
745 if (howto
->pc_relative
)
747 /* This is a PC relative relocation. We want to set RELOCATION
748 to the distance between the address of the symbol and the
749 location. RELOCATION is already the address of the symbol.
751 We start by subtracting the address of the section containing
754 If pcrel_offset is set, we must further subtract the position
755 of the location within the section. Some targets arrange for
756 the addend to be the negative of the position of the location
757 within the section; for example, i386-aout does this. For
758 i386-aout, pcrel_offset is FALSE. Some other targets do not
759 include the position of the location; for example, ELF.
760 For those targets, pcrel_offset is TRUE.
762 If we are producing relocatable output, then we must ensure
763 that this reloc will be correctly computed when the final
764 relocation is done. If pcrel_offset is FALSE we want to wind
765 up with the negative of the location within the section,
766 which means we must adjust the existing addend by the change
767 in the location within the section. If pcrel_offset is TRUE
768 we do not want to adjust the existing addend at all.
770 FIXME: This seems logical to me, but for the case of
771 producing relocatable output it is not what the code
772 actually does. I don't want to change it, because it seems
773 far too likely that something will break. */
776 input_section
->output_section
->vma
+ input_section
->output_offset
;
778 if (howto
->pcrel_offset
)
779 relocation
-= reloc_entry
->address
;
782 if (output_bfd
!= NULL
)
784 if (! howto
->partial_inplace
)
786 /* This is a partial relocation, and we want to apply the relocation
787 to the reloc entry rather than the raw data. Modify the reloc
788 inplace to reflect what we now know. */
789 reloc_entry
->addend
= relocation
;
790 reloc_entry
->address
+= input_section
->output_offset
;
795 /* This is a partial relocation, but inplace, so modify the
798 If we've relocated with a symbol with a section, change
799 into a ref to the section belonging to the symbol. */
801 reloc_entry
->address
+= input_section
->output_offset
;
804 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
805 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
806 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
808 /* For m68k-coff, the addend was being subtracted twice during
809 relocation with -r. Removing the line below this comment
810 fixes that problem; see PR 2953.
812 However, Ian wrote the following, regarding removing the line below,
813 which explains why it is still enabled: --djm
815 If you put a patch like that into BFD you need to check all the COFF
816 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
817 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
818 problem in a different way. There may very well be a reason that the
819 code works as it does.
821 Hmmm. The first obvious point is that bfd_perform_relocation should
822 not have any tests that depend upon the flavour. It's seem like
823 entirely the wrong place for such a thing. The second obvious point
824 is that the current code ignores the reloc addend when producing
825 relocatable output for COFF. That's peculiar. In fact, I really
826 have no idea what the point of the line you want to remove is.
828 A typical COFF reloc subtracts the old value of the symbol and adds in
829 the new value to the location in the object file (if it's a pc
830 relative reloc it adds the difference between the symbol value and the
831 location). When relocating we need to preserve that property.
833 BFD handles this by setting the addend to the negative of the old
834 value of the symbol. Unfortunately it handles common symbols in a
835 non-standard way (it doesn't subtract the old value) but that's a
836 different story (we can't change it without losing backward
837 compatibility with old object files) (coff-i386 does subtract the old
838 value, to be compatible with existing coff-i386 targets, like SCO).
840 So everything works fine when not producing relocatable output. When
841 we are producing relocatable output, logically we should do exactly
842 what we do when not producing relocatable output. Therefore, your
843 patch is correct. In fact, it should probably always just set
844 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
845 add the value into the object file. This won't hurt the COFF code,
846 which doesn't use the addend; I'm not sure what it will do to other
847 formats (the thing to check for would be whether any formats both use
848 the addend and set partial_inplace).
850 When I wanted to make coff-i386 produce relocatable output, I ran
851 into the problem that you are running into: I wanted to remove that
852 line. Rather than risk it, I made the coff-i386 relocs use a special
853 function; it's coff_i386_reloc in coff-i386.c. The function
854 specifically adds the addend field into the object file, knowing that
855 bfd_perform_relocation is not going to. If you remove that line, then
856 coff-i386.c will wind up adding the addend field in twice. It's
857 trivial to fix; it just needs to be done.
859 The problem with removing the line is just that it may break some
860 working code. With BFD it's hard to be sure of anything. The right
861 way to deal with this is simply to build and test at least all the
862 supported COFF targets. It should be straightforward if time and disk
863 space consuming. For each target:
865 2) generate some executable, and link it using -r (I would
866 probably use paranoia.o and link against newlib/libc.a, which
867 for all the supported targets would be available in
868 /usr/cygnus/progressive/H-host/target/lib/libc.a).
869 3) make the change to reloc.c
870 4) rebuild the linker
872 6) if the resulting object files are the same, you have at least
874 7) if they are different you have to figure out which version is
877 relocation
-= reloc_entry
->addend
;
878 reloc_entry
->addend
= 0;
882 reloc_entry
->addend
= relocation
;
887 /* FIXME: This overflow checking is incomplete, because the value
888 might have overflowed before we get here. For a correct check we
889 need to compute the value in a size larger than bitsize, but we
890 can't reasonably do that for a reloc the same size as a host
892 FIXME: We should also do overflow checking on the result after
893 adding in the value contained in the object file. */
894 if (howto
->complain_on_overflow
!= complain_overflow_dont
895 && flag
== bfd_reloc_ok
)
896 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
899 bfd_arch_bits_per_address (abfd
),
902 /* Either we are relocating all the way, or we don't want to apply
903 the relocation to the reloc entry (probably because there isn't
904 any room in the output format to describe addends to relocs). */
906 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
907 (OSF version 1.3, compiler version 3.11). It miscompiles the
921 x <<= (unsigned long) s.i0;
925 printf ("succeeded (%lx)\n", x);
929 relocation
>>= (bfd_vma
) howto
->rightshift
;
931 /* Shift everything up to where it's going to be used. */
932 relocation
<<= (bfd_vma
) howto
->bitpos
;
934 /* Wait for the day when all have the mask in them. */
937 i instruction to be left alone
938 o offset within instruction
939 r relocation offset to apply
948 (( i i i i i o o o o o from bfd_get<size>
949 and S S S S S) to get the size offset we want
950 + r r r r r r r r r r) to get the final value to place
951 and D D D D D to chop to right size
952 -----------------------
955 ( i i i i i o o o o o from bfd_get<size>
956 and N N N N N ) get instruction
957 -----------------------
963 -----------------------
964 = R R R R R R R R R R put into bfd_put<size>
967 data
= (bfd_byte
*) data
+ octets
;
968 apply_reloc (abfd
, data
, howto
, relocation
);
974 bfd_install_relocation
977 bfd_reloc_status_type bfd_install_relocation
979 arelent *reloc_entry,
980 void *data, bfd_vma data_start,
981 asection *input_section,
982 char **error_message);
985 This looks remarkably like <<bfd_perform_relocation>>, except it
986 does not expect that the section contents have been filled in.
987 I.e., it's suitable for use when creating, rather than applying
990 For now, this function should be considered reserved for the
994 bfd_reloc_status_type
995 bfd_install_relocation (bfd
*abfd
,
996 arelent
*reloc_entry
,
998 bfd_vma data_start_offset
,
999 asection
*input_section
,
1000 char **error_message
)
1003 bfd_reloc_status_type flag
= bfd_reloc_ok
;
1004 bfd_size_type octets
;
1005 bfd_vma output_base
= 0;
1006 reloc_howto_type
*howto
= reloc_entry
->howto
;
1007 asection
*reloc_target_output_section
;
1011 symbol
= *(reloc_entry
->sym_ptr_ptr
);
1013 /* If there is a function supplied to handle this relocation type,
1014 call it. It'll return `bfd_reloc_continue' if further processing
1016 if (howto
&& howto
->special_function
)
1018 bfd_reloc_status_type cont
;
1020 /* Note - we do not call bfd_reloc_offset_in_range here as the
1021 reloc_entry->address field might actually be valid for the
1022 backend concerned. It is up to the special_function itself
1023 to call bfd_reloc_offset_in_range if needed. */
1024 /* XXX - The special_function calls haven't been fixed up to deal
1025 with creating new relocations and section contents. */
1026 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1027 /* XXX - Non-portable! */
1028 ((bfd_byte
*) data_start
1029 - data_start_offset
),
1030 input_section
, abfd
, error_message
);
1031 if (cont
!= bfd_reloc_continue
)
1035 if (bfd_is_abs_section (symbol
->section
))
1037 reloc_entry
->address
+= input_section
->output_offset
;
1038 return bfd_reloc_ok
;
1041 /* No need to check for howto != NULL if !bfd_is_abs_section as
1042 it will have been checked in `bfd_perform_relocation already'. */
1044 /* Is the address of the relocation really within the section? */
1045 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
1046 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
1047 return bfd_reloc_outofrange
;
1049 /* Work out which section the relocation is targeted at and the
1050 initial relocation command value. */
1052 /* Get symbol value. (Common symbols are special.) */
1053 if (bfd_is_com_section (symbol
->section
))
1056 relocation
= symbol
->value
;
1058 reloc_target_output_section
= symbol
->section
->output_section
;
1060 /* Convert input-section-relative symbol value to absolute. */
1061 if (! howto
->partial_inplace
)
1064 output_base
= reloc_target_output_section
->vma
;
1066 output_base
+= symbol
->section
->output_offset
;
1068 /* If symbol addresses are in octets, convert to bytes. */
1069 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
1070 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
1071 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
1073 relocation
+= output_base
;
1075 /* Add in supplied addend. */
1076 relocation
+= reloc_entry
->addend
;
1078 /* Here the variable relocation holds the final address of the
1079 symbol we are relocating against, plus any addend. */
1081 if (howto
->pc_relative
)
1083 /* This is a PC relative relocation. We want to set RELOCATION
1084 to the distance between the address of the symbol and the
1085 location. RELOCATION is already the address of the symbol.
1087 We start by subtracting the address of the section containing
1090 If pcrel_offset is set, we must further subtract the position
1091 of the location within the section. Some targets arrange for
1092 the addend to be the negative of the position of the location
1093 within the section; for example, i386-aout does this. For
1094 i386-aout, pcrel_offset is FALSE. Some other targets do not
1095 include the position of the location; for example, ELF.
1096 For those targets, pcrel_offset is TRUE.
1098 If we are producing relocatable output, then we must ensure
1099 that this reloc will be correctly computed when the final
1100 relocation is done. If pcrel_offset is FALSE we want to wind
1101 up with the negative of the location within the section,
1102 which means we must adjust the existing addend by the change
1103 in the location within the section. If pcrel_offset is TRUE
1104 we do not want to adjust the existing addend at all.
1106 FIXME: This seems logical to me, but for the case of
1107 producing relocatable output it is not what the code
1108 actually does. I don't want to change it, because it seems
1109 far too likely that something will break. */
1112 input_section
->output_section
->vma
+ input_section
->output_offset
;
1114 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1115 relocation
-= reloc_entry
->address
;
1118 if (! howto
->partial_inplace
)
1120 /* This is a partial relocation, and we want to apply the relocation
1121 to the reloc entry rather than the raw data. Modify the reloc
1122 inplace to reflect what we now know. */
1123 reloc_entry
->addend
= relocation
;
1124 reloc_entry
->address
+= input_section
->output_offset
;
1129 /* This is a partial relocation, but inplace, so modify the
1132 If we've relocated with a symbol with a section, change
1133 into a ref to the section belonging to the symbol. */
1134 reloc_entry
->address
+= input_section
->output_offset
;
1137 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1138 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1139 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1142 /* For m68k-coff, the addend was being subtracted twice during
1143 relocation with -r. Removing the line below this comment
1144 fixes that problem; see PR 2953.
1146 However, Ian wrote the following, regarding removing the line below,
1147 which explains why it is still enabled: --djm
1149 If you put a patch like that into BFD you need to check all the COFF
1150 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1151 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1152 problem in a different way. There may very well be a reason that the
1153 code works as it does.
1155 Hmmm. The first obvious point is that bfd_install_relocation should
1156 not have any tests that depend upon the flavour. It's seem like
1157 entirely the wrong place for such a thing. The second obvious point
1158 is that the current code ignores the reloc addend when producing
1159 relocatable output for COFF. That's peculiar. In fact, I really
1160 have no idea what the point of the line you want to remove is.
1162 A typical COFF reloc subtracts the old value of the symbol and adds in
1163 the new value to the location in the object file (if it's a pc
1164 relative reloc it adds the difference between the symbol value and the
1165 location). When relocating we need to preserve that property.
1167 BFD handles this by setting the addend to the negative of the old
1168 value of the symbol. Unfortunately it handles common symbols in a
1169 non-standard way (it doesn't subtract the old value) but that's a
1170 different story (we can't change it without losing backward
1171 compatibility with old object files) (coff-i386 does subtract the old
1172 value, to be compatible with existing coff-i386 targets, like SCO).
1174 So everything works fine when not producing relocatable output. When
1175 we are producing relocatable output, logically we should do exactly
1176 what we do when not producing relocatable output. Therefore, your
1177 patch is correct. In fact, it should probably always just set
1178 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1179 add the value into the object file. This won't hurt the COFF code,
1180 which doesn't use the addend; I'm not sure what it will do to other
1181 formats (the thing to check for would be whether any formats both use
1182 the addend and set partial_inplace).
1184 When I wanted to make coff-i386 produce relocatable output, I ran
1185 into the problem that you are running into: I wanted to remove that
1186 line. Rather than risk it, I made the coff-i386 relocs use a special
1187 function; it's coff_i386_reloc in coff-i386.c. The function
1188 specifically adds the addend field into the object file, knowing that
1189 bfd_install_relocation is not going to. If you remove that line, then
1190 coff-i386.c will wind up adding the addend field in twice. It's
1191 trivial to fix; it just needs to be done.
1193 The problem with removing the line is just that it may break some
1194 working code. With BFD it's hard to be sure of anything. The right
1195 way to deal with this is simply to build and test at least all the
1196 supported COFF targets. It should be straightforward if time and disk
1197 space consuming. For each target:
1199 2) generate some executable, and link it using -r (I would
1200 probably use paranoia.o and link against newlib/libc.a, which
1201 for all the supported targets would be available in
1202 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1203 3) make the change to reloc.c
1204 4) rebuild the linker
1206 6) if the resulting object files are the same, you have at least
1208 7) if they are different you have to figure out which version is
1210 relocation
-= reloc_entry
->addend
;
1211 /* FIXME: There should be no target specific code here... */
1212 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1213 reloc_entry
->addend
= 0;
1217 reloc_entry
->addend
= relocation
;
1221 /* FIXME: This overflow checking is incomplete, because the value
1222 might have overflowed before we get here. For a correct check we
1223 need to compute the value in a size larger than bitsize, but we
1224 can't reasonably do that for a reloc the same size as a host
1226 FIXME: We should also do overflow checking on the result after
1227 adding in the value contained in the object file. */
1228 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1229 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1232 bfd_arch_bits_per_address (abfd
),
1235 /* Either we are relocating all the way, or we don't want to apply
1236 the relocation to the reloc entry (probably because there isn't
1237 any room in the output format to describe addends to relocs). */
1239 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1240 (OSF version 1.3, compiler version 3.11). It miscompiles the
1254 x <<= (unsigned long) s.i0;
1256 printf ("failed\n");
1258 printf ("succeeded (%lx)\n", x);
1262 relocation
>>= (bfd_vma
) howto
->rightshift
;
1264 /* Shift everything up to where it's going to be used. */
1265 relocation
<<= (bfd_vma
) howto
->bitpos
;
1267 /* Wait for the day when all have the mask in them. */
1270 i instruction to be left alone
1271 o offset within instruction
1272 r relocation offset to apply
1281 (( i i i i i o o o o o from bfd_get<size>
1282 and S S S S S) to get the size offset we want
1283 + r r r r r r r r r r) to get the final value to place
1284 and D D D D D to chop to right size
1285 -----------------------
1288 ( i i i i i o o o o o from bfd_get<size>
1289 and N N N N N ) get instruction
1290 -----------------------
1296 -----------------------
1297 = R R R R R R R R R R put into bfd_put<size>
1300 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1301 apply_reloc (abfd
, data
, howto
, relocation
);
1305 /* This relocation routine is used by some of the backend linkers.
1306 They do not construct asymbol or arelent structures, so there is no
1307 reason for them to use bfd_perform_relocation. Also,
1308 bfd_perform_relocation is so hacked up it is easier to write a new
1309 function than to try to deal with it.
1311 This routine does a final relocation. Whether it is useful for a
1312 relocatable link depends upon how the object format defines
1315 FIXME: This routine ignores any special_function in the HOWTO,
1316 since the existing special_function values have been written for
1317 bfd_perform_relocation.
1319 HOWTO is the reloc howto information.
1320 INPUT_BFD is the BFD which the reloc applies to.
1321 INPUT_SECTION is the section which the reloc applies to.
1322 CONTENTS is the contents of the section.
1323 ADDRESS is the address of the reloc within INPUT_SECTION.
1324 VALUE is the value of the symbol the reloc refers to.
1325 ADDEND is the addend of the reloc. */
1327 bfd_reloc_status_type
1328 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1330 asection
*input_section
,
1337 bfd_size_type octets
= (address
1338 * bfd_octets_per_byte (input_bfd
, input_section
));
1340 /* Sanity check the address. */
1341 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, octets
))
1342 return bfd_reloc_outofrange
;
1344 /* This function assumes that we are dealing with a basic relocation
1345 against a symbol. We want to compute the value of the symbol to
1346 relocate to. This is just VALUE, the value of the symbol, plus
1347 ADDEND, any addend associated with the reloc. */
1348 relocation
= value
+ addend
;
1350 /* If the relocation is PC relative, we want to set RELOCATION to
1351 the distance between the symbol (currently in RELOCATION) and the
1352 location we are relocating. Some targets (e.g., i386-aout)
1353 arrange for the contents of the section to be the negative of the
1354 offset of the location within the section; for such targets
1355 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1356 the contents of the section as zero; for such targets
1357 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1358 subtract out the offset of the location within the section (which
1359 is just ADDRESS). */
1360 if (howto
->pc_relative
)
1362 relocation
-= (input_section
->output_section
->vma
1363 + input_section
->output_offset
);
1364 if (howto
->pcrel_offset
)
1365 relocation
-= address
;
1368 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1372 /* Relocate a given location using a given value and howto. */
1374 bfd_reloc_status_type
1375 _bfd_relocate_contents (reloc_howto_type
*howto
,
1381 bfd_reloc_status_type flag
;
1382 unsigned int rightshift
= howto
->rightshift
;
1383 unsigned int bitpos
= howto
->bitpos
;
1386 relocation
= -relocation
;
1388 /* Get the value we are going to relocate. */
1389 x
= read_reloc (input_bfd
, location
, howto
);
1391 /* Check for overflow. FIXME: We may drop bits during the addition
1392 which we don't check for. We must either check at every single
1393 operation, which would be tedious, or we must do the computations
1394 in a type larger than bfd_vma, which would be inefficient. */
1395 flag
= bfd_reloc_ok
;
1396 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1398 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1401 /* Get the values to be added together. For signed and unsigned
1402 relocations, we assume that all values should be truncated to
1403 the size of an address. For bitfields, all the bits matter.
1404 See also bfd_check_overflow. */
1405 fieldmask
= N_ONES (howto
->bitsize
);
1406 signmask
= ~fieldmask
;
1407 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1408 | (fieldmask
<< rightshift
));
1409 a
= (relocation
& addrmask
) >> rightshift
;
1410 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1411 addrmask
>>= rightshift
;
1413 switch (howto
->complain_on_overflow
)
1415 case complain_overflow_signed
:
1416 /* If any sign bits are set, all sign bits must be set.
1417 That is, A must be a valid negative address after
1419 signmask
= ~(fieldmask
>> 1);
1422 case complain_overflow_bitfield
:
1423 /* Much like the signed check, but for a field one bit
1424 wider. We allow a bitfield to represent numbers in the
1425 range -2**n to 2**n-1, where n is the number of bits in the
1426 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1427 can't overflow, which is exactly what we want. */
1429 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1430 flag
= bfd_reloc_overflow
;
1432 /* We only need this next bit of code if the sign bit of B
1433 is below the sign bit of A. This would only happen if
1434 SRC_MASK had fewer bits than BITSIZE. Note that if
1435 SRC_MASK has more bits than BITSIZE, we can get into
1436 trouble; we would need to verify that B is in range, as
1437 we do for A above. */
1438 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1441 /* Set all the bits above the sign bit. */
1444 /* Now we can do the addition. */
1447 /* See if the result has the correct sign. Bits above the
1448 sign bit are junk now; ignore them. If the sum is
1449 positive, make sure we did not have all negative inputs;
1450 if the sum is negative, make sure we did not have all
1451 positive inputs. The test below looks only at the sign
1452 bits, and it really just
1453 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1455 We mask with addrmask here to explicitly allow an address
1456 wrap-around. The Linux kernel relies on it, and it is
1457 the only way to write assembler code which can run when
1458 loaded at a location 0x80000000 away from the location at
1459 which it is linked. */
1460 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1461 flag
= bfd_reloc_overflow
;
1464 case complain_overflow_unsigned
:
1465 /* Checking for an unsigned overflow is relatively easy:
1466 trim the addresses and add, and trim the result as well.
1467 Overflow is normally indicated when the result does not
1468 fit in the field. However, we also need to consider the
1469 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1470 input is 0x80000000, and bfd_vma is only 32 bits; then we
1471 will get sum == 0, but there is an overflow, since the
1472 inputs did not fit in the field. Instead of doing a
1473 separate test, we can check for this by or-ing in the
1474 operands when testing for the sum overflowing its final
1476 sum
= (a
+ b
) & addrmask
;
1477 if ((a
| b
| sum
) & signmask
)
1478 flag
= bfd_reloc_overflow
;
1486 /* Put RELOCATION in the right bits. */
1487 relocation
>>= (bfd_vma
) rightshift
;
1488 relocation
<<= (bfd_vma
) bitpos
;
1490 /* Add RELOCATION to the right bits of X. */
1491 x
= ((x
& ~howto
->dst_mask
)
1492 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1494 /* Put the relocated value back in the object file. */
1495 write_reloc (input_bfd
, x
, location
, howto
);
1499 /* Clear a given location using a given howto, by applying a fixed relocation
1500 value and discarding any in-place addend. This is used for fixed-up
1501 relocations against discarded symbols, to make ignorable debug or unwind
1502 information more obvious. */
1504 bfd_reloc_status_type
1505 _bfd_clear_contents (reloc_howto_type
*howto
,
1507 asection
*input_section
,
1514 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, off
))
1515 return bfd_reloc_outofrange
;
1517 /* Get the value we are going to relocate. */
1518 location
= buf
+ off
;
1519 x
= read_reloc (input_bfd
, location
, howto
);
1521 /* Zero out the unwanted bits of X. */
1522 x
&= ~howto
->dst_mask
;
1524 /* For a range list, use 1 instead of 0 as placeholder. 0
1525 would terminate the list, hiding any later entries. */
1526 if (strcmp (bfd_section_name (input_section
), ".debug_ranges") == 0
1527 && (howto
->dst_mask
& 1) != 0)
1530 /* Put the relocated value back in the object file. */
1531 write_reloc (input_bfd
, x
, location
, howto
);
1532 return bfd_reloc_ok
;
1538 howto manager, , typedef arelent, Relocations
1543 When an application wants to create a relocation, but doesn't
1544 know what the target machine might call it, it can find out by
1545 using this bit of code.
1554 The insides of a reloc code. The idea is that, eventually, there
1555 will be one enumerator for every type of relocation we ever do.
1556 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1557 return a howto pointer.
1559 This does mean that the application must determine the correct
1560 enumerator value; you can't get a howto pointer from a random set
1581 Basic absolute relocations of N bits.
1596 PC-relative relocations. Sometimes these are relative to the address
1597 of the relocation itself; sometimes they are relative to the start of
1598 the section containing the relocation. It depends on the specific target.
1605 Section relative relocations. Some targets need this for DWARF2.
1608 BFD_RELOC_32_GOT_PCREL
1610 BFD_RELOC_16_GOT_PCREL
1612 BFD_RELOC_8_GOT_PCREL
1618 BFD_RELOC_LO16_GOTOFF
1620 BFD_RELOC_HI16_GOTOFF
1622 BFD_RELOC_HI16_S_GOTOFF
1626 BFD_RELOC_64_PLT_PCREL
1628 BFD_RELOC_32_PLT_PCREL
1630 BFD_RELOC_24_PLT_PCREL
1632 BFD_RELOC_16_PLT_PCREL
1634 BFD_RELOC_8_PLT_PCREL
1642 BFD_RELOC_LO16_PLTOFF
1644 BFD_RELOC_HI16_PLTOFF
1646 BFD_RELOC_HI16_S_PLTOFF
1660 BFD_RELOC_68K_GLOB_DAT
1662 BFD_RELOC_68K_JMP_SLOT
1664 BFD_RELOC_68K_RELATIVE
1666 BFD_RELOC_68K_TLS_GD32
1668 BFD_RELOC_68K_TLS_GD16
1670 BFD_RELOC_68K_TLS_GD8
1672 BFD_RELOC_68K_TLS_LDM32
1674 BFD_RELOC_68K_TLS_LDM16
1676 BFD_RELOC_68K_TLS_LDM8
1678 BFD_RELOC_68K_TLS_LDO32
1680 BFD_RELOC_68K_TLS_LDO16
1682 BFD_RELOC_68K_TLS_LDO8
1684 BFD_RELOC_68K_TLS_IE32
1686 BFD_RELOC_68K_TLS_IE16
1688 BFD_RELOC_68K_TLS_IE8
1690 BFD_RELOC_68K_TLS_LE32
1692 BFD_RELOC_68K_TLS_LE16
1694 BFD_RELOC_68K_TLS_LE8
1696 Relocations used by 68K ELF.
1699 BFD_RELOC_32_BASEREL
1701 BFD_RELOC_16_BASEREL
1703 BFD_RELOC_LO16_BASEREL
1705 BFD_RELOC_HI16_BASEREL
1707 BFD_RELOC_HI16_S_BASEREL
1713 Linkage-table relative.
1718 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1721 BFD_RELOC_32_PCREL_S2
1723 BFD_RELOC_16_PCREL_S2
1725 BFD_RELOC_23_PCREL_S2
1727 These PC-relative relocations are stored as word displacements --
1728 i.e., byte displacements shifted right two bits. The 30-bit word
1729 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1730 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1731 signed 16-bit displacement is used on the MIPS, and the 23-bit
1732 displacement is used on the Alpha.
1739 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1740 the target word. These are used on the SPARC.
1747 For systems that allocate a Global Pointer register, these are
1748 displacements off that register. These relocation types are
1749 handled specially, because the value the register will have is
1750 decided relatively late.
1755 BFD_RELOC_SPARC_WDISP22
1761 BFD_RELOC_SPARC_GOT10
1763 BFD_RELOC_SPARC_GOT13
1765 BFD_RELOC_SPARC_GOT22
1767 BFD_RELOC_SPARC_PC10
1769 BFD_RELOC_SPARC_PC22
1771 BFD_RELOC_SPARC_WPLT30
1773 BFD_RELOC_SPARC_COPY
1775 BFD_RELOC_SPARC_GLOB_DAT
1777 BFD_RELOC_SPARC_JMP_SLOT
1779 BFD_RELOC_SPARC_RELATIVE
1781 BFD_RELOC_SPARC_UA16
1783 BFD_RELOC_SPARC_UA32
1785 BFD_RELOC_SPARC_UA64
1787 BFD_RELOC_SPARC_GOTDATA_HIX22
1789 BFD_RELOC_SPARC_GOTDATA_LOX10
1791 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1793 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1795 BFD_RELOC_SPARC_GOTDATA_OP
1797 BFD_RELOC_SPARC_JMP_IREL
1799 BFD_RELOC_SPARC_IRELATIVE
1801 SPARC ELF relocations. There is probably some overlap with other
1802 relocation types already defined.
1805 BFD_RELOC_SPARC_BASE13
1807 BFD_RELOC_SPARC_BASE22
1809 I think these are specific to SPARC a.out (e.g., Sun 4).
1819 BFD_RELOC_SPARC_OLO10
1821 BFD_RELOC_SPARC_HH22
1823 BFD_RELOC_SPARC_HM10
1825 BFD_RELOC_SPARC_LM22
1827 BFD_RELOC_SPARC_PC_HH22
1829 BFD_RELOC_SPARC_PC_HM10
1831 BFD_RELOC_SPARC_PC_LM22
1833 BFD_RELOC_SPARC_WDISP16
1835 BFD_RELOC_SPARC_WDISP19
1843 BFD_RELOC_SPARC_DISP64
1846 BFD_RELOC_SPARC_PLT32
1848 BFD_RELOC_SPARC_PLT64
1850 BFD_RELOC_SPARC_HIX22
1852 BFD_RELOC_SPARC_LOX10
1860 BFD_RELOC_SPARC_REGISTER
1864 BFD_RELOC_SPARC_SIZE32
1866 BFD_RELOC_SPARC_SIZE64
1868 BFD_RELOC_SPARC_WDISP10
1873 BFD_RELOC_SPARC_REV32
1875 SPARC little endian relocation
1877 BFD_RELOC_SPARC_TLS_GD_HI22
1879 BFD_RELOC_SPARC_TLS_GD_LO10
1881 BFD_RELOC_SPARC_TLS_GD_ADD
1883 BFD_RELOC_SPARC_TLS_GD_CALL
1885 BFD_RELOC_SPARC_TLS_LDM_HI22
1887 BFD_RELOC_SPARC_TLS_LDM_LO10
1889 BFD_RELOC_SPARC_TLS_LDM_ADD
1891 BFD_RELOC_SPARC_TLS_LDM_CALL
1893 BFD_RELOC_SPARC_TLS_LDO_HIX22
1895 BFD_RELOC_SPARC_TLS_LDO_LOX10
1897 BFD_RELOC_SPARC_TLS_LDO_ADD
1899 BFD_RELOC_SPARC_TLS_IE_HI22
1901 BFD_RELOC_SPARC_TLS_IE_LO10
1903 BFD_RELOC_SPARC_TLS_IE_LD
1905 BFD_RELOC_SPARC_TLS_IE_LDX
1907 BFD_RELOC_SPARC_TLS_IE_ADD
1909 BFD_RELOC_SPARC_TLS_LE_HIX22
1911 BFD_RELOC_SPARC_TLS_LE_LOX10
1913 BFD_RELOC_SPARC_TLS_DTPMOD32
1915 BFD_RELOC_SPARC_TLS_DTPMOD64
1917 BFD_RELOC_SPARC_TLS_DTPOFF32
1919 BFD_RELOC_SPARC_TLS_DTPOFF64
1921 BFD_RELOC_SPARC_TLS_TPOFF32
1923 BFD_RELOC_SPARC_TLS_TPOFF64
1925 SPARC TLS relocations
1934 BFD_RELOC_SPU_IMM10W
1938 BFD_RELOC_SPU_IMM16W
1942 BFD_RELOC_SPU_PCREL9a
1944 BFD_RELOC_SPU_PCREL9b
1946 BFD_RELOC_SPU_PCREL16
1956 BFD_RELOC_SPU_ADD_PIC
1961 BFD_RELOC_ALPHA_GPDISP_HI16
1963 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
1964 "addend" in some special way.
1965 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
1966 writing; when reading, it will be the absolute section symbol. The
1967 addend is the displacement in bytes of the "lda" instruction from
1968 the "ldah" instruction (which is at the address of this reloc).
1970 BFD_RELOC_ALPHA_GPDISP_LO16
1972 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
1973 with GPDISP_HI16 relocs. The addend is ignored when writing the
1974 relocations out, and is filled in with the file's GP value on
1975 reading, for convenience.
1978 BFD_RELOC_ALPHA_GPDISP
1980 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
1981 relocation except that there is no accompanying GPDISP_LO16
1985 BFD_RELOC_ALPHA_LITERAL
1987 BFD_RELOC_ALPHA_ELF_LITERAL
1989 BFD_RELOC_ALPHA_LITUSE
1991 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
1992 the assembler turns it into a LDQ instruction to load the address of
1993 the symbol, and then fills in a register in the real instruction.
1995 The LITERAL reloc, at the LDQ instruction, refers to the .lita
1996 section symbol. The addend is ignored when writing, but is filled
1997 in with the file's GP value on reading, for convenience, as with the
2000 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2001 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2002 but it generates output not based on the position within the .got
2003 section, but relative to the GP value chosen for the file during the
2006 The LITUSE reloc, on the instruction using the loaded address, gives
2007 information to the linker that it might be able to use to optimize
2008 away some literal section references. The symbol is ignored (read
2009 as the absolute section symbol), and the "addend" indicates the type
2010 of instruction using the register:
2011 1 - "memory" fmt insn
2012 2 - byte-manipulation (byte offset reg)
2013 3 - jsr (target of branch)
2016 BFD_RELOC_ALPHA_HINT
2018 The HINT relocation indicates a value that should be filled into the
2019 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2020 prediction logic which may be provided on some processors.
2023 BFD_RELOC_ALPHA_LINKAGE
2025 The LINKAGE relocation outputs a linkage pair in the object file,
2026 which is filled by the linker.
2029 BFD_RELOC_ALPHA_CODEADDR
2031 The CODEADDR relocation outputs a STO_CA in the object file,
2032 which is filled by the linker.
2035 BFD_RELOC_ALPHA_GPREL_HI16
2037 BFD_RELOC_ALPHA_GPREL_LO16
2039 The GPREL_HI/LO relocations together form a 32-bit offset from the
2043 BFD_RELOC_ALPHA_BRSGP
2045 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2046 share a common GP, and the target address is adjusted for
2047 STO_ALPHA_STD_GPLOAD.
2052 The NOP relocation outputs a NOP if the longword displacement
2053 between two procedure entry points is < 2^21.
2058 The BSR relocation outputs a BSR if the longword displacement
2059 between two procedure entry points is < 2^21.
2064 The LDA relocation outputs a LDA if the longword displacement
2065 between two procedure entry points is < 2^16.
2070 The BOH relocation outputs a BSR if the longword displacement
2071 between two procedure entry points is < 2^21, or else a hint.
2074 BFD_RELOC_ALPHA_TLSGD
2076 BFD_RELOC_ALPHA_TLSLDM
2078 BFD_RELOC_ALPHA_DTPMOD64
2080 BFD_RELOC_ALPHA_GOTDTPREL16
2082 BFD_RELOC_ALPHA_DTPREL64
2084 BFD_RELOC_ALPHA_DTPREL_HI16
2086 BFD_RELOC_ALPHA_DTPREL_LO16
2088 BFD_RELOC_ALPHA_DTPREL16
2090 BFD_RELOC_ALPHA_GOTTPREL16
2092 BFD_RELOC_ALPHA_TPREL64
2094 BFD_RELOC_ALPHA_TPREL_HI16
2096 BFD_RELOC_ALPHA_TPREL_LO16
2098 BFD_RELOC_ALPHA_TPREL16
2100 Alpha thread-local storage relocations.
2105 BFD_RELOC_MICROMIPS_JMP
2107 The MIPS jump instruction.
2110 BFD_RELOC_MIPS16_JMP
2112 The MIPS16 jump instruction.
2115 BFD_RELOC_MIPS16_GPREL
2117 MIPS16 GP relative reloc.
2122 High 16 bits of 32-bit value; simple reloc.
2127 High 16 bits of 32-bit value but the low 16 bits will be sign
2128 extended and added to form the final result. If the low 16
2129 bits form a negative number, we need to add one to the high value
2130 to compensate for the borrow when the low bits are added.
2138 BFD_RELOC_HI16_PCREL
2140 High 16 bits of 32-bit pc-relative value
2142 BFD_RELOC_HI16_S_PCREL
2144 High 16 bits of 32-bit pc-relative value, adjusted
2146 BFD_RELOC_LO16_PCREL
2148 Low 16 bits of pc-relative value
2151 BFD_RELOC_MIPS16_GOT16
2153 BFD_RELOC_MIPS16_CALL16
2155 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2156 16-bit immediate fields
2158 BFD_RELOC_MIPS16_HI16
2160 MIPS16 high 16 bits of 32-bit value.
2162 BFD_RELOC_MIPS16_HI16_S
2164 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2165 extended and added to form the final result. If the low 16
2166 bits form a negative number, we need to add one to the high value
2167 to compensate for the borrow when the low bits are added.
2169 BFD_RELOC_MIPS16_LO16
2174 BFD_RELOC_MIPS16_TLS_GD
2176 BFD_RELOC_MIPS16_TLS_LDM
2178 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2180 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2182 BFD_RELOC_MIPS16_TLS_GOTTPREL
2184 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2186 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2188 MIPS16 TLS relocations
2191 BFD_RELOC_MIPS_LITERAL
2193 BFD_RELOC_MICROMIPS_LITERAL
2195 Relocation against a MIPS literal section.
2198 BFD_RELOC_MICROMIPS_7_PCREL_S1
2200 BFD_RELOC_MICROMIPS_10_PCREL_S1
2202 BFD_RELOC_MICROMIPS_16_PCREL_S1
2204 microMIPS PC-relative relocations.
2207 BFD_RELOC_MIPS16_16_PCREL_S1
2209 MIPS16 PC-relative relocation.
2212 BFD_RELOC_MIPS_21_PCREL_S2
2214 BFD_RELOC_MIPS_26_PCREL_S2
2216 BFD_RELOC_MIPS_18_PCREL_S3
2218 BFD_RELOC_MIPS_19_PCREL_S2
2220 MIPS PC-relative relocations.
2223 BFD_RELOC_MICROMIPS_GPREL16
2225 BFD_RELOC_MICROMIPS_HI16
2227 BFD_RELOC_MICROMIPS_HI16_S
2229 BFD_RELOC_MICROMIPS_LO16
2231 microMIPS versions of generic BFD relocs.
2234 BFD_RELOC_MIPS_GOT16
2236 BFD_RELOC_MICROMIPS_GOT16
2238 BFD_RELOC_MIPS_CALL16
2240 BFD_RELOC_MICROMIPS_CALL16
2242 BFD_RELOC_MIPS_GOT_HI16
2244 BFD_RELOC_MICROMIPS_GOT_HI16
2246 BFD_RELOC_MIPS_GOT_LO16
2248 BFD_RELOC_MICROMIPS_GOT_LO16
2250 BFD_RELOC_MIPS_CALL_HI16
2252 BFD_RELOC_MICROMIPS_CALL_HI16
2254 BFD_RELOC_MIPS_CALL_LO16
2256 BFD_RELOC_MICROMIPS_CALL_LO16
2260 BFD_RELOC_MICROMIPS_SUB
2262 BFD_RELOC_MIPS_GOT_PAGE
2264 BFD_RELOC_MICROMIPS_GOT_PAGE
2266 BFD_RELOC_MIPS_GOT_OFST
2268 BFD_RELOC_MICROMIPS_GOT_OFST
2270 BFD_RELOC_MIPS_GOT_DISP
2272 BFD_RELOC_MICROMIPS_GOT_DISP
2274 BFD_RELOC_MIPS_SHIFT5
2276 BFD_RELOC_MIPS_SHIFT6
2278 BFD_RELOC_MIPS_INSERT_A
2280 BFD_RELOC_MIPS_INSERT_B
2282 BFD_RELOC_MIPS_DELETE
2284 BFD_RELOC_MIPS_HIGHEST
2286 BFD_RELOC_MICROMIPS_HIGHEST
2288 BFD_RELOC_MIPS_HIGHER
2290 BFD_RELOC_MICROMIPS_HIGHER
2292 BFD_RELOC_MIPS_SCN_DISP
2294 BFD_RELOC_MICROMIPS_SCN_DISP
2298 BFD_RELOC_MIPS_RELGOT
2302 BFD_RELOC_MICROMIPS_JALR
2304 BFD_RELOC_MIPS_TLS_DTPMOD32
2306 BFD_RELOC_MIPS_TLS_DTPREL32
2308 BFD_RELOC_MIPS_TLS_DTPMOD64
2310 BFD_RELOC_MIPS_TLS_DTPREL64
2312 BFD_RELOC_MIPS_TLS_GD
2314 BFD_RELOC_MICROMIPS_TLS_GD
2316 BFD_RELOC_MIPS_TLS_LDM
2318 BFD_RELOC_MICROMIPS_TLS_LDM
2320 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2322 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2324 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2326 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2328 BFD_RELOC_MIPS_TLS_GOTTPREL
2330 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2332 BFD_RELOC_MIPS_TLS_TPREL32
2334 BFD_RELOC_MIPS_TLS_TPREL64
2336 BFD_RELOC_MIPS_TLS_TPREL_HI16
2338 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2340 BFD_RELOC_MIPS_TLS_TPREL_LO16
2342 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2346 MIPS ELF relocations.
2352 BFD_RELOC_MIPS_JUMP_SLOT
2354 MIPS ELF relocations (VxWorks and PLT extensions).
2358 BFD_RELOC_MOXIE_10_PCREL
2360 Moxie ELF relocations.
2372 BFD_RELOC_FT32_RELAX
2380 BFD_RELOC_FT32_DIFF32
2382 FT32 ELF relocations.
2386 BFD_RELOC_FRV_LABEL16
2388 BFD_RELOC_FRV_LABEL24
2394 BFD_RELOC_FRV_GPREL12
2396 BFD_RELOC_FRV_GPRELU12
2398 BFD_RELOC_FRV_GPREL32
2400 BFD_RELOC_FRV_GPRELHI
2402 BFD_RELOC_FRV_GPRELLO
2410 BFD_RELOC_FRV_FUNCDESC
2412 BFD_RELOC_FRV_FUNCDESC_GOT12
2414 BFD_RELOC_FRV_FUNCDESC_GOTHI
2416 BFD_RELOC_FRV_FUNCDESC_GOTLO
2418 BFD_RELOC_FRV_FUNCDESC_VALUE
2420 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2422 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2424 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2426 BFD_RELOC_FRV_GOTOFF12
2428 BFD_RELOC_FRV_GOTOFFHI
2430 BFD_RELOC_FRV_GOTOFFLO
2432 BFD_RELOC_FRV_GETTLSOFF
2434 BFD_RELOC_FRV_TLSDESC_VALUE
2436 BFD_RELOC_FRV_GOTTLSDESC12
2438 BFD_RELOC_FRV_GOTTLSDESCHI
2440 BFD_RELOC_FRV_GOTTLSDESCLO
2442 BFD_RELOC_FRV_TLSMOFF12
2444 BFD_RELOC_FRV_TLSMOFFHI
2446 BFD_RELOC_FRV_TLSMOFFLO
2448 BFD_RELOC_FRV_GOTTLSOFF12
2450 BFD_RELOC_FRV_GOTTLSOFFHI
2452 BFD_RELOC_FRV_GOTTLSOFFLO
2454 BFD_RELOC_FRV_TLSOFF
2456 BFD_RELOC_FRV_TLSDESC_RELAX
2458 BFD_RELOC_FRV_GETTLSOFF_RELAX
2460 BFD_RELOC_FRV_TLSOFF_RELAX
2462 BFD_RELOC_FRV_TLSMOFF
2464 Fujitsu Frv Relocations.
2468 BFD_RELOC_MN10300_GOTOFF24
2470 This is a 24bit GOT-relative reloc for the mn10300.
2472 BFD_RELOC_MN10300_GOT32
2474 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2477 BFD_RELOC_MN10300_GOT24
2479 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2482 BFD_RELOC_MN10300_GOT16
2484 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2487 BFD_RELOC_MN10300_COPY
2489 Copy symbol at runtime.
2491 BFD_RELOC_MN10300_GLOB_DAT
2495 BFD_RELOC_MN10300_JMP_SLOT
2499 BFD_RELOC_MN10300_RELATIVE
2501 Adjust by program base.
2503 BFD_RELOC_MN10300_SYM_DIFF
2505 Together with another reloc targeted at the same location,
2506 allows for a value that is the difference of two symbols
2507 in the same section.
2509 BFD_RELOC_MN10300_ALIGN
2511 The addend of this reloc is an alignment power that must
2512 be honoured at the offset's location, regardless of linker
2515 BFD_RELOC_MN10300_TLS_GD
2517 BFD_RELOC_MN10300_TLS_LD
2519 BFD_RELOC_MN10300_TLS_LDO
2521 BFD_RELOC_MN10300_TLS_GOTIE
2523 BFD_RELOC_MN10300_TLS_IE
2525 BFD_RELOC_MN10300_TLS_LE
2527 BFD_RELOC_MN10300_TLS_DTPMOD
2529 BFD_RELOC_MN10300_TLS_DTPOFF
2531 BFD_RELOC_MN10300_TLS_TPOFF
2533 Various TLS-related relocations.
2535 BFD_RELOC_MN10300_32_PCREL
2537 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2540 BFD_RELOC_MN10300_16_PCREL
2542 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2553 BFD_RELOC_386_GLOB_DAT
2555 BFD_RELOC_386_JUMP_SLOT
2557 BFD_RELOC_386_RELATIVE
2559 BFD_RELOC_386_GOTOFF
2563 BFD_RELOC_386_TLS_TPOFF
2565 BFD_RELOC_386_TLS_IE
2567 BFD_RELOC_386_TLS_GOTIE
2569 BFD_RELOC_386_TLS_LE
2571 BFD_RELOC_386_TLS_GD
2573 BFD_RELOC_386_TLS_LDM
2575 BFD_RELOC_386_TLS_LDO_32
2577 BFD_RELOC_386_TLS_IE_32
2579 BFD_RELOC_386_TLS_LE_32
2581 BFD_RELOC_386_TLS_DTPMOD32
2583 BFD_RELOC_386_TLS_DTPOFF32
2585 BFD_RELOC_386_TLS_TPOFF32
2587 BFD_RELOC_386_TLS_GOTDESC
2589 BFD_RELOC_386_TLS_DESC_CALL
2591 BFD_RELOC_386_TLS_DESC
2593 BFD_RELOC_386_IRELATIVE
2595 BFD_RELOC_386_GOT32X
2597 i386/elf relocations
2600 BFD_RELOC_X86_64_GOT32
2602 BFD_RELOC_X86_64_PLT32
2604 BFD_RELOC_X86_64_COPY
2606 BFD_RELOC_X86_64_GLOB_DAT
2608 BFD_RELOC_X86_64_JUMP_SLOT
2610 BFD_RELOC_X86_64_RELATIVE
2612 BFD_RELOC_X86_64_GOTPCREL
2614 BFD_RELOC_X86_64_32S
2616 BFD_RELOC_X86_64_DTPMOD64
2618 BFD_RELOC_X86_64_DTPOFF64
2620 BFD_RELOC_X86_64_TPOFF64
2622 BFD_RELOC_X86_64_TLSGD
2624 BFD_RELOC_X86_64_TLSLD
2626 BFD_RELOC_X86_64_DTPOFF32
2628 BFD_RELOC_X86_64_GOTTPOFF
2630 BFD_RELOC_X86_64_TPOFF32
2632 BFD_RELOC_X86_64_GOTOFF64
2634 BFD_RELOC_X86_64_GOTPC32
2636 BFD_RELOC_X86_64_GOT64
2638 BFD_RELOC_X86_64_GOTPCREL64
2640 BFD_RELOC_X86_64_GOTPC64
2642 BFD_RELOC_X86_64_GOTPLT64
2644 BFD_RELOC_X86_64_PLTOFF64
2646 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2648 BFD_RELOC_X86_64_TLSDESC_CALL
2650 BFD_RELOC_X86_64_TLSDESC
2652 BFD_RELOC_X86_64_IRELATIVE
2654 BFD_RELOC_X86_64_PC32_BND
2656 BFD_RELOC_X86_64_PLT32_BND
2658 BFD_RELOC_X86_64_GOTPCRELX
2660 BFD_RELOC_X86_64_REX_GOTPCRELX
2662 x86-64/elf relocations
2665 BFD_RELOC_NS32K_IMM_8
2667 BFD_RELOC_NS32K_IMM_16
2669 BFD_RELOC_NS32K_IMM_32
2671 BFD_RELOC_NS32K_IMM_8_PCREL
2673 BFD_RELOC_NS32K_IMM_16_PCREL
2675 BFD_RELOC_NS32K_IMM_32_PCREL
2677 BFD_RELOC_NS32K_DISP_8
2679 BFD_RELOC_NS32K_DISP_16
2681 BFD_RELOC_NS32K_DISP_32
2683 BFD_RELOC_NS32K_DISP_8_PCREL
2685 BFD_RELOC_NS32K_DISP_16_PCREL
2687 BFD_RELOC_NS32K_DISP_32_PCREL
2692 BFD_RELOC_PDP11_DISP_8_PCREL
2694 BFD_RELOC_PDP11_DISP_6_PCREL
2699 BFD_RELOC_PJ_CODE_HI16
2701 BFD_RELOC_PJ_CODE_LO16
2703 BFD_RELOC_PJ_CODE_DIR16
2705 BFD_RELOC_PJ_CODE_DIR32
2707 BFD_RELOC_PJ_CODE_REL16
2709 BFD_RELOC_PJ_CODE_REL32
2711 Picojava relocs. Not all of these appear in object files.
2720 BFD_RELOC_PPC_TOC16_LO
2722 BFD_RELOC_PPC_TOC16_HI
2726 BFD_RELOC_PPC_B16_BRTAKEN
2728 BFD_RELOC_PPC_B16_BRNTAKEN
2732 BFD_RELOC_PPC_BA16_BRTAKEN
2734 BFD_RELOC_PPC_BA16_BRNTAKEN
2738 BFD_RELOC_PPC_GLOB_DAT
2740 BFD_RELOC_PPC_JMP_SLOT
2742 BFD_RELOC_PPC_RELATIVE
2744 BFD_RELOC_PPC_LOCAL24PC
2746 BFD_RELOC_PPC_EMB_NADDR32
2748 BFD_RELOC_PPC_EMB_NADDR16
2750 BFD_RELOC_PPC_EMB_NADDR16_LO
2752 BFD_RELOC_PPC_EMB_NADDR16_HI
2754 BFD_RELOC_PPC_EMB_NADDR16_HA
2756 BFD_RELOC_PPC_EMB_SDAI16
2758 BFD_RELOC_PPC_EMB_SDA2I16
2760 BFD_RELOC_PPC_EMB_SDA2REL
2762 BFD_RELOC_PPC_EMB_SDA21
2764 BFD_RELOC_PPC_EMB_MRKREF
2766 BFD_RELOC_PPC_EMB_RELSEC16
2768 BFD_RELOC_PPC_EMB_RELST_LO
2770 BFD_RELOC_PPC_EMB_RELST_HI
2772 BFD_RELOC_PPC_EMB_RELST_HA
2774 BFD_RELOC_PPC_EMB_BIT_FLD
2776 BFD_RELOC_PPC_EMB_RELSDA
2778 BFD_RELOC_PPC_VLE_REL8
2780 BFD_RELOC_PPC_VLE_REL15
2782 BFD_RELOC_PPC_VLE_REL24
2784 BFD_RELOC_PPC_VLE_LO16A
2786 BFD_RELOC_PPC_VLE_LO16D
2788 BFD_RELOC_PPC_VLE_HI16A
2790 BFD_RELOC_PPC_VLE_HI16D
2792 BFD_RELOC_PPC_VLE_HA16A
2794 BFD_RELOC_PPC_VLE_HA16D
2796 BFD_RELOC_PPC_VLE_SDA21
2798 BFD_RELOC_PPC_VLE_SDA21_LO
2800 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2802 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2804 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2806 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2808 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2810 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2812 BFD_RELOC_PPC_16DX_HA
2814 BFD_RELOC_PPC_REL16DX_HA
2818 BFD_RELOC_PPC64_HIGHER
2820 BFD_RELOC_PPC64_HIGHER_S
2822 BFD_RELOC_PPC64_HIGHEST
2824 BFD_RELOC_PPC64_HIGHEST_S
2826 BFD_RELOC_PPC64_TOC16_LO
2828 BFD_RELOC_PPC64_TOC16_HI
2830 BFD_RELOC_PPC64_TOC16_HA
2834 BFD_RELOC_PPC64_PLTGOT16
2836 BFD_RELOC_PPC64_PLTGOT16_LO
2838 BFD_RELOC_PPC64_PLTGOT16_HI
2840 BFD_RELOC_PPC64_PLTGOT16_HA
2842 BFD_RELOC_PPC64_ADDR16_DS
2844 BFD_RELOC_PPC64_ADDR16_LO_DS
2846 BFD_RELOC_PPC64_GOT16_DS
2848 BFD_RELOC_PPC64_GOT16_LO_DS
2850 BFD_RELOC_PPC64_PLT16_LO_DS
2852 BFD_RELOC_PPC64_SECTOFF_DS
2854 BFD_RELOC_PPC64_SECTOFF_LO_DS
2856 BFD_RELOC_PPC64_TOC16_DS
2858 BFD_RELOC_PPC64_TOC16_LO_DS
2860 BFD_RELOC_PPC64_PLTGOT16_DS
2862 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2864 BFD_RELOC_PPC64_ADDR16_HIGH
2866 BFD_RELOC_PPC64_ADDR16_HIGHA
2868 BFD_RELOC_PPC64_REL16_HIGH
2870 BFD_RELOC_PPC64_REL16_HIGHA
2872 BFD_RELOC_PPC64_REL16_HIGHER
2874 BFD_RELOC_PPC64_REL16_HIGHERA
2876 BFD_RELOC_PPC64_REL16_HIGHEST
2878 BFD_RELOC_PPC64_REL16_HIGHESTA
2880 BFD_RELOC_PPC64_ADDR64_LOCAL
2882 BFD_RELOC_PPC64_ENTRY
2884 BFD_RELOC_PPC64_REL24_NOTOC
2886 BFD_RELOC_PPC64_REL24_P9NOTOC
2890 BFD_RELOC_PPC64_D34_LO
2892 BFD_RELOC_PPC64_D34_HI30
2894 BFD_RELOC_PPC64_D34_HA30
2896 BFD_RELOC_PPC64_PCREL34
2898 BFD_RELOC_PPC64_GOT_PCREL34
2900 BFD_RELOC_PPC64_PLT_PCREL34
2902 BFD_RELOC_PPC64_ADDR16_HIGHER34
2904 BFD_RELOC_PPC64_ADDR16_HIGHERA34
2906 BFD_RELOC_PPC64_ADDR16_HIGHEST34
2908 BFD_RELOC_PPC64_ADDR16_HIGHESTA34
2910 BFD_RELOC_PPC64_REL16_HIGHER34
2912 BFD_RELOC_PPC64_REL16_HIGHERA34
2914 BFD_RELOC_PPC64_REL16_HIGHEST34
2916 BFD_RELOC_PPC64_REL16_HIGHESTA34
2920 BFD_RELOC_PPC64_PCREL28
2922 Power(rs6000) and PowerPC relocations.
2939 BFD_RELOC_PPC_DTPMOD
2941 BFD_RELOC_PPC_TPREL16
2943 BFD_RELOC_PPC_TPREL16_LO
2945 BFD_RELOC_PPC_TPREL16_HI
2947 BFD_RELOC_PPC_TPREL16_HA
2951 BFD_RELOC_PPC_DTPREL16
2953 BFD_RELOC_PPC_DTPREL16_LO
2955 BFD_RELOC_PPC_DTPREL16_HI
2957 BFD_RELOC_PPC_DTPREL16_HA
2959 BFD_RELOC_PPC_DTPREL
2961 BFD_RELOC_PPC_GOT_TLSGD16
2963 BFD_RELOC_PPC_GOT_TLSGD16_LO
2965 BFD_RELOC_PPC_GOT_TLSGD16_HI
2967 BFD_RELOC_PPC_GOT_TLSGD16_HA
2969 BFD_RELOC_PPC_GOT_TLSLD16
2971 BFD_RELOC_PPC_GOT_TLSLD16_LO
2973 BFD_RELOC_PPC_GOT_TLSLD16_HI
2975 BFD_RELOC_PPC_GOT_TLSLD16_HA
2977 BFD_RELOC_PPC_GOT_TPREL16
2979 BFD_RELOC_PPC_GOT_TPREL16_LO
2981 BFD_RELOC_PPC_GOT_TPREL16_HI
2983 BFD_RELOC_PPC_GOT_TPREL16_HA
2985 BFD_RELOC_PPC_GOT_DTPREL16
2987 BFD_RELOC_PPC_GOT_DTPREL16_LO
2989 BFD_RELOC_PPC_GOT_DTPREL16_HI
2991 BFD_RELOC_PPC_GOT_DTPREL16_HA
2993 BFD_RELOC_PPC64_TLSGD
2995 BFD_RELOC_PPC64_TLSLD
2997 BFD_RELOC_PPC64_TLSLE
2999 BFD_RELOC_PPC64_TLSIE
3001 BFD_RELOC_PPC64_TLSM
3003 BFD_RELOC_PPC64_TLSML
3005 BFD_RELOC_PPC64_TPREL16_DS
3007 BFD_RELOC_PPC64_TPREL16_LO_DS
3009 BFD_RELOC_PPC64_TPREL16_HIGH
3011 BFD_RELOC_PPC64_TPREL16_HIGHA
3013 BFD_RELOC_PPC64_TPREL16_HIGHER
3015 BFD_RELOC_PPC64_TPREL16_HIGHERA
3017 BFD_RELOC_PPC64_TPREL16_HIGHEST
3019 BFD_RELOC_PPC64_TPREL16_HIGHESTA
3021 BFD_RELOC_PPC64_DTPREL16_DS
3023 BFD_RELOC_PPC64_DTPREL16_LO_DS
3025 BFD_RELOC_PPC64_DTPREL16_HIGH
3027 BFD_RELOC_PPC64_DTPREL16_HIGHA
3029 BFD_RELOC_PPC64_DTPREL16_HIGHER
3031 BFD_RELOC_PPC64_DTPREL16_HIGHERA
3033 BFD_RELOC_PPC64_DTPREL16_HIGHEST
3035 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
3037 BFD_RELOC_PPC64_TPREL34
3039 BFD_RELOC_PPC64_DTPREL34
3041 BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
3043 BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
3045 BFD_RELOC_PPC64_GOT_TPREL_PCREL34
3047 BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
3049 BFD_RELOC_PPC64_TLS_PCREL
3051 PowerPC and PowerPC64 thread-local storage relocations.
3056 IBM 370/390 relocations
3061 The type of reloc used to build a constructor table - at the moment
3062 probably a 32 bit wide absolute relocation, but the target can choose.
3063 It generally does map to one of the other relocation types.
3066 BFD_RELOC_ARM_PCREL_BRANCH
3068 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3069 not stored in the instruction.
3071 BFD_RELOC_ARM_PCREL_BLX
3073 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3074 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3075 field in the instruction.
3077 BFD_RELOC_THUMB_PCREL_BLX
3079 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3080 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3081 field in the instruction.
3083 BFD_RELOC_ARM_PCREL_CALL
3085 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3087 BFD_RELOC_ARM_PCREL_JUMP
3089 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3092 BFD_RELOC_THUMB_PCREL_BRANCH5
3094 ARM 5-bit pc-relative branch for Branch Future instructions.
3097 BFD_RELOC_THUMB_PCREL_BFCSEL
3099 ARM 6-bit pc-relative branch for BFCSEL instruction.
3102 BFD_RELOC_ARM_THUMB_BF17
3104 ARM 17-bit pc-relative branch for Branch Future instructions.
3107 BFD_RELOC_ARM_THUMB_BF13
3109 ARM 13-bit pc-relative branch for BFCSEL instruction.
3112 BFD_RELOC_ARM_THUMB_BF19
3114 ARM 19-bit pc-relative branch for Branch Future Link instruction.
3117 BFD_RELOC_ARM_THUMB_LOOP12
3119 ARM 12-bit pc-relative branch for Low Overhead Loop instructions.
3122 BFD_RELOC_THUMB_PCREL_BRANCH7
3124 BFD_RELOC_THUMB_PCREL_BRANCH9
3126 BFD_RELOC_THUMB_PCREL_BRANCH12
3128 BFD_RELOC_THUMB_PCREL_BRANCH20
3130 BFD_RELOC_THUMB_PCREL_BRANCH23
3132 BFD_RELOC_THUMB_PCREL_BRANCH25
3134 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3135 The lowest bit must be zero and is not stored in the instruction.
3136 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3137 "nn" one smaller in all cases. Note further that BRANCH23
3138 corresponds to R_ARM_THM_CALL.
3141 BFD_RELOC_ARM_OFFSET_IMM
3143 12-bit immediate offset, used in ARM-format ldr and str instructions.
3146 BFD_RELOC_ARM_THUMB_OFFSET
3148 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3151 BFD_RELOC_ARM_TARGET1
3153 Pc-relative or absolute relocation depending on target. Used for
3154 entries in .init_array sections.
3156 BFD_RELOC_ARM_ROSEGREL32
3158 Read-only segment base relative address.
3160 BFD_RELOC_ARM_SBREL32
3162 Data segment base relative address.
3164 BFD_RELOC_ARM_TARGET2
3166 This reloc is used for references to RTTI data from exception handling
3167 tables. The actual definition depends on the target. It may be a
3168 pc-relative or some form of GOT-indirect relocation.
3170 BFD_RELOC_ARM_PREL31
3172 31-bit PC relative address.
3178 BFD_RELOC_ARM_MOVW_PCREL
3180 BFD_RELOC_ARM_MOVT_PCREL
3182 BFD_RELOC_ARM_THUMB_MOVW
3184 BFD_RELOC_ARM_THUMB_MOVT
3186 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3188 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3190 Low and High halfword relocations for MOVW and MOVT instructions.
3193 BFD_RELOC_ARM_GOTFUNCDESC
3195 BFD_RELOC_ARM_GOTOFFFUNCDESC
3197 BFD_RELOC_ARM_FUNCDESC
3199 BFD_RELOC_ARM_FUNCDESC_VALUE
3201 BFD_RELOC_ARM_TLS_GD32_FDPIC
3203 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3205 BFD_RELOC_ARM_TLS_IE32_FDPIC
3207 ARM FDPIC specific relocations.
3210 BFD_RELOC_ARM_JUMP_SLOT
3212 BFD_RELOC_ARM_GLOB_DAT
3218 BFD_RELOC_ARM_RELATIVE
3220 BFD_RELOC_ARM_GOTOFF
3224 BFD_RELOC_ARM_GOT_PREL
3226 Relocations for setting up GOTs and PLTs for shared libraries.
3229 BFD_RELOC_ARM_TLS_GD32
3231 BFD_RELOC_ARM_TLS_LDO32
3233 BFD_RELOC_ARM_TLS_LDM32
3235 BFD_RELOC_ARM_TLS_DTPOFF32
3237 BFD_RELOC_ARM_TLS_DTPMOD32
3239 BFD_RELOC_ARM_TLS_TPOFF32
3241 BFD_RELOC_ARM_TLS_IE32
3243 BFD_RELOC_ARM_TLS_LE32
3245 BFD_RELOC_ARM_TLS_GOTDESC
3247 BFD_RELOC_ARM_TLS_CALL
3249 BFD_RELOC_ARM_THM_TLS_CALL
3251 BFD_RELOC_ARM_TLS_DESCSEQ
3253 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3255 BFD_RELOC_ARM_TLS_DESC
3257 ARM thread-local storage relocations.
3260 BFD_RELOC_ARM_ALU_PC_G0_NC
3262 BFD_RELOC_ARM_ALU_PC_G0
3264 BFD_RELOC_ARM_ALU_PC_G1_NC
3266 BFD_RELOC_ARM_ALU_PC_G1
3268 BFD_RELOC_ARM_ALU_PC_G2
3270 BFD_RELOC_ARM_LDR_PC_G0
3272 BFD_RELOC_ARM_LDR_PC_G1
3274 BFD_RELOC_ARM_LDR_PC_G2
3276 BFD_RELOC_ARM_LDRS_PC_G0
3278 BFD_RELOC_ARM_LDRS_PC_G1
3280 BFD_RELOC_ARM_LDRS_PC_G2
3282 BFD_RELOC_ARM_LDC_PC_G0
3284 BFD_RELOC_ARM_LDC_PC_G1
3286 BFD_RELOC_ARM_LDC_PC_G2
3288 BFD_RELOC_ARM_ALU_SB_G0_NC
3290 BFD_RELOC_ARM_ALU_SB_G0
3292 BFD_RELOC_ARM_ALU_SB_G1_NC
3294 BFD_RELOC_ARM_ALU_SB_G1
3296 BFD_RELOC_ARM_ALU_SB_G2
3298 BFD_RELOC_ARM_LDR_SB_G0
3300 BFD_RELOC_ARM_LDR_SB_G1
3302 BFD_RELOC_ARM_LDR_SB_G2
3304 BFD_RELOC_ARM_LDRS_SB_G0
3306 BFD_RELOC_ARM_LDRS_SB_G1
3308 BFD_RELOC_ARM_LDRS_SB_G2
3310 BFD_RELOC_ARM_LDC_SB_G0
3312 BFD_RELOC_ARM_LDC_SB_G1
3314 BFD_RELOC_ARM_LDC_SB_G2
3316 ARM group relocations.
3321 Annotation of BX instructions.
3324 BFD_RELOC_ARM_IRELATIVE
3326 ARM support for STT_GNU_IFUNC.
3329 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3331 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3333 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3335 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3337 Thumb1 relocations to support execute-only code.
3340 BFD_RELOC_ARM_IMMEDIATE
3342 BFD_RELOC_ARM_ADRL_IMMEDIATE
3344 BFD_RELOC_ARM_T32_IMMEDIATE
3346 BFD_RELOC_ARM_T32_ADD_IMM
3348 BFD_RELOC_ARM_T32_IMM12
3350 BFD_RELOC_ARM_T32_ADD_PC12
3352 BFD_RELOC_ARM_SHIFT_IMM
3362 BFD_RELOC_ARM_CP_OFF_IMM
3364 BFD_RELOC_ARM_CP_OFF_IMM_S2
3366 BFD_RELOC_ARM_T32_CP_OFF_IMM
3368 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3370 BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
3372 BFD_RELOC_ARM_ADR_IMM
3374 BFD_RELOC_ARM_LDR_IMM
3376 BFD_RELOC_ARM_LITERAL
3378 BFD_RELOC_ARM_IN_POOL
3380 BFD_RELOC_ARM_OFFSET_IMM8
3382 BFD_RELOC_ARM_T32_OFFSET_U8
3384 BFD_RELOC_ARM_T32_OFFSET_IMM
3386 BFD_RELOC_ARM_HWLITERAL
3388 BFD_RELOC_ARM_THUMB_ADD
3390 BFD_RELOC_ARM_THUMB_IMM
3392 BFD_RELOC_ARM_THUMB_SHIFT
3394 These relocs are only used within the ARM assembler. They are not
3395 (at present) written to any object files.
3398 BFD_RELOC_SH_PCDISP8BY2
3400 BFD_RELOC_SH_PCDISP12BY2
3408 BFD_RELOC_SH_DISP12BY2
3410 BFD_RELOC_SH_DISP12BY4
3412 BFD_RELOC_SH_DISP12BY8
3416 BFD_RELOC_SH_DISP20BY8
3420 BFD_RELOC_SH_IMM4BY2
3422 BFD_RELOC_SH_IMM4BY4
3426 BFD_RELOC_SH_IMM8BY2
3428 BFD_RELOC_SH_IMM8BY4
3430 BFD_RELOC_SH_PCRELIMM8BY2
3432 BFD_RELOC_SH_PCRELIMM8BY4
3434 BFD_RELOC_SH_SWITCH16
3436 BFD_RELOC_SH_SWITCH32
3450 BFD_RELOC_SH_LOOP_START
3452 BFD_RELOC_SH_LOOP_END
3456 BFD_RELOC_SH_GLOB_DAT
3458 BFD_RELOC_SH_JMP_SLOT
3460 BFD_RELOC_SH_RELATIVE
3464 BFD_RELOC_SH_GOT_LOW16
3466 BFD_RELOC_SH_GOT_MEDLOW16
3468 BFD_RELOC_SH_GOT_MEDHI16
3470 BFD_RELOC_SH_GOT_HI16
3472 BFD_RELOC_SH_GOTPLT_LOW16
3474 BFD_RELOC_SH_GOTPLT_MEDLOW16
3476 BFD_RELOC_SH_GOTPLT_MEDHI16
3478 BFD_RELOC_SH_GOTPLT_HI16
3480 BFD_RELOC_SH_PLT_LOW16
3482 BFD_RELOC_SH_PLT_MEDLOW16
3484 BFD_RELOC_SH_PLT_MEDHI16
3486 BFD_RELOC_SH_PLT_HI16
3488 BFD_RELOC_SH_GOTOFF_LOW16
3490 BFD_RELOC_SH_GOTOFF_MEDLOW16
3492 BFD_RELOC_SH_GOTOFF_MEDHI16
3494 BFD_RELOC_SH_GOTOFF_HI16
3496 BFD_RELOC_SH_GOTPC_LOW16
3498 BFD_RELOC_SH_GOTPC_MEDLOW16
3500 BFD_RELOC_SH_GOTPC_MEDHI16
3502 BFD_RELOC_SH_GOTPC_HI16
3506 BFD_RELOC_SH_GLOB_DAT64
3508 BFD_RELOC_SH_JMP_SLOT64
3510 BFD_RELOC_SH_RELATIVE64
3512 BFD_RELOC_SH_GOT10BY4
3514 BFD_RELOC_SH_GOT10BY8
3516 BFD_RELOC_SH_GOTPLT10BY4
3518 BFD_RELOC_SH_GOTPLT10BY8
3520 BFD_RELOC_SH_GOTPLT32
3522 BFD_RELOC_SH_SHMEDIA_CODE
3528 BFD_RELOC_SH_IMMS6BY32
3534 BFD_RELOC_SH_IMMS10BY2
3536 BFD_RELOC_SH_IMMS10BY4
3538 BFD_RELOC_SH_IMMS10BY8
3544 BFD_RELOC_SH_IMM_LOW16
3546 BFD_RELOC_SH_IMM_LOW16_PCREL
3548 BFD_RELOC_SH_IMM_MEDLOW16
3550 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3552 BFD_RELOC_SH_IMM_MEDHI16
3554 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3556 BFD_RELOC_SH_IMM_HI16
3558 BFD_RELOC_SH_IMM_HI16_PCREL
3562 BFD_RELOC_SH_TLS_GD_32
3564 BFD_RELOC_SH_TLS_LD_32
3566 BFD_RELOC_SH_TLS_LDO_32
3568 BFD_RELOC_SH_TLS_IE_32
3570 BFD_RELOC_SH_TLS_LE_32
3572 BFD_RELOC_SH_TLS_DTPMOD32
3574 BFD_RELOC_SH_TLS_DTPOFF32
3576 BFD_RELOC_SH_TLS_TPOFF32
3580 BFD_RELOC_SH_GOTOFF20
3582 BFD_RELOC_SH_GOTFUNCDESC
3584 BFD_RELOC_SH_GOTFUNCDESC20
3586 BFD_RELOC_SH_GOTOFFFUNCDESC
3588 BFD_RELOC_SH_GOTOFFFUNCDESC20
3590 BFD_RELOC_SH_FUNCDESC
3592 Renesas / SuperH SH relocs. Not all of these appear in object files.
3615 BFD_RELOC_ARC_SECTOFF
3617 BFD_RELOC_ARC_S21H_PCREL
3619 BFD_RELOC_ARC_S21W_PCREL
3621 BFD_RELOC_ARC_S25H_PCREL
3623 BFD_RELOC_ARC_S25W_PCREL
3627 BFD_RELOC_ARC_SDA_LDST
3629 BFD_RELOC_ARC_SDA_LDST1
3631 BFD_RELOC_ARC_SDA_LDST2
3633 BFD_RELOC_ARC_SDA16_LD
3635 BFD_RELOC_ARC_SDA16_LD1
3637 BFD_RELOC_ARC_SDA16_LD2
3639 BFD_RELOC_ARC_S13_PCREL
3645 BFD_RELOC_ARC_32_ME_S
3647 BFD_RELOC_ARC_N32_ME
3649 BFD_RELOC_ARC_SECTOFF_ME
3651 BFD_RELOC_ARC_SDA32_ME
3655 BFD_RELOC_AC_SECTOFF_U8
3657 BFD_RELOC_AC_SECTOFF_U8_1
3659 BFD_RELOC_AC_SECTOFF_U8_2
3661 BFD_RELOC_AC_SECTOFF_S9
3663 BFD_RELOC_AC_SECTOFF_S9_1
3665 BFD_RELOC_AC_SECTOFF_S9_2
3667 BFD_RELOC_ARC_SECTOFF_ME_1
3669 BFD_RELOC_ARC_SECTOFF_ME_2
3671 BFD_RELOC_ARC_SECTOFF_1
3673 BFD_RELOC_ARC_SECTOFF_2
3675 BFD_RELOC_ARC_SDA_12
3677 BFD_RELOC_ARC_SDA16_ST2
3679 BFD_RELOC_ARC_32_PCREL
3685 BFD_RELOC_ARC_GOTPC32
3691 BFD_RELOC_ARC_GLOB_DAT
3693 BFD_RELOC_ARC_JMP_SLOT
3695 BFD_RELOC_ARC_RELATIVE
3697 BFD_RELOC_ARC_GOTOFF
3701 BFD_RELOC_ARC_S21W_PCREL_PLT
3703 BFD_RELOC_ARC_S25H_PCREL_PLT
3705 BFD_RELOC_ARC_TLS_DTPMOD
3707 BFD_RELOC_ARC_TLS_TPOFF
3709 BFD_RELOC_ARC_TLS_GD_GOT
3711 BFD_RELOC_ARC_TLS_GD_LD
3713 BFD_RELOC_ARC_TLS_GD_CALL
3715 BFD_RELOC_ARC_TLS_IE_GOT
3717 BFD_RELOC_ARC_TLS_DTPOFF
3719 BFD_RELOC_ARC_TLS_DTPOFF_S9
3721 BFD_RELOC_ARC_TLS_LE_S9
3723 BFD_RELOC_ARC_TLS_LE_32
3725 BFD_RELOC_ARC_S25W_PCREL_PLT
3727 BFD_RELOC_ARC_S21H_PCREL_PLT
3729 BFD_RELOC_ARC_NPS_CMEM16
3731 BFD_RELOC_ARC_JLI_SECTOFF
3736 BFD_RELOC_BFIN_16_IMM
3738 ADI Blackfin 16 bit immediate absolute reloc.
3740 BFD_RELOC_BFIN_16_HIGH
3742 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3744 BFD_RELOC_BFIN_4_PCREL
3746 ADI Blackfin 'a' part of LSETUP.
3748 BFD_RELOC_BFIN_5_PCREL
3752 BFD_RELOC_BFIN_16_LOW
3754 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3756 BFD_RELOC_BFIN_10_PCREL
3760 BFD_RELOC_BFIN_11_PCREL
3762 ADI Blackfin 'b' part of LSETUP.
3764 BFD_RELOC_BFIN_12_PCREL_JUMP
3768 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3770 ADI Blackfin Short jump, pcrel.
3772 BFD_RELOC_BFIN_24_PCREL_CALL_X
3774 ADI Blackfin Call.x not implemented.
3776 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3778 ADI Blackfin Long Jump pcrel.
3780 BFD_RELOC_BFIN_GOT17M4
3782 BFD_RELOC_BFIN_GOTHI
3784 BFD_RELOC_BFIN_GOTLO
3786 BFD_RELOC_BFIN_FUNCDESC
3788 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3790 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3792 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3794 BFD_RELOC_BFIN_FUNCDESC_VALUE
3796 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3798 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3800 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3802 BFD_RELOC_BFIN_GOTOFF17M4
3804 BFD_RELOC_BFIN_GOTOFFHI
3806 BFD_RELOC_BFIN_GOTOFFLO
3808 ADI Blackfin FD-PIC relocations.
3812 ADI Blackfin GOT relocation.
3814 BFD_RELOC_BFIN_PLTPC
3816 ADI Blackfin PLTPC relocation.
3818 BFD_ARELOC_BFIN_PUSH
3820 ADI Blackfin arithmetic relocation.
3822 BFD_ARELOC_BFIN_CONST
3824 ADI Blackfin arithmetic relocation.
3828 ADI Blackfin arithmetic relocation.
3832 ADI Blackfin arithmetic relocation.
3834 BFD_ARELOC_BFIN_MULT
3836 ADI Blackfin arithmetic relocation.
3840 ADI Blackfin arithmetic relocation.
3844 ADI Blackfin arithmetic relocation.
3846 BFD_ARELOC_BFIN_LSHIFT
3848 ADI Blackfin arithmetic relocation.
3850 BFD_ARELOC_BFIN_RSHIFT
3852 ADI Blackfin arithmetic relocation.
3856 ADI Blackfin arithmetic relocation.
3860 ADI Blackfin arithmetic relocation.
3864 ADI Blackfin arithmetic relocation.
3866 BFD_ARELOC_BFIN_LAND
3868 ADI Blackfin arithmetic relocation.
3872 ADI Blackfin arithmetic relocation.
3876 ADI Blackfin arithmetic relocation.
3880 ADI Blackfin arithmetic relocation.
3882 BFD_ARELOC_BFIN_COMP
3884 ADI Blackfin arithmetic relocation.
3886 BFD_ARELOC_BFIN_PAGE
3888 ADI Blackfin arithmetic relocation.
3890 BFD_ARELOC_BFIN_HWPAGE
3892 ADI Blackfin arithmetic relocation.
3894 BFD_ARELOC_BFIN_ADDR
3896 ADI Blackfin arithmetic relocation.
3899 BFD_RELOC_D10V_10_PCREL_R
3901 Mitsubishi D10V relocs.
3902 This is a 10-bit reloc with the right 2 bits
3905 BFD_RELOC_D10V_10_PCREL_L
3907 Mitsubishi D10V relocs.
3908 This is a 10-bit reloc with the right 2 bits
3909 assumed to be 0. This is the same as the previous reloc
3910 except it is in the left container, i.e.,
3911 shifted left 15 bits.
3915 This is an 18-bit reloc with the right 2 bits
3918 BFD_RELOC_D10V_18_PCREL
3920 This is an 18-bit reloc with the right 2 bits
3926 Mitsubishi D30V relocs.
3927 This is a 6-bit absolute reloc.
3929 BFD_RELOC_D30V_9_PCREL
3931 This is a 6-bit pc-relative reloc with
3932 the right 3 bits assumed to be 0.
3934 BFD_RELOC_D30V_9_PCREL_R
3936 This is a 6-bit pc-relative reloc with
3937 the right 3 bits assumed to be 0. Same
3938 as the previous reloc but on the right side
3943 This is a 12-bit absolute reloc with the
3944 right 3 bitsassumed to be 0.
3946 BFD_RELOC_D30V_15_PCREL
3948 This is a 12-bit pc-relative reloc with
3949 the right 3 bits assumed to be 0.
3951 BFD_RELOC_D30V_15_PCREL_R
3953 This is a 12-bit pc-relative reloc with
3954 the right 3 bits assumed to be 0. Same
3955 as the previous reloc but on the right side
3960 This is an 18-bit absolute reloc with
3961 the right 3 bits assumed to be 0.
3963 BFD_RELOC_D30V_21_PCREL
3965 This is an 18-bit pc-relative reloc with
3966 the right 3 bits assumed to be 0.
3968 BFD_RELOC_D30V_21_PCREL_R
3970 This is an 18-bit pc-relative reloc with
3971 the right 3 bits assumed to be 0. Same
3972 as the previous reloc but on the right side
3977 This is a 32-bit absolute reloc.
3979 BFD_RELOC_D30V_32_PCREL
3981 This is a 32-bit pc-relative reloc.
3984 BFD_RELOC_DLX_HI16_S
3999 BFD_RELOC_M32C_RL_JUMP
4001 BFD_RELOC_M32C_RL_1ADDR
4003 BFD_RELOC_M32C_RL_2ADDR
4005 Renesas M16C/M32C Relocations.
4010 Renesas M32R (formerly Mitsubishi M32R) relocs.
4011 This is a 24 bit absolute address.
4013 BFD_RELOC_M32R_10_PCREL
4015 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
4017 BFD_RELOC_M32R_18_PCREL
4019 This is an 18-bit reloc with the right 2 bits assumed to be 0.
4021 BFD_RELOC_M32R_26_PCREL
4023 This is a 26-bit reloc with the right 2 bits assumed to be 0.
4025 BFD_RELOC_M32R_HI16_ULO
4027 This is a 16-bit reloc containing the high 16 bits of an address
4028 used when the lower 16 bits are treated as unsigned.
4030 BFD_RELOC_M32R_HI16_SLO
4032 This is a 16-bit reloc containing the high 16 bits of an address
4033 used when the lower 16 bits are treated as signed.
4037 This is a 16-bit reloc containing the lower 16 bits of an address.
4039 BFD_RELOC_M32R_SDA16
4041 This is a 16-bit reloc containing the small data area offset for use in
4042 add3, load, and store instructions.
4044 BFD_RELOC_M32R_GOT24
4046 BFD_RELOC_M32R_26_PLTREL
4050 BFD_RELOC_M32R_GLOB_DAT
4052 BFD_RELOC_M32R_JMP_SLOT
4054 BFD_RELOC_M32R_RELATIVE
4056 BFD_RELOC_M32R_GOTOFF
4058 BFD_RELOC_M32R_GOTOFF_HI_ULO
4060 BFD_RELOC_M32R_GOTOFF_HI_SLO
4062 BFD_RELOC_M32R_GOTOFF_LO
4064 BFD_RELOC_M32R_GOTPC24
4066 BFD_RELOC_M32R_GOT16_HI_ULO
4068 BFD_RELOC_M32R_GOT16_HI_SLO
4070 BFD_RELOC_M32R_GOT16_LO
4072 BFD_RELOC_M32R_GOTPC_HI_ULO
4074 BFD_RELOC_M32R_GOTPC_HI_SLO
4076 BFD_RELOC_M32R_GOTPC_LO
4085 This is a 20 bit absolute address.
4087 BFD_RELOC_NDS32_9_PCREL
4089 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4091 BFD_RELOC_NDS32_WORD_9_PCREL
4093 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
4095 BFD_RELOC_NDS32_15_PCREL
4097 This is an 15-bit reloc with the right 1 bit assumed to be 0.
4099 BFD_RELOC_NDS32_17_PCREL
4101 This is an 17-bit reloc with the right 1 bit assumed to be 0.
4103 BFD_RELOC_NDS32_25_PCREL
4105 This is a 25-bit reloc with the right 1 bit assumed to be 0.
4107 BFD_RELOC_NDS32_HI20
4109 This is a 20-bit reloc containing the high 20 bits of an address
4110 used with the lower 12 bits
4112 BFD_RELOC_NDS32_LO12S3
4114 This is a 12-bit reloc containing the lower 12 bits of an address
4115 then shift right by 3. This is used with ldi,sdi...
4117 BFD_RELOC_NDS32_LO12S2
4119 This is a 12-bit reloc containing the lower 12 bits of an address
4120 then shift left by 2. This is used with lwi,swi...
4122 BFD_RELOC_NDS32_LO12S1
4124 This is a 12-bit reloc containing the lower 12 bits of an address
4125 then shift left by 1. This is used with lhi,shi...
4127 BFD_RELOC_NDS32_LO12S0
4129 This is a 12-bit reloc containing the lower 12 bits of an address
4130 then shift left by 0. This is used with lbisbi...
4132 BFD_RELOC_NDS32_LO12S0_ORI
4134 This is a 12-bit reloc containing the lower 12 bits of an address
4135 then shift left by 0. This is only used with branch relaxations
4137 BFD_RELOC_NDS32_SDA15S3
4139 This is a 15-bit reloc containing the small data area 18-bit signed offset
4140 and shift left by 3 for use in ldi, sdi...
4142 BFD_RELOC_NDS32_SDA15S2
4144 This is a 15-bit reloc containing the small data area 17-bit signed offset
4145 and shift left by 2 for use in lwi, swi...
4147 BFD_RELOC_NDS32_SDA15S1
4149 This is a 15-bit reloc containing the small data area 16-bit signed offset
4150 and shift left by 1 for use in lhi, shi...
4152 BFD_RELOC_NDS32_SDA15S0
4154 This is a 15-bit reloc containing the small data area 15-bit signed offset
4155 and shift left by 0 for use in lbi, sbi...
4157 BFD_RELOC_NDS32_SDA16S3
4159 This is a 16-bit reloc containing the small data area 16-bit signed offset
4162 BFD_RELOC_NDS32_SDA17S2
4164 This is a 17-bit reloc containing the small data area 17-bit signed offset
4165 and shift left by 2 for use in lwi.gp, swi.gp...
4167 BFD_RELOC_NDS32_SDA18S1
4169 This is a 18-bit reloc containing the small data area 18-bit signed offset
4170 and shift left by 1 for use in lhi.gp, shi.gp...
4172 BFD_RELOC_NDS32_SDA19S0
4174 This is a 19-bit reloc containing the small data area 19-bit signed offset
4175 and shift left by 0 for use in lbi.gp, sbi.gp...
4177 BFD_RELOC_NDS32_GOT20
4179 BFD_RELOC_NDS32_9_PLTREL
4181 BFD_RELOC_NDS32_25_PLTREL
4183 BFD_RELOC_NDS32_COPY
4185 BFD_RELOC_NDS32_GLOB_DAT
4187 BFD_RELOC_NDS32_JMP_SLOT
4189 BFD_RELOC_NDS32_RELATIVE
4191 BFD_RELOC_NDS32_GOTOFF
4193 BFD_RELOC_NDS32_GOTOFF_HI20
4195 BFD_RELOC_NDS32_GOTOFF_LO12
4197 BFD_RELOC_NDS32_GOTPC20
4199 BFD_RELOC_NDS32_GOT_HI20
4201 BFD_RELOC_NDS32_GOT_LO12
4203 BFD_RELOC_NDS32_GOTPC_HI20
4205 BFD_RELOC_NDS32_GOTPC_LO12
4209 BFD_RELOC_NDS32_INSN16
4211 BFD_RELOC_NDS32_LABEL
4213 BFD_RELOC_NDS32_LONGCALL1
4215 BFD_RELOC_NDS32_LONGCALL2
4217 BFD_RELOC_NDS32_LONGCALL3
4219 BFD_RELOC_NDS32_LONGJUMP1
4221 BFD_RELOC_NDS32_LONGJUMP2
4223 BFD_RELOC_NDS32_LONGJUMP3
4225 BFD_RELOC_NDS32_LOADSTORE
4227 BFD_RELOC_NDS32_9_FIXED
4229 BFD_RELOC_NDS32_15_FIXED
4231 BFD_RELOC_NDS32_17_FIXED
4233 BFD_RELOC_NDS32_25_FIXED
4235 BFD_RELOC_NDS32_LONGCALL4
4237 BFD_RELOC_NDS32_LONGCALL5
4239 BFD_RELOC_NDS32_LONGCALL6
4241 BFD_RELOC_NDS32_LONGJUMP4
4243 BFD_RELOC_NDS32_LONGJUMP5
4245 BFD_RELOC_NDS32_LONGJUMP6
4247 BFD_RELOC_NDS32_LONGJUMP7
4251 BFD_RELOC_NDS32_PLTREL_HI20
4253 BFD_RELOC_NDS32_PLTREL_LO12
4255 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4257 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4261 BFD_RELOC_NDS32_SDA12S2_DP
4263 BFD_RELOC_NDS32_SDA12S2_SP
4265 BFD_RELOC_NDS32_LO12S2_DP
4267 BFD_RELOC_NDS32_LO12S2_SP
4271 BFD_RELOC_NDS32_DWARF2_OP1
4273 BFD_RELOC_NDS32_DWARF2_OP2
4275 BFD_RELOC_NDS32_DWARF2_LEB
4277 for dwarf2 debug_line.
4279 BFD_RELOC_NDS32_UPDATE_TA
4281 for eliminate 16-bit instructions
4283 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4285 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4287 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4289 BFD_RELOC_NDS32_GOT_LO15
4291 BFD_RELOC_NDS32_GOT_LO19
4293 BFD_RELOC_NDS32_GOTOFF_LO15
4295 BFD_RELOC_NDS32_GOTOFF_LO19
4297 BFD_RELOC_NDS32_GOT15S2
4299 BFD_RELOC_NDS32_GOT17S2
4301 for PIC object relaxation
4306 This is a 5 bit absolute address.
4308 BFD_RELOC_NDS32_10_UPCREL
4310 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4312 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4314 If fp were omitted, fp can used as another gp.
4316 BFD_RELOC_NDS32_RELAX_ENTRY
4318 BFD_RELOC_NDS32_GOT_SUFF
4320 BFD_RELOC_NDS32_GOTOFF_SUFF
4322 BFD_RELOC_NDS32_PLT_GOT_SUFF
4324 BFD_RELOC_NDS32_MULCALL_SUFF
4328 BFD_RELOC_NDS32_PTR_COUNT
4330 BFD_RELOC_NDS32_PTR_RESOLVED
4332 BFD_RELOC_NDS32_PLTBLOCK
4334 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4336 BFD_RELOC_NDS32_RELAX_REGION_END
4338 BFD_RELOC_NDS32_MINUEND
4340 BFD_RELOC_NDS32_SUBTRAHEND
4342 BFD_RELOC_NDS32_DIFF8
4344 BFD_RELOC_NDS32_DIFF16
4346 BFD_RELOC_NDS32_DIFF32
4348 BFD_RELOC_NDS32_DIFF_ULEB128
4350 BFD_RELOC_NDS32_EMPTY
4352 relaxation relative relocation types
4354 BFD_RELOC_NDS32_25_ABS
4356 This is a 25 bit absolute address.
4358 BFD_RELOC_NDS32_DATA
4360 BFD_RELOC_NDS32_TRAN
4362 BFD_RELOC_NDS32_17IFC_PCREL
4364 BFD_RELOC_NDS32_10IFCU_PCREL
4366 For ex9 and ifc using.
4368 BFD_RELOC_NDS32_TPOFF
4370 BFD_RELOC_NDS32_GOTTPOFF
4372 BFD_RELOC_NDS32_TLS_LE_HI20
4374 BFD_RELOC_NDS32_TLS_LE_LO12
4376 BFD_RELOC_NDS32_TLS_LE_20
4378 BFD_RELOC_NDS32_TLS_LE_15S0
4380 BFD_RELOC_NDS32_TLS_LE_15S1
4382 BFD_RELOC_NDS32_TLS_LE_15S2
4384 BFD_RELOC_NDS32_TLS_LE_ADD
4386 BFD_RELOC_NDS32_TLS_LE_LS
4388 BFD_RELOC_NDS32_TLS_IE_HI20
4390 BFD_RELOC_NDS32_TLS_IE_LO12
4392 BFD_RELOC_NDS32_TLS_IE_LO12S2
4394 BFD_RELOC_NDS32_TLS_IEGP_HI20
4396 BFD_RELOC_NDS32_TLS_IEGP_LO12
4398 BFD_RELOC_NDS32_TLS_IEGP_LO12S2
4400 BFD_RELOC_NDS32_TLS_IEGP_LW
4402 BFD_RELOC_NDS32_TLS_DESC
4404 BFD_RELOC_NDS32_TLS_DESC_HI20
4406 BFD_RELOC_NDS32_TLS_DESC_LO12
4408 BFD_RELOC_NDS32_TLS_DESC_20
4410 BFD_RELOC_NDS32_TLS_DESC_SDA17S2
4412 BFD_RELOC_NDS32_TLS_DESC_ADD
4414 BFD_RELOC_NDS32_TLS_DESC_FUNC
4416 BFD_RELOC_NDS32_TLS_DESC_CALL
4418 BFD_RELOC_NDS32_TLS_DESC_MEM
4420 BFD_RELOC_NDS32_REMOVE
4422 BFD_RELOC_NDS32_GROUP
4428 For floating load store relaxation.
4432 BFD_RELOC_V850_9_PCREL
4434 This is a 9-bit reloc
4436 BFD_RELOC_V850_22_PCREL
4438 This is a 22-bit reloc
4441 BFD_RELOC_V850_SDA_16_16_OFFSET
4443 This is a 16 bit offset from the short data area pointer.
4445 BFD_RELOC_V850_SDA_15_16_OFFSET
4447 This is a 16 bit offset (of which only 15 bits are used) from the
4448 short data area pointer.
4450 BFD_RELOC_V850_ZDA_16_16_OFFSET
4452 This is a 16 bit offset from the zero data area pointer.
4454 BFD_RELOC_V850_ZDA_15_16_OFFSET
4456 This is a 16 bit offset (of which only 15 bits are used) from the
4457 zero data area pointer.
4459 BFD_RELOC_V850_TDA_6_8_OFFSET
4461 This is an 8 bit offset (of which only 6 bits are used) from the
4462 tiny data area pointer.
4464 BFD_RELOC_V850_TDA_7_8_OFFSET
4466 This is an 8bit offset (of which only 7 bits are used) from the tiny
4469 BFD_RELOC_V850_TDA_7_7_OFFSET
4471 This is a 7 bit offset from the tiny data area pointer.
4473 BFD_RELOC_V850_TDA_16_16_OFFSET
4475 This is a 16 bit offset from the tiny data area pointer.
4478 BFD_RELOC_V850_TDA_4_5_OFFSET
4480 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4483 BFD_RELOC_V850_TDA_4_4_OFFSET
4485 This is a 4 bit offset from the tiny data area pointer.
4487 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4489 This is a 16 bit offset from the short data area pointer, with the
4490 bits placed non-contiguously in the instruction.
4492 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4494 This is a 16 bit offset from the zero data area pointer, with the
4495 bits placed non-contiguously in the instruction.
4497 BFD_RELOC_V850_CALLT_6_7_OFFSET
4499 This is a 6 bit offset from the call table base pointer.
4501 BFD_RELOC_V850_CALLT_16_16_OFFSET
4503 This is a 16 bit offset from the call table base pointer.
4505 BFD_RELOC_V850_LONGCALL
4507 Used for relaxing indirect function calls.
4509 BFD_RELOC_V850_LONGJUMP
4511 Used for relaxing indirect jumps.
4513 BFD_RELOC_V850_ALIGN
4515 Used to maintain alignment whilst relaxing.
4517 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4519 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4522 BFD_RELOC_V850_16_PCREL
4524 This is a 16-bit reloc.
4526 BFD_RELOC_V850_17_PCREL
4528 This is a 17-bit reloc.
4532 This is a 23-bit reloc.
4534 BFD_RELOC_V850_32_PCREL
4536 This is a 32-bit reloc.
4538 BFD_RELOC_V850_32_ABS
4540 This is a 32-bit reloc.
4542 BFD_RELOC_V850_16_SPLIT_OFFSET
4544 This is a 16-bit reloc.
4546 BFD_RELOC_V850_16_S1
4548 This is a 16-bit reloc.
4550 BFD_RELOC_V850_LO16_S1
4552 Low 16 bits. 16 bit shifted by 1.
4554 BFD_RELOC_V850_CALLT_15_16_OFFSET
4556 This is a 16 bit offset from the call table base pointer.
4558 BFD_RELOC_V850_32_GOTPCREL
4562 BFD_RELOC_V850_16_GOT
4566 BFD_RELOC_V850_32_GOT
4570 BFD_RELOC_V850_22_PLT_PCREL
4574 BFD_RELOC_V850_32_PLT_PCREL
4582 BFD_RELOC_V850_GLOB_DAT
4586 BFD_RELOC_V850_JMP_SLOT
4590 BFD_RELOC_V850_RELATIVE
4594 BFD_RELOC_V850_16_GOTOFF
4598 BFD_RELOC_V850_32_GOTOFF
4613 This is a 8bit DP reloc for the tms320c30, where the most
4614 significant 8 bits of a 24 bit word are placed into the least
4615 significant 8 bits of the opcode.
4618 BFD_RELOC_TIC54X_PARTLS7
4620 This is a 7bit reloc for the tms320c54x, where the least
4621 significant 7 bits of a 16 bit word are placed into the least
4622 significant 7 bits of the opcode.
4625 BFD_RELOC_TIC54X_PARTMS9
4627 This is a 9bit DP reloc for the tms320c54x, where the most
4628 significant 9 bits of a 16 bit word are placed into the least
4629 significant 9 bits of the opcode.
4634 This is an extended address 23-bit reloc for the tms320c54x.
4637 BFD_RELOC_TIC54X_16_OF_23
4639 This is a 16-bit reloc for the tms320c54x, where the least
4640 significant 16 bits of a 23-bit extended address are placed into
4644 BFD_RELOC_TIC54X_MS7_OF_23
4646 This is a reloc for the tms320c54x, where the most
4647 significant 7 bits of a 23-bit extended address are placed into
4651 BFD_RELOC_C6000_PCR_S21
4653 BFD_RELOC_C6000_PCR_S12
4655 BFD_RELOC_C6000_PCR_S10
4657 BFD_RELOC_C6000_PCR_S7
4659 BFD_RELOC_C6000_ABS_S16
4661 BFD_RELOC_C6000_ABS_L16
4663 BFD_RELOC_C6000_ABS_H16
4665 BFD_RELOC_C6000_SBR_U15_B
4667 BFD_RELOC_C6000_SBR_U15_H
4669 BFD_RELOC_C6000_SBR_U15_W
4671 BFD_RELOC_C6000_SBR_S16
4673 BFD_RELOC_C6000_SBR_L16_B
4675 BFD_RELOC_C6000_SBR_L16_H
4677 BFD_RELOC_C6000_SBR_L16_W
4679 BFD_RELOC_C6000_SBR_H16_B
4681 BFD_RELOC_C6000_SBR_H16_H
4683 BFD_RELOC_C6000_SBR_H16_W
4685 BFD_RELOC_C6000_SBR_GOT_U15_W
4687 BFD_RELOC_C6000_SBR_GOT_L16_W
4689 BFD_RELOC_C6000_SBR_GOT_H16_W
4691 BFD_RELOC_C6000_DSBT_INDEX
4693 BFD_RELOC_C6000_PREL31
4695 BFD_RELOC_C6000_COPY
4697 BFD_RELOC_C6000_JUMP_SLOT
4699 BFD_RELOC_C6000_EHTYPE
4701 BFD_RELOC_C6000_PCR_H16
4703 BFD_RELOC_C6000_PCR_L16
4705 BFD_RELOC_C6000_ALIGN
4707 BFD_RELOC_C6000_FPHEAD
4709 BFD_RELOC_C6000_NOCMP
4711 TMS320C6000 relocations.
4716 This is a 48 bit reloc for the FR30 that stores 32 bits.
4720 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4723 BFD_RELOC_FR30_6_IN_4
4725 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4728 BFD_RELOC_FR30_8_IN_8
4730 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4733 BFD_RELOC_FR30_9_IN_8
4735 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4738 BFD_RELOC_FR30_10_IN_8
4740 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4743 BFD_RELOC_FR30_9_PCREL
4745 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4746 short offset into 8 bits.
4748 BFD_RELOC_FR30_12_PCREL
4750 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4751 short offset into 11 bits.
4754 BFD_RELOC_MCORE_PCREL_IMM8BY4
4756 BFD_RELOC_MCORE_PCREL_IMM11BY2
4758 BFD_RELOC_MCORE_PCREL_IMM4BY2
4760 BFD_RELOC_MCORE_PCREL_32
4762 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4766 Motorola Mcore relocations.
4775 BFD_RELOC_MEP_PCREL8A2
4777 BFD_RELOC_MEP_PCREL12A2
4779 BFD_RELOC_MEP_PCREL17A2
4781 BFD_RELOC_MEP_PCREL24A2
4783 BFD_RELOC_MEP_PCABS24A2
4795 BFD_RELOC_MEP_TPREL7
4797 BFD_RELOC_MEP_TPREL7A2
4799 BFD_RELOC_MEP_TPREL7A4
4801 BFD_RELOC_MEP_UIMM24
4803 BFD_RELOC_MEP_ADDR24A4
4805 BFD_RELOC_MEP_GNU_VTINHERIT
4807 BFD_RELOC_MEP_GNU_VTENTRY
4809 Toshiba Media Processor Relocations.
4813 BFD_RELOC_METAG_HIADDR16
4815 BFD_RELOC_METAG_LOADDR16
4817 BFD_RELOC_METAG_RELBRANCH
4819 BFD_RELOC_METAG_GETSETOFF
4821 BFD_RELOC_METAG_HIOG
4823 BFD_RELOC_METAG_LOOG
4825 BFD_RELOC_METAG_REL8
4827 BFD_RELOC_METAG_REL16
4829 BFD_RELOC_METAG_HI16_GOTOFF
4831 BFD_RELOC_METAG_LO16_GOTOFF
4833 BFD_RELOC_METAG_GETSET_GOTOFF
4835 BFD_RELOC_METAG_GETSET_GOT
4837 BFD_RELOC_METAG_HI16_GOTPC
4839 BFD_RELOC_METAG_LO16_GOTPC
4841 BFD_RELOC_METAG_HI16_PLT
4843 BFD_RELOC_METAG_LO16_PLT
4845 BFD_RELOC_METAG_RELBRANCH_PLT
4847 BFD_RELOC_METAG_GOTOFF
4851 BFD_RELOC_METAG_COPY
4853 BFD_RELOC_METAG_JMP_SLOT
4855 BFD_RELOC_METAG_RELATIVE
4857 BFD_RELOC_METAG_GLOB_DAT
4859 BFD_RELOC_METAG_TLS_GD
4861 BFD_RELOC_METAG_TLS_LDM
4863 BFD_RELOC_METAG_TLS_LDO_HI16
4865 BFD_RELOC_METAG_TLS_LDO_LO16
4867 BFD_RELOC_METAG_TLS_LDO
4869 BFD_RELOC_METAG_TLS_IE
4871 BFD_RELOC_METAG_TLS_IENONPIC
4873 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4875 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4877 BFD_RELOC_METAG_TLS_TPOFF
4879 BFD_RELOC_METAG_TLS_DTPMOD
4881 BFD_RELOC_METAG_TLS_DTPOFF
4883 BFD_RELOC_METAG_TLS_LE
4885 BFD_RELOC_METAG_TLS_LE_HI16
4887 BFD_RELOC_METAG_TLS_LE_LO16
4889 Imagination Technologies Meta relocations.
4894 BFD_RELOC_MMIX_GETA_1
4896 BFD_RELOC_MMIX_GETA_2
4898 BFD_RELOC_MMIX_GETA_3
4900 These are relocations for the GETA instruction.
4902 BFD_RELOC_MMIX_CBRANCH
4904 BFD_RELOC_MMIX_CBRANCH_J
4906 BFD_RELOC_MMIX_CBRANCH_1
4908 BFD_RELOC_MMIX_CBRANCH_2
4910 BFD_RELOC_MMIX_CBRANCH_3
4912 These are relocations for a conditional branch instruction.
4914 BFD_RELOC_MMIX_PUSHJ
4916 BFD_RELOC_MMIX_PUSHJ_1
4918 BFD_RELOC_MMIX_PUSHJ_2
4920 BFD_RELOC_MMIX_PUSHJ_3
4922 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4924 These are relocations for the PUSHJ instruction.
4928 BFD_RELOC_MMIX_JMP_1
4930 BFD_RELOC_MMIX_JMP_2
4932 BFD_RELOC_MMIX_JMP_3
4934 These are relocations for the JMP instruction.
4936 BFD_RELOC_MMIX_ADDR19
4938 This is a relocation for a relative address as in a GETA instruction or
4941 BFD_RELOC_MMIX_ADDR27
4943 This is a relocation for a relative address as in a JMP instruction.
4945 BFD_RELOC_MMIX_REG_OR_BYTE
4947 This is a relocation for an instruction field that may be a general
4948 register or a value 0..255.
4952 This is a relocation for an instruction field that may be a general
4955 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4957 This is a relocation for two instruction fields holding a register and
4958 an offset, the equivalent of the relocation.
4960 BFD_RELOC_MMIX_LOCAL
4962 This relocation is an assertion that the expression is not allocated as
4963 a global register. It does not modify contents.
4966 BFD_RELOC_AVR_7_PCREL
4968 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4969 short offset into 7 bits.
4971 BFD_RELOC_AVR_13_PCREL
4973 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4974 short offset into 12 bits.
4978 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4979 program memory address) into 16 bits.
4981 BFD_RELOC_AVR_LO8_LDI
4983 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4984 data memory address) into 8 bit immediate value of LDI insn.
4986 BFD_RELOC_AVR_HI8_LDI
4988 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4989 of data memory address) into 8 bit immediate value of LDI insn.
4991 BFD_RELOC_AVR_HH8_LDI
4993 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4994 of program memory address) into 8 bit immediate value of LDI insn.
4996 BFD_RELOC_AVR_MS8_LDI
4998 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4999 of 32 bit value) into 8 bit immediate value of LDI insn.
5001 BFD_RELOC_AVR_LO8_LDI_NEG
5003 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5004 (usually data memory address) into 8 bit immediate value of SUBI insn.
5006 BFD_RELOC_AVR_HI8_LDI_NEG
5008 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5009 (high 8 bit of data memory address) into 8 bit immediate value of
5012 BFD_RELOC_AVR_HH8_LDI_NEG
5014 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5015 (most high 8 bit of program memory address) into 8 bit immediate value
5016 of LDI or SUBI insn.
5018 BFD_RELOC_AVR_MS8_LDI_NEG
5020 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
5021 of 32 bit value) into 8 bit immediate value of LDI insn.
5023 BFD_RELOC_AVR_LO8_LDI_PM
5025 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
5026 command address) into 8 bit immediate value of LDI insn.
5028 BFD_RELOC_AVR_LO8_LDI_GS
5030 This is a 16 bit reloc for the AVR that stores 8 bit value
5031 (command address) into 8 bit immediate value of LDI insn. If the address
5032 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5035 BFD_RELOC_AVR_HI8_LDI_PM
5037 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5038 of command address) into 8 bit immediate value of LDI insn.
5040 BFD_RELOC_AVR_HI8_LDI_GS
5042 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
5043 of command address) into 8 bit immediate value of LDI insn. If the address
5044 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
5047 BFD_RELOC_AVR_HH8_LDI_PM
5049 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
5050 of command address) into 8 bit immediate value of LDI insn.
5052 BFD_RELOC_AVR_LO8_LDI_PM_NEG
5054 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5055 (usually command address) into 8 bit immediate value of SUBI insn.
5057 BFD_RELOC_AVR_HI8_LDI_PM_NEG
5059 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5060 (high 8 bit of 16 bit command address) into 8 bit immediate value
5063 BFD_RELOC_AVR_HH8_LDI_PM_NEG
5065 This is a 16 bit reloc for the AVR that stores negated 8 bit value
5066 (high 6 bit of 22 bit command address) into 8 bit immediate
5071 This is a 32 bit reloc for the AVR that stores 23 bit value
5076 This is a 16 bit reloc for the AVR that stores all needed bits
5077 for absolute addressing with ldi with overflow check to linktime
5081 This is a 6 bit reloc for the AVR that stores offset for ldd/std
5084 BFD_RELOC_AVR_6_ADIW
5086 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
5091 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
5092 in .byte lo8(symbol)
5096 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
5097 in .byte hi8(symbol)
5101 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
5102 in .byte hlo8(symbol)
5106 BFD_RELOC_AVR_DIFF16
5108 BFD_RELOC_AVR_DIFF32
5110 AVR relocations to mark the difference of two local symbols.
5111 These are only needed to support linker relaxation and can be ignored
5112 when not relaxing. The field is set to the value of the difference
5113 assuming no relaxation. The relocation encodes the position of the
5114 second symbol so the linker can determine whether to adjust the field
5117 BFD_RELOC_AVR_LDS_STS_16
5119 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
5120 lds and sts instructions supported only tiny core.
5124 This is a 6 bit reloc for the AVR that stores an I/O register
5125 number for the IN and OUT instructions
5129 This is a 5 bit reloc for the AVR that stores an I/O register
5130 number for the SBIC, SBIS, SBI and CBI instructions
5133 BFD_RELOC_RISCV_HI20
5135 BFD_RELOC_RISCV_PCREL_HI20
5137 BFD_RELOC_RISCV_PCREL_LO12_I
5139 BFD_RELOC_RISCV_PCREL_LO12_S
5141 BFD_RELOC_RISCV_LO12_I
5143 BFD_RELOC_RISCV_LO12_S
5145 BFD_RELOC_RISCV_GPREL12_I
5147 BFD_RELOC_RISCV_GPREL12_S
5149 BFD_RELOC_RISCV_TPREL_HI20
5151 BFD_RELOC_RISCV_TPREL_LO12_I
5153 BFD_RELOC_RISCV_TPREL_LO12_S
5155 BFD_RELOC_RISCV_TPREL_ADD
5157 BFD_RELOC_RISCV_CALL
5159 BFD_RELOC_RISCV_CALL_PLT
5161 BFD_RELOC_RISCV_ADD8
5163 BFD_RELOC_RISCV_ADD16
5165 BFD_RELOC_RISCV_ADD32
5167 BFD_RELOC_RISCV_ADD64
5169 BFD_RELOC_RISCV_SUB8
5171 BFD_RELOC_RISCV_SUB16
5173 BFD_RELOC_RISCV_SUB32
5175 BFD_RELOC_RISCV_SUB64
5177 BFD_RELOC_RISCV_GOT_HI20
5179 BFD_RELOC_RISCV_TLS_GOT_HI20
5181 BFD_RELOC_RISCV_TLS_GD_HI20
5185 BFD_RELOC_RISCV_TLS_DTPMOD32
5187 BFD_RELOC_RISCV_TLS_DTPREL32
5189 BFD_RELOC_RISCV_TLS_DTPMOD64
5191 BFD_RELOC_RISCV_TLS_DTPREL64
5193 BFD_RELOC_RISCV_TLS_TPREL32
5195 BFD_RELOC_RISCV_TLS_TPREL64
5197 BFD_RELOC_RISCV_ALIGN
5199 BFD_RELOC_RISCV_RVC_BRANCH
5201 BFD_RELOC_RISCV_RVC_JUMP
5203 BFD_RELOC_RISCV_RVC_LUI
5205 BFD_RELOC_RISCV_GPREL_I
5207 BFD_RELOC_RISCV_GPREL_S
5209 BFD_RELOC_RISCV_TPREL_I
5211 BFD_RELOC_RISCV_TPREL_S
5213 BFD_RELOC_RISCV_RELAX
5217 BFD_RELOC_RISCV_SUB6
5219 BFD_RELOC_RISCV_SET6
5221 BFD_RELOC_RISCV_SET8
5223 BFD_RELOC_RISCV_SET16
5225 BFD_RELOC_RISCV_SET32
5227 BFD_RELOC_RISCV_32_PCREL
5234 BFD_RELOC_RL78_NEG16
5236 BFD_RELOC_RL78_NEG24
5238 BFD_RELOC_RL78_NEG32
5240 BFD_RELOC_RL78_16_OP
5242 BFD_RELOC_RL78_24_OP
5244 BFD_RELOC_RL78_32_OP
5252 BFD_RELOC_RL78_DIR3U_PCREL
5256 BFD_RELOC_RL78_GPRELB
5258 BFD_RELOC_RL78_GPRELW
5260 BFD_RELOC_RL78_GPRELL
5264 BFD_RELOC_RL78_OP_SUBTRACT
5266 BFD_RELOC_RL78_OP_NEG
5268 BFD_RELOC_RL78_OP_AND
5270 BFD_RELOC_RL78_OP_SHRA
5274 BFD_RELOC_RL78_ABS16
5276 BFD_RELOC_RL78_ABS16_REV
5278 BFD_RELOC_RL78_ABS32
5280 BFD_RELOC_RL78_ABS32_REV
5282 BFD_RELOC_RL78_ABS16U
5284 BFD_RELOC_RL78_ABS16UW
5286 BFD_RELOC_RL78_ABS16UL
5288 BFD_RELOC_RL78_RELAX
5298 BFD_RELOC_RL78_SADDR
5300 Renesas RL78 Relocations.
5323 BFD_RELOC_RX_DIR3U_PCREL
5335 BFD_RELOC_RX_OP_SUBTRACT
5343 BFD_RELOC_RX_ABS16_REV
5347 BFD_RELOC_RX_ABS32_REV
5351 BFD_RELOC_RX_ABS16UW
5353 BFD_RELOC_RX_ABS16UL
5357 Renesas RX Relocations.
5370 32 bit PC relative PLT address.
5374 Copy symbol at runtime.
5376 BFD_RELOC_390_GLOB_DAT
5380 BFD_RELOC_390_JMP_SLOT
5384 BFD_RELOC_390_RELATIVE
5386 Adjust by program base.
5390 32 bit PC relative offset to GOT.
5396 BFD_RELOC_390_PC12DBL
5398 PC relative 12 bit shifted by 1.
5400 BFD_RELOC_390_PLT12DBL
5402 12 bit PC rel. PLT shifted by 1.
5404 BFD_RELOC_390_PC16DBL
5406 PC relative 16 bit shifted by 1.
5408 BFD_RELOC_390_PLT16DBL
5410 16 bit PC rel. PLT shifted by 1.
5412 BFD_RELOC_390_PC24DBL
5414 PC relative 24 bit shifted by 1.
5416 BFD_RELOC_390_PLT24DBL
5418 24 bit PC rel. PLT shifted by 1.
5420 BFD_RELOC_390_PC32DBL
5422 PC relative 32 bit shifted by 1.
5424 BFD_RELOC_390_PLT32DBL
5426 32 bit PC rel. PLT shifted by 1.
5428 BFD_RELOC_390_GOTPCDBL
5430 32 bit PC rel. GOT shifted by 1.
5438 64 bit PC relative PLT address.
5440 BFD_RELOC_390_GOTENT
5442 32 bit rel. offset to GOT entry.
5444 BFD_RELOC_390_GOTOFF64
5446 64 bit offset to GOT.
5448 BFD_RELOC_390_GOTPLT12
5450 12-bit offset to symbol-entry within GOT, with PLT handling.
5452 BFD_RELOC_390_GOTPLT16
5454 16-bit offset to symbol-entry within GOT, with PLT handling.
5456 BFD_RELOC_390_GOTPLT32
5458 32-bit offset to symbol-entry within GOT, with PLT handling.
5460 BFD_RELOC_390_GOTPLT64
5462 64-bit offset to symbol-entry within GOT, with PLT handling.
5464 BFD_RELOC_390_GOTPLTENT
5466 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5468 BFD_RELOC_390_PLTOFF16
5470 16-bit rel. offset from the GOT to a PLT entry.
5472 BFD_RELOC_390_PLTOFF32
5474 32-bit rel. offset from the GOT to a PLT entry.
5476 BFD_RELOC_390_PLTOFF64
5478 64-bit rel. offset from the GOT to a PLT entry.
5481 BFD_RELOC_390_TLS_LOAD
5483 BFD_RELOC_390_TLS_GDCALL
5485 BFD_RELOC_390_TLS_LDCALL
5487 BFD_RELOC_390_TLS_GD32
5489 BFD_RELOC_390_TLS_GD64
5491 BFD_RELOC_390_TLS_GOTIE12
5493 BFD_RELOC_390_TLS_GOTIE32
5495 BFD_RELOC_390_TLS_GOTIE64
5497 BFD_RELOC_390_TLS_LDM32
5499 BFD_RELOC_390_TLS_LDM64
5501 BFD_RELOC_390_TLS_IE32
5503 BFD_RELOC_390_TLS_IE64
5505 BFD_RELOC_390_TLS_IEENT
5507 BFD_RELOC_390_TLS_LE32
5509 BFD_RELOC_390_TLS_LE64
5511 BFD_RELOC_390_TLS_LDO32
5513 BFD_RELOC_390_TLS_LDO64
5515 BFD_RELOC_390_TLS_DTPMOD
5517 BFD_RELOC_390_TLS_DTPOFF
5519 BFD_RELOC_390_TLS_TPOFF
5521 s390 tls relocations.
5528 BFD_RELOC_390_GOTPLT20
5530 BFD_RELOC_390_TLS_GOTIE20
5532 Long displacement extension.
5535 BFD_RELOC_390_IRELATIVE
5537 STT_GNU_IFUNC relocation.
5540 BFD_RELOC_SCORE_GPREL15
5543 Low 16 bit for load/store
5545 BFD_RELOC_SCORE_DUMMY2
5549 This is a 24-bit reloc with the right 1 bit assumed to be 0
5551 BFD_RELOC_SCORE_BRANCH
5553 This is a 19-bit reloc with the right 1 bit assumed to be 0
5555 BFD_RELOC_SCORE_IMM30
5557 This is a 32-bit reloc for 48-bit instructions.
5559 BFD_RELOC_SCORE_IMM32
5561 This is a 32-bit reloc for 48-bit instructions.
5563 BFD_RELOC_SCORE16_JMP
5565 This is a 11-bit reloc with the right 1 bit assumed to be 0
5567 BFD_RELOC_SCORE16_BRANCH
5569 This is a 8-bit reloc with the right 1 bit assumed to be 0
5571 BFD_RELOC_SCORE_BCMP
5573 This is a 9-bit reloc with the right 1 bit assumed to be 0
5575 BFD_RELOC_SCORE_GOT15
5577 BFD_RELOC_SCORE_GOT_LO16
5579 BFD_RELOC_SCORE_CALL15
5581 BFD_RELOC_SCORE_DUMMY_HI16
5583 Undocumented Score relocs
5588 Scenix IP2K - 9-bit register number / data address
5592 Scenix IP2K - 4-bit register/data bank number
5594 BFD_RELOC_IP2K_ADDR16CJP
5596 Scenix IP2K - low 13 bits of instruction word address
5598 BFD_RELOC_IP2K_PAGE3
5600 Scenix IP2K - high 3 bits of instruction word address
5602 BFD_RELOC_IP2K_LO8DATA
5604 BFD_RELOC_IP2K_HI8DATA
5606 BFD_RELOC_IP2K_EX8DATA
5608 Scenix IP2K - ext/low/high 8 bits of data address
5610 BFD_RELOC_IP2K_LO8INSN
5612 BFD_RELOC_IP2K_HI8INSN
5614 Scenix IP2K - low/high 8 bits of instruction word address
5616 BFD_RELOC_IP2K_PC_SKIP
5618 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5622 Scenix IP2K - 16 bit word address in text section.
5624 BFD_RELOC_IP2K_FR_OFFSET
5626 Scenix IP2K - 7-bit sp or dp offset
5628 BFD_RELOC_VPE4KMATH_DATA
5630 BFD_RELOC_VPE4KMATH_INSN
5632 Scenix VPE4K coprocessor - data/insn-space addressing
5635 BFD_RELOC_VTABLE_INHERIT
5637 BFD_RELOC_VTABLE_ENTRY
5639 These two relocations are used by the linker to determine which of
5640 the entries in a C++ virtual function table are actually used. When
5641 the --gc-sections option is given, the linker will zero out the entries
5642 that are not used, so that the code for those functions need not be
5643 included in the output.
5645 VTABLE_INHERIT is a zero-space relocation used to describe to the
5646 linker the inheritance tree of a C++ virtual function table. The
5647 relocation's symbol should be the parent class' vtable, and the
5648 relocation should be located at the child vtable.
5650 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5651 virtual function table entry. The reloc's symbol should refer to the
5652 table of the class mentioned in the code. Off of that base, an offset
5653 describes the entry that is being used. For Rela hosts, this offset
5654 is stored in the reloc's addend. For Rel hosts, we are forced to put
5655 this offset in the reloc's section offset.
5658 BFD_RELOC_IA64_IMM14
5660 BFD_RELOC_IA64_IMM22
5662 BFD_RELOC_IA64_IMM64
5664 BFD_RELOC_IA64_DIR32MSB
5666 BFD_RELOC_IA64_DIR32LSB
5668 BFD_RELOC_IA64_DIR64MSB
5670 BFD_RELOC_IA64_DIR64LSB
5672 BFD_RELOC_IA64_GPREL22
5674 BFD_RELOC_IA64_GPREL64I
5676 BFD_RELOC_IA64_GPREL32MSB
5678 BFD_RELOC_IA64_GPREL32LSB
5680 BFD_RELOC_IA64_GPREL64MSB
5682 BFD_RELOC_IA64_GPREL64LSB
5684 BFD_RELOC_IA64_LTOFF22
5686 BFD_RELOC_IA64_LTOFF64I
5688 BFD_RELOC_IA64_PLTOFF22
5690 BFD_RELOC_IA64_PLTOFF64I
5692 BFD_RELOC_IA64_PLTOFF64MSB
5694 BFD_RELOC_IA64_PLTOFF64LSB
5696 BFD_RELOC_IA64_FPTR64I
5698 BFD_RELOC_IA64_FPTR32MSB
5700 BFD_RELOC_IA64_FPTR32LSB
5702 BFD_RELOC_IA64_FPTR64MSB
5704 BFD_RELOC_IA64_FPTR64LSB
5706 BFD_RELOC_IA64_PCREL21B
5708 BFD_RELOC_IA64_PCREL21BI
5710 BFD_RELOC_IA64_PCREL21M
5712 BFD_RELOC_IA64_PCREL21F
5714 BFD_RELOC_IA64_PCREL22
5716 BFD_RELOC_IA64_PCREL60B
5718 BFD_RELOC_IA64_PCREL64I
5720 BFD_RELOC_IA64_PCREL32MSB
5722 BFD_RELOC_IA64_PCREL32LSB
5724 BFD_RELOC_IA64_PCREL64MSB
5726 BFD_RELOC_IA64_PCREL64LSB
5728 BFD_RELOC_IA64_LTOFF_FPTR22
5730 BFD_RELOC_IA64_LTOFF_FPTR64I
5732 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5734 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5736 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5738 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5740 BFD_RELOC_IA64_SEGREL32MSB
5742 BFD_RELOC_IA64_SEGREL32LSB
5744 BFD_RELOC_IA64_SEGREL64MSB
5746 BFD_RELOC_IA64_SEGREL64LSB
5748 BFD_RELOC_IA64_SECREL32MSB
5750 BFD_RELOC_IA64_SECREL32LSB
5752 BFD_RELOC_IA64_SECREL64MSB
5754 BFD_RELOC_IA64_SECREL64LSB
5756 BFD_RELOC_IA64_REL32MSB
5758 BFD_RELOC_IA64_REL32LSB
5760 BFD_RELOC_IA64_REL64MSB
5762 BFD_RELOC_IA64_REL64LSB
5764 BFD_RELOC_IA64_LTV32MSB
5766 BFD_RELOC_IA64_LTV32LSB
5768 BFD_RELOC_IA64_LTV64MSB
5770 BFD_RELOC_IA64_LTV64LSB
5772 BFD_RELOC_IA64_IPLTMSB
5774 BFD_RELOC_IA64_IPLTLSB
5778 BFD_RELOC_IA64_LTOFF22X
5780 BFD_RELOC_IA64_LDXMOV
5782 BFD_RELOC_IA64_TPREL14
5784 BFD_RELOC_IA64_TPREL22
5786 BFD_RELOC_IA64_TPREL64I
5788 BFD_RELOC_IA64_TPREL64MSB
5790 BFD_RELOC_IA64_TPREL64LSB
5792 BFD_RELOC_IA64_LTOFF_TPREL22
5794 BFD_RELOC_IA64_DTPMOD64MSB
5796 BFD_RELOC_IA64_DTPMOD64LSB
5798 BFD_RELOC_IA64_LTOFF_DTPMOD22
5800 BFD_RELOC_IA64_DTPREL14
5802 BFD_RELOC_IA64_DTPREL22
5804 BFD_RELOC_IA64_DTPREL64I
5806 BFD_RELOC_IA64_DTPREL32MSB
5808 BFD_RELOC_IA64_DTPREL32LSB
5810 BFD_RELOC_IA64_DTPREL64MSB
5812 BFD_RELOC_IA64_DTPREL64LSB
5814 BFD_RELOC_IA64_LTOFF_DTPREL22
5816 Intel IA64 Relocations.
5819 BFD_RELOC_M68HC11_HI8
5821 Motorola 68HC11 reloc.
5822 This is the 8 bit high part of an absolute address.
5824 BFD_RELOC_M68HC11_LO8
5826 Motorola 68HC11 reloc.
5827 This is the 8 bit low part of an absolute address.
5829 BFD_RELOC_M68HC11_3B
5831 Motorola 68HC11 reloc.
5832 This is the 3 bit of a value.
5834 BFD_RELOC_M68HC11_RL_JUMP
5836 Motorola 68HC11 reloc.
5837 This reloc marks the beginning of a jump/call instruction.
5838 It is used for linker relaxation to correctly identify beginning
5839 of instruction and change some branches to use PC-relative
5842 BFD_RELOC_M68HC11_RL_GROUP
5844 Motorola 68HC11 reloc.
5845 This reloc marks a group of several instructions that gcc generates
5846 and for which the linker relaxation pass can modify and/or remove
5849 BFD_RELOC_M68HC11_LO16
5851 Motorola 68HC11 reloc.
5852 This is the 16-bit lower part of an address. It is used for 'call'
5853 instruction to specify the symbol address without any special
5854 transformation (due to memory bank window).
5856 BFD_RELOC_M68HC11_PAGE
5858 Motorola 68HC11 reloc.
5859 This is a 8-bit reloc that specifies the page number of an address.
5860 It is used by 'call' instruction to specify the page number of
5863 BFD_RELOC_M68HC11_24
5865 Motorola 68HC11 reloc.
5866 This is a 24-bit reloc that represents the address with a 16-bit
5867 value and a 8-bit page number. The symbol address is transformed
5868 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5870 BFD_RELOC_M68HC12_5B
5872 Motorola 68HC12 reloc.
5873 This is the 5 bits of a value.
5875 BFD_RELOC_XGATE_RL_JUMP
5877 Freescale XGATE reloc.
5878 This reloc marks the beginning of a bra/jal instruction.
5880 BFD_RELOC_XGATE_RL_GROUP
5882 Freescale XGATE reloc.
5883 This reloc marks a group of several instructions that gcc generates
5884 and for which the linker relaxation pass can modify and/or remove
5887 BFD_RELOC_XGATE_LO16
5889 Freescale XGATE reloc.
5890 This is the 16-bit lower part of an address. It is used for the '16-bit'
5893 BFD_RELOC_XGATE_GPAGE
5895 Freescale XGATE reloc.
5899 Freescale XGATE reloc.
5901 BFD_RELOC_XGATE_PCREL_9
5903 Freescale XGATE reloc.
5904 This is a 9-bit pc-relative reloc.
5906 BFD_RELOC_XGATE_PCREL_10
5908 Freescale XGATE reloc.
5909 This is a 10-bit pc-relative reloc.
5911 BFD_RELOC_XGATE_IMM8_LO
5913 Freescale XGATE reloc.
5914 This is the 16-bit lower part of an address. It is used for the '16-bit'
5917 BFD_RELOC_XGATE_IMM8_HI
5919 Freescale XGATE reloc.
5920 This is the 16-bit higher part of an address. It is used for the '16-bit'
5923 BFD_RELOC_XGATE_IMM3
5925 Freescale XGATE reloc.
5926 This is a 3-bit pc-relative reloc.
5928 BFD_RELOC_XGATE_IMM4
5930 Freescale XGATE reloc.
5931 This is a 4-bit pc-relative reloc.
5933 BFD_RELOC_XGATE_IMM5
5935 Freescale XGATE reloc.
5936 This is a 5-bit pc-relative reloc.
5938 BFD_RELOC_M68HC12_9B
5940 Motorola 68HC12 reloc.
5941 This is the 9 bits of a value.
5943 BFD_RELOC_M68HC12_16B
5945 Motorola 68HC12 reloc.
5946 This is the 16 bits of a value.
5948 BFD_RELOC_M68HC12_9_PCREL
5950 Motorola 68HC12/XGATE reloc.
5951 This is a PCREL9 branch.
5953 BFD_RELOC_M68HC12_10_PCREL
5955 Motorola 68HC12/XGATE reloc.
5956 This is a PCREL10 branch.
5958 BFD_RELOC_M68HC12_LO8XG
5960 Motorola 68HC12/XGATE reloc.
5961 This is the 8 bit low part of an absolute address and immediately precedes
5962 a matching HI8XG part.
5964 BFD_RELOC_M68HC12_HI8XG
5966 Motorola 68HC12/XGATE reloc.
5967 This is the 8 bit high part of an absolute address and immediately follows
5968 a matching LO8XG part.
5970 BFD_RELOC_S12Z_15_PCREL
5972 Freescale S12Z reloc.
5973 This is a 15 bit relative address. If the most significant bits are all zero
5974 then it may be truncated to 8 bits.
5979 BFD_RELOC_CR16_NUM16
5981 BFD_RELOC_CR16_NUM32
5983 BFD_RELOC_CR16_NUM32a
5985 BFD_RELOC_CR16_REGREL0
5987 BFD_RELOC_CR16_REGREL4
5989 BFD_RELOC_CR16_REGREL4a
5991 BFD_RELOC_CR16_REGREL14
5993 BFD_RELOC_CR16_REGREL14a
5995 BFD_RELOC_CR16_REGREL16
5997 BFD_RELOC_CR16_REGREL20
5999 BFD_RELOC_CR16_REGREL20a
6001 BFD_RELOC_CR16_ABS20
6003 BFD_RELOC_CR16_ABS24
6009 BFD_RELOC_CR16_IMM16
6011 BFD_RELOC_CR16_IMM20
6013 BFD_RELOC_CR16_IMM24
6015 BFD_RELOC_CR16_IMM32
6017 BFD_RELOC_CR16_IMM32a
6019 BFD_RELOC_CR16_DISP4
6021 BFD_RELOC_CR16_DISP8
6023 BFD_RELOC_CR16_DISP16
6025 BFD_RELOC_CR16_DISP20
6027 BFD_RELOC_CR16_DISP24
6029 BFD_RELOC_CR16_DISP24a
6031 BFD_RELOC_CR16_SWITCH8
6033 BFD_RELOC_CR16_SWITCH16
6035 BFD_RELOC_CR16_SWITCH32
6037 BFD_RELOC_CR16_GOT_REGREL20
6039 BFD_RELOC_CR16_GOTC_REGREL20
6041 BFD_RELOC_CR16_GLOB_DAT
6043 NS CR16 Relocations.
6050 BFD_RELOC_CRX_REL8_CMP
6058 BFD_RELOC_CRX_REGREL12
6060 BFD_RELOC_CRX_REGREL22
6062 BFD_RELOC_CRX_REGREL28
6064 BFD_RELOC_CRX_REGREL32
6080 BFD_RELOC_CRX_SWITCH8
6082 BFD_RELOC_CRX_SWITCH16
6084 BFD_RELOC_CRX_SWITCH32
6089 BFD_RELOC_CRIS_BDISP8
6091 BFD_RELOC_CRIS_UNSIGNED_5
6093 BFD_RELOC_CRIS_SIGNED_6
6095 BFD_RELOC_CRIS_UNSIGNED_6
6097 BFD_RELOC_CRIS_SIGNED_8
6099 BFD_RELOC_CRIS_UNSIGNED_8
6101 BFD_RELOC_CRIS_SIGNED_16
6103 BFD_RELOC_CRIS_UNSIGNED_16
6105 BFD_RELOC_CRIS_LAPCQ_OFFSET
6107 BFD_RELOC_CRIS_UNSIGNED_4
6109 These relocs are only used within the CRIS assembler. They are not
6110 (at present) written to any object files.
6114 BFD_RELOC_CRIS_GLOB_DAT
6116 BFD_RELOC_CRIS_JUMP_SLOT
6118 BFD_RELOC_CRIS_RELATIVE
6120 Relocs used in ELF shared libraries for CRIS.
6122 BFD_RELOC_CRIS_32_GOT
6124 32-bit offset to symbol-entry within GOT.
6126 BFD_RELOC_CRIS_16_GOT
6128 16-bit offset to symbol-entry within GOT.
6130 BFD_RELOC_CRIS_32_GOTPLT
6132 32-bit offset to symbol-entry within GOT, with PLT handling.
6134 BFD_RELOC_CRIS_16_GOTPLT
6136 16-bit offset to symbol-entry within GOT, with PLT handling.
6138 BFD_RELOC_CRIS_32_GOTREL
6140 32-bit offset to symbol, relative to GOT.
6142 BFD_RELOC_CRIS_32_PLT_GOTREL
6144 32-bit offset to symbol with PLT entry, relative to GOT.
6146 BFD_RELOC_CRIS_32_PLT_PCREL
6148 32-bit offset to symbol with PLT entry, relative to this relocation.
6151 BFD_RELOC_CRIS_32_GOT_GD
6153 BFD_RELOC_CRIS_16_GOT_GD
6155 BFD_RELOC_CRIS_32_GD
6159 BFD_RELOC_CRIS_32_DTPREL
6161 BFD_RELOC_CRIS_16_DTPREL
6163 BFD_RELOC_CRIS_32_GOT_TPREL
6165 BFD_RELOC_CRIS_16_GOT_TPREL
6167 BFD_RELOC_CRIS_32_TPREL
6169 BFD_RELOC_CRIS_16_TPREL
6171 BFD_RELOC_CRIS_DTPMOD
6173 BFD_RELOC_CRIS_32_IE
6175 Relocs used in TLS code for CRIS.
6178 BFD_RELOC_OR1K_REL_26
6180 BFD_RELOC_OR1K_SLO16
6182 BFD_RELOC_OR1K_PCREL_PG21
6186 BFD_RELOC_OR1K_SLO13
6188 BFD_RELOC_OR1K_GOTPC_HI16
6190 BFD_RELOC_OR1K_GOTPC_LO16
6192 BFD_RELOC_OR1K_GOT_AHI16
6194 BFD_RELOC_OR1K_GOT16
6196 BFD_RELOC_OR1K_GOT_PG21
6198 BFD_RELOC_OR1K_GOT_LO13
6200 BFD_RELOC_OR1K_PLT26
6202 BFD_RELOC_OR1K_PLTA26
6204 BFD_RELOC_OR1K_GOTOFF_SLO16
6208 BFD_RELOC_OR1K_GLOB_DAT
6210 BFD_RELOC_OR1K_JMP_SLOT
6212 BFD_RELOC_OR1K_RELATIVE
6214 BFD_RELOC_OR1K_TLS_GD_HI16
6216 BFD_RELOC_OR1K_TLS_GD_LO16
6218 BFD_RELOC_OR1K_TLS_GD_PG21
6220 BFD_RELOC_OR1K_TLS_GD_LO13
6222 BFD_RELOC_OR1K_TLS_LDM_HI16
6224 BFD_RELOC_OR1K_TLS_LDM_LO16
6226 BFD_RELOC_OR1K_TLS_LDM_PG21
6228 BFD_RELOC_OR1K_TLS_LDM_LO13
6230 BFD_RELOC_OR1K_TLS_LDO_HI16
6232 BFD_RELOC_OR1K_TLS_LDO_LO16
6234 BFD_RELOC_OR1K_TLS_IE_HI16
6236 BFD_RELOC_OR1K_TLS_IE_AHI16
6238 BFD_RELOC_OR1K_TLS_IE_LO16
6240 BFD_RELOC_OR1K_TLS_IE_PG21
6242 BFD_RELOC_OR1K_TLS_IE_LO13
6244 BFD_RELOC_OR1K_TLS_LE_HI16
6246 BFD_RELOC_OR1K_TLS_LE_AHI16
6248 BFD_RELOC_OR1K_TLS_LE_LO16
6250 BFD_RELOC_OR1K_TLS_LE_SLO16
6252 BFD_RELOC_OR1K_TLS_TPOFF
6254 BFD_RELOC_OR1K_TLS_DTPOFF
6256 BFD_RELOC_OR1K_TLS_DTPMOD
6258 OpenRISC 1000 Relocations.
6261 BFD_RELOC_H8_DIR16A8
6263 BFD_RELOC_H8_DIR16R8
6265 BFD_RELOC_H8_DIR24A8
6267 BFD_RELOC_H8_DIR24R8
6269 BFD_RELOC_H8_DIR32A16
6271 BFD_RELOC_H8_DISP32A16
6276 BFD_RELOC_XSTORMY16_REL_12
6278 BFD_RELOC_XSTORMY16_12
6280 BFD_RELOC_XSTORMY16_24
6282 BFD_RELOC_XSTORMY16_FPTR16
6284 Sony Xstormy16 Relocations.
6289 Self-describing complex relocations.
6293 BFD_RELOC_VAX_GLOB_DAT
6295 BFD_RELOC_VAX_JMP_SLOT
6297 BFD_RELOC_VAX_RELATIVE
6299 Relocations used by VAX ELF.
6304 Morpho MT - 16 bit immediate relocation.
6308 Morpho MT - Hi 16 bits of an address.
6312 Morpho MT - Low 16 bits of an address.
6314 BFD_RELOC_MT_GNU_VTINHERIT
6316 Morpho MT - Used to tell the linker which vtable entries are used.
6318 BFD_RELOC_MT_GNU_VTENTRY
6320 Morpho MT - Used to tell the linker which vtable entries are used.
6322 BFD_RELOC_MT_PCINSN8
6324 Morpho MT - 8 bit immediate relocation.
6327 BFD_RELOC_MSP430_10_PCREL
6329 BFD_RELOC_MSP430_16_PCREL
6333 BFD_RELOC_MSP430_16_PCREL_BYTE
6335 BFD_RELOC_MSP430_16_BYTE
6337 BFD_RELOC_MSP430_2X_PCREL
6339 BFD_RELOC_MSP430_RL_PCREL
6341 BFD_RELOC_MSP430_ABS8
6343 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6345 BFD_RELOC_MSP430X_PCR20_EXT_DST
6347 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6349 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6351 BFD_RELOC_MSP430X_ABS20_EXT_DST
6353 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6355 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6357 BFD_RELOC_MSP430X_ABS20_ADR_DST
6359 BFD_RELOC_MSP430X_PCR16
6361 BFD_RELOC_MSP430X_PCR20_CALL
6363 BFD_RELOC_MSP430X_ABS16
6365 BFD_RELOC_MSP430_ABS_HI16
6367 BFD_RELOC_MSP430_PREL31
6369 BFD_RELOC_MSP430_SYM_DIFF
6371 BFD_RELOC_MSP430_SET_ULEB128
6373 BFD_RELOC_MSP430_SUB_ULEB128
6376 msp430 specific relocation codes
6383 BFD_RELOC_NIOS2_CALL26
6385 BFD_RELOC_NIOS2_IMM5
6387 BFD_RELOC_NIOS2_CACHE_OPX
6389 BFD_RELOC_NIOS2_IMM6
6391 BFD_RELOC_NIOS2_IMM8
6393 BFD_RELOC_NIOS2_HI16
6395 BFD_RELOC_NIOS2_LO16
6397 BFD_RELOC_NIOS2_HIADJ16
6399 BFD_RELOC_NIOS2_GPREL
6401 BFD_RELOC_NIOS2_UJMP
6403 BFD_RELOC_NIOS2_CJMP
6405 BFD_RELOC_NIOS2_CALLR
6407 BFD_RELOC_NIOS2_ALIGN
6409 BFD_RELOC_NIOS2_GOT16
6411 BFD_RELOC_NIOS2_CALL16
6413 BFD_RELOC_NIOS2_GOTOFF_LO
6415 BFD_RELOC_NIOS2_GOTOFF_HA
6417 BFD_RELOC_NIOS2_PCREL_LO
6419 BFD_RELOC_NIOS2_PCREL_HA
6421 BFD_RELOC_NIOS2_TLS_GD16
6423 BFD_RELOC_NIOS2_TLS_LDM16
6425 BFD_RELOC_NIOS2_TLS_LDO16
6427 BFD_RELOC_NIOS2_TLS_IE16
6429 BFD_RELOC_NIOS2_TLS_LE16
6431 BFD_RELOC_NIOS2_TLS_DTPMOD
6433 BFD_RELOC_NIOS2_TLS_DTPREL
6435 BFD_RELOC_NIOS2_TLS_TPREL
6437 BFD_RELOC_NIOS2_COPY
6439 BFD_RELOC_NIOS2_GLOB_DAT
6441 BFD_RELOC_NIOS2_JUMP_SLOT
6443 BFD_RELOC_NIOS2_RELATIVE
6445 BFD_RELOC_NIOS2_GOTOFF
6447 BFD_RELOC_NIOS2_CALL26_NOAT
6449 BFD_RELOC_NIOS2_GOT_LO
6451 BFD_RELOC_NIOS2_GOT_HA
6453 BFD_RELOC_NIOS2_CALL_LO
6455 BFD_RELOC_NIOS2_CALL_HA
6457 BFD_RELOC_NIOS2_R2_S12
6459 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6461 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6463 BFD_RELOC_NIOS2_R2_T1I7_2
6465 BFD_RELOC_NIOS2_R2_T2I4
6467 BFD_RELOC_NIOS2_R2_T2I4_1
6469 BFD_RELOC_NIOS2_R2_T2I4_2
6471 BFD_RELOC_NIOS2_R2_X1I7_2
6473 BFD_RELOC_NIOS2_R2_X2L5
6475 BFD_RELOC_NIOS2_R2_F1I5_2
6477 BFD_RELOC_NIOS2_R2_L5I4X1
6479 BFD_RELOC_NIOS2_R2_T1X1I6
6481 BFD_RELOC_NIOS2_R2_T1X1I6_2
6483 Relocations used by the Altera Nios II core.
6488 PRU LDI 16-bit unsigned data-memory relocation.
6490 BFD_RELOC_PRU_U16_PMEMIMM
6492 PRU LDI 16-bit unsigned instruction-memory relocation.
6496 PRU relocation for two consecutive LDI load instructions that load a
6497 32 bit value into a register. If the higher bits are all zero, then
6498 the second instruction may be relaxed.
6500 BFD_RELOC_PRU_S10_PCREL
6502 PRU QBBx 10-bit signed PC-relative relocation.
6504 BFD_RELOC_PRU_U8_PCREL
6506 PRU 8-bit unsigned relocation used for the LOOP instruction.
6508 BFD_RELOC_PRU_32_PMEM
6510 BFD_RELOC_PRU_16_PMEM
6512 PRU Program Memory relocations. Used to convert from byte addressing to
6513 32-bit word addressing.
6515 BFD_RELOC_PRU_GNU_DIFF8
6517 BFD_RELOC_PRU_GNU_DIFF16
6519 BFD_RELOC_PRU_GNU_DIFF32
6521 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6523 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6525 PRU relocations to mark the difference of two local symbols.
6526 These are only needed to support linker relaxation and can be ignored
6527 when not relaxing. The field is set to the value of the difference
6528 assuming no relaxation. The relocation encodes the position of the
6529 second symbol so the linker can determine whether to adjust the field
6530 value. The PMEM variants encode the word difference, instead of byte
6531 difference between symbols.
6534 BFD_RELOC_IQ2000_OFFSET_16
6536 BFD_RELOC_IQ2000_OFFSET_21
6538 BFD_RELOC_IQ2000_UHI16
6543 BFD_RELOC_XTENSA_RTLD
6545 Special Xtensa relocation used only by PLT entries in ELF shared
6546 objects to indicate that the runtime linker should set the value
6547 to one of its own internal functions or data structures.
6549 BFD_RELOC_XTENSA_GLOB_DAT
6551 BFD_RELOC_XTENSA_JMP_SLOT
6553 BFD_RELOC_XTENSA_RELATIVE
6555 Xtensa relocations for ELF shared objects.
6557 BFD_RELOC_XTENSA_PLT
6559 Xtensa relocation used in ELF object files for symbols that may require
6560 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6562 BFD_RELOC_XTENSA_DIFF8
6564 BFD_RELOC_XTENSA_DIFF16
6566 BFD_RELOC_XTENSA_DIFF32
6568 Xtensa relocations for backward compatibility. These have been replaced
6569 by BFD_RELOC_XTENSA_PDIFF and BFD_RELOC_XTENSA_NDIFF.
6570 Xtensa relocations to mark the difference of two local symbols.
6571 These are only needed to support linker relaxation and can be ignored
6572 when not relaxing. The field is set to the value of the difference
6573 assuming no relaxation. The relocation encodes the position of the
6574 first symbol so the linker can determine whether to adjust the field
6577 BFD_RELOC_XTENSA_SLOT0_OP
6579 BFD_RELOC_XTENSA_SLOT1_OP
6581 BFD_RELOC_XTENSA_SLOT2_OP
6583 BFD_RELOC_XTENSA_SLOT3_OP
6585 BFD_RELOC_XTENSA_SLOT4_OP
6587 BFD_RELOC_XTENSA_SLOT5_OP
6589 BFD_RELOC_XTENSA_SLOT6_OP
6591 BFD_RELOC_XTENSA_SLOT7_OP
6593 BFD_RELOC_XTENSA_SLOT8_OP
6595 BFD_RELOC_XTENSA_SLOT9_OP
6597 BFD_RELOC_XTENSA_SLOT10_OP
6599 BFD_RELOC_XTENSA_SLOT11_OP
6601 BFD_RELOC_XTENSA_SLOT12_OP
6603 BFD_RELOC_XTENSA_SLOT13_OP
6605 BFD_RELOC_XTENSA_SLOT14_OP
6607 Generic Xtensa relocations for instruction operands. Only the slot
6608 number is encoded in the relocation. The relocation applies to the
6609 last PC-relative immediate operand, or if there are no PC-relative
6610 immediates, to the last immediate operand.
6612 BFD_RELOC_XTENSA_SLOT0_ALT
6614 BFD_RELOC_XTENSA_SLOT1_ALT
6616 BFD_RELOC_XTENSA_SLOT2_ALT
6618 BFD_RELOC_XTENSA_SLOT3_ALT
6620 BFD_RELOC_XTENSA_SLOT4_ALT
6622 BFD_RELOC_XTENSA_SLOT5_ALT
6624 BFD_RELOC_XTENSA_SLOT6_ALT
6626 BFD_RELOC_XTENSA_SLOT7_ALT
6628 BFD_RELOC_XTENSA_SLOT8_ALT
6630 BFD_RELOC_XTENSA_SLOT9_ALT
6632 BFD_RELOC_XTENSA_SLOT10_ALT
6634 BFD_RELOC_XTENSA_SLOT11_ALT
6636 BFD_RELOC_XTENSA_SLOT12_ALT
6638 BFD_RELOC_XTENSA_SLOT13_ALT
6640 BFD_RELOC_XTENSA_SLOT14_ALT
6642 Alternate Xtensa relocations. Only the slot is encoded in the
6643 relocation. The meaning of these relocations is opcode-specific.
6645 BFD_RELOC_XTENSA_OP0
6647 BFD_RELOC_XTENSA_OP1
6649 BFD_RELOC_XTENSA_OP2
6651 Xtensa relocations for backward compatibility. These have all been
6652 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6654 BFD_RELOC_XTENSA_ASM_EXPAND
6656 Xtensa relocation to mark that the assembler expanded the
6657 instructions from an original target. The expansion size is
6658 encoded in the reloc size.
6660 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6662 Xtensa relocation to mark that the linker should simplify
6663 assembler-expanded instructions. This is commonly used
6664 internally by the linker after analysis of a
6665 BFD_RELOC_XTENSA_ASM_EXPAND.
6667 BFD_RELOC_XTENSA_TLSDESC_FN
6669 BFD_RELOC_XTENSA_TLSDESC_ARG
6671 BFD_RELOC_XTENSA_TLS_DTPOFF
6673 BFD_RELOC_XTENSA_TLS_TPOFF
6675 BFD_RELOC_XTENSA_TLS_FUNC
6677 BFD_RELOC_XTENSA_TLS_ARG
6679 BFD_RELOC_XTENSA_TLS_CALL
6681 Xtensa TLS relocations.
6683 BFD_RELOC_XTENSA_PDIFF8
6685 BFD_RELOC_XTENSA_PDIFF16
6687 BFD_RELOC_XTENSA_PDIFF32
6689 BFD_RELOC_XTENSA_NDIFF8
6691 BFD_RELOC_XTENSA_NDIFF16
6693 BFD_RELOC_XTENSA_NDIFF32
6695 Xtensa relocations to mark the difference of two local symbols.
6696 These are only needed to support linker relaxation and can be ignored
6697 when not relaxing. The field is set to the value of the difference
6698 assuming no relaxation. The relocation encodes the position of the
6699 subtracted symbol so the linker can determine whether to adjust the field
6700 value. PDIFF relocations are used for positive differences, NDIFF
6701 relocations are used for negative differences. The difference value
6702 is treated as unsigned with these relocation types, giving full
6708 8 bit signed offset in (ix+d) or (iy+d).
6712 First 8 bits of multibyte (32, 24 or 16 bit) value.
6716 Second 8 bits of multibyte (32, 24 or 16 bit) value.
6720 Third 8 bits of multibyte (32 or 24 bit) value.
6724 Fourth 8 bits of multibyte (32 bit) value.
6728 Lowest 16 bits of multibyte (32 or 24 bit) value.
6732 Highest 16 bits of multibyte (32 or 24 bit) value.
6736 Like BFD_RELOC_16 but big-endian.
6754 BFD_RELOC_LM32_BRANCH
6756 BFD_RELOC_LM32_16_GOT
6758 BFD_RELOC_LM32_GOTOFF_HI16
6760 BFD_RELOC_LM32_GOTOFF_LO16
6764 BFD_RELOC_LM32_GLOB_DAT
6766 BFD_RELOC_LM32_JMP_SLOT
6768 BFD_RELOC_LM32_RELATIVE
6770 Lattice Mico32 relocations.
6773 BFD_RELOC_MACH_O_SECTDIFF
6775 Difference between two section addreses. Must be followed by a
6776 BFD_RELOC_MACH_O_PAIR.
6778 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6780 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6782 BFD_RELOC_MACH_O_PAIR
6784 Pair of relocation. Contains the first symbol.
6786 BFD_RELOC_MACH_O_SUBTRACTOR32
6788 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6790 BFD_RELOC_MACH_O_SUBTRACTOR64
6792 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6795 BFD_RELOC_MACH_O_X86_64_BRANCH32
6797 BFD_RELOC_MACH_O_X86_64_BRANCH8
6799 PCREL relocations. They are marked as branch to create PLT entry if
6802 BFD_RELOC_MACH_O_X86_64_GOT
6804 Used when referencing a GOT entry.
6806 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6808 Used when loading a GOT entry with movq. It is specially marked so that
6809 the linker could optimize the movq to a leaq if possible.
6811 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6813 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6815 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6817 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6819 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6821 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6823 BFD_RELOC_MACH_O_X86_64_TLV
6825 Used when referencing a TLV entry.
6829 BFD_RELOC_MACH_O_ARM64_ADDEND
6831 Addend for PAGE or PAGEOFF.
6833 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6835 Relative offset to page of GOT slot.
6837 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6839 Relative offset within page of GOT slot.
6841 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6843 Address of a GOT entry.
6846 BFD_RELOC_MICROBLAZE_32_LO
6848 This is a 32 bit reloc for the microblaze that stores the
6849 low 16 bits of a value
6851 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6853 This is a 32 bit pc-relative reloc for the microblaze that
6854 stores the low 16 bits of a value
6856 BFD_RELOC_MICROBLAZE_32_ROSDA
6858 This is a 32 bit reloc for the microblaze that stores a
6859 value relative to the read-only small data area anchor
6861 BFD_RELOC_MICROBLAZE_32_RWSDA
6863 This is a 32 bit reloc for the microblaze that stores a
6864 value relative to the read-write small data area anchor
6866 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6868 This is a 32 bit reloc for the microblaze to handle
6869 expressions of the form "Symbol Op Symbol"
6871 BFD_RELOC_MICROBLAZE_64_NONE
6873 This is a 64 bit reloc that stores the 32 bit pc relative
6874 value in two words (with an imm instruction). No relocation is
6875 done here - only used for relaxing
6877 BFD_RELOC_MICROBLAZE_64_GOTPC
6879 This is a 64 bit reloc that stores the 32 bit pc relative
6880 value in two words (with an imm instruction). The relocation is
6881 PC-relative GOT offset
6883 BFD_RELOC_MICROBLAZE_64_GOT
6885 This is a 64 bit reloc that stores the 32 bit pc relative
6886 value in two words (with an imm instruction). The relocation is
6889 BFD_RELOC_MICROBLAZE_64_PLT
6891 This is a 64 bit reloc that stores the 32 bit pc relative
6892 value in two words (with an imm instruction). The relocation is
6893 PC-relative offset into PLT
6895 BFD_RELOC_MICROBLAZE_64_GOTOFF
6897 This is a 64 bit reloc that stores the 32 bit GOT relative
6898 value in two words (with an imm instruction). The relocation is
6899 relative offset from _GLOBAL_OFFSET_TABLE_
6901 BFD_RELOC_MICROBLAZE_32_GOTOFF
6903 This is a 32 bit reloc that stores the 32 bit GOT relative
6904 value in a word. The relocation is relative offset from
6905 _GLOBAL_OFFSET_TABLE_
6907 BFD_RELOC_MICROBLAZE_COPY
6909 This is used to tell the dynamic linker to copy the value out of
6910 the dynamic object into the runtime process image.
6912 BFD_RELOC_MICROBLAZE_64_TLS
6916 BFD_RELOC_MICROBLAZE_64_TLSGD
6918 This is a 64 bit reloc that stores the 32 bit GOT relative value
6919 of the GOT TLS GD info entry in two words (with an imm instruction). The
6920 relocation is GOT offset.
6922 BFD_RELOC_MICROBLAZE_64_TLSLD
6924 This is a 64 bit reloc that stores the 32 bit GOT relative value
6925 of the GOT TLS LD info entry in two words (with an imm instruction). The
6926 relocation is GOT offset.
6928 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6930 This is a 32 bit reloc that stores the Module ID to GOT(n).
6932 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6934 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6936 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6938 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6941 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6943 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6944 to two words (uses imm instruction).
6946 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6948 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6949 to two words (uses imm instruction).
6951 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6953 This is a 64 bit reloc that stores the 32 bit pc relative
6954 value in two words (with an imm instruction). The relocation is
6955 PC-relative offset from start of TEXT.
6957 BFD_RELOC_MICROBLAZE_64_TEXTREL
6959 This is a 64 bit reloc that stores the 32 bit offset
6960 value in two words (with an imm instruction). The relocation is
6961 relative offset from start of TEXT.
6964 BFD_RELOC_AARCH64_RELOC_START
6966 AArch64 pseudo relocation code to mark the start of the AArch64
6967 relocation enumerators. N.B. the order of the enumerators is
6968 important as several tables in the AArch64 bfd backend are indexed
6969 by these enumerators; make sure they are all synced.
6971 BFD_RELOC_AARCH64_NULL
6973 Deprecated AArch64 null relocation code.
6975 BFD_RELOC_AARCH64_NONE
6977 AArch64 null relocation code.
6979 BFD_RELOC_AARCH64_64
6981 BFD_RELOC_AARCH64_32
6983 BFD_RELOC_AARCH64_16
6985 Basic absolute relocations of N bits. These are equivalent to
6986 BFD_RELOC_N and they were added to assist the indexing of the howto
6989 BFD_RELOC_AARCH64_64_PCREL
6991 BFD_RELOC_AARCH64_32_PCREL
6993 BFD_RELOC_AARCH64_16_PCREL
6995 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6996 and they were added to assist the indexing of the howto table.
6998 BFD_RELOC_AARCH64_MOVW_G0
7000 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
7001 of an unsigned address/value.
7003 BFD_RELOC_AARCH64_MOVW_G0_NC
7005 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
7006 an address/value. No overflow checking.
7008 BFD_RELOC_AARCH64_MOVW_G1
7010 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
7011 of an unsigned address/value.
7013 BFD_RELOC_AARCH64_MOVW_G1_NC
7015 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7016 of an address/value. No overflow checking.
7018 BFD_RELOC_AARCH64_MOVW_G2
7020 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7021 of an unsigned address/value.
7023 BFD_RELOC_AARCH64_MOVW_G2_NC
7025 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7026 of an address/value. No overflow checking.
7028 BFD_RELOC_AARCH64_MOVW_G3
7030 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7031 of a signed or unsigned address/value.
7033 BFD_RELOC_AARCH64_MOVW_G0_S
7035 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7036 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7039 BFD_RELOC_AARCH64_MOVW_G1_S
7041 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7042 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7045 BFD_RELOC_AARCH64_MOVW_G2_S
7047 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7048 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7051 BFD_RELOC_AARCH64_MOVW_PREL_G0
7053 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7054 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7057 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7059 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7060 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7063 BFD_RELOC_AARCH64_MOVW_PREL_G1
7065 AArch64 MOVK instruction with most significant bits 16 to 31
7068 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7070 AArch64 MOVK instruction with most significant bits 16 to 31
7073 BFD_RELOC_AARCH64_MOVW_PREL_G2
7075 AArch64 MOVK instruction with most significant bits 32 to 47
7078 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7080 AArch64 MOVK instruction with most significant bits 32 to 47
7083 BFD_RELOC_AARCH64_MOVW_PREL_G3
7085 AArch64 MOVK instruction with most significant bits 47 to 63
7088 BFD_RELOC_AARCH64_LD_LO19_PCREL
7090 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7091 offset. The lowest two bits must be zero and are not stored in the
7092 instruction, giving a 21 bit signed byte offset.
7094 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7096 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7098 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7100 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7101 offset, giving a 4KB aligned page base address.
7103 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7105 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7106 offset, giving a 4KB aligned page base address, but with no overflow
7109 BFD_RELOC_AARCH64_ADD_LO12
7111 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7112 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7114 BFD_RELOC_AARCH64_LDST8_LO12
7116 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7117 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7119 BFD_RELOC_AARCH64_TSTBR14
7121 AArch64 14 bit pc-relative test bit and branch.
7122 The lowest two bits must be zero and are not stored in the instruction,
7123 giving a 16 bit signed byte offset.
7125 BFD_RELOC_AARCH64_BRANCH19
7127 AArch64 19 bit pc-relative conditional branch and compare & branch.
7128 The lowest two bits must be zero and are not stored in the instruction,
7129 giving a 21 bit signed byte offset.
7131 BFD_RELOC_AARCH64_JUMP26
7133 AArch64 26 bit pc-relative unconditional branch.
7134 The lowest two bits must be zero and are not stored in the instruction,
7135 giving a 28 bit signed byte offset.
7137 BFD_RELOC_AARCH64_CALL26
7139 AArch64 26 bit pc-relative unconditional branch and link.
7140 The lowest two bits must be zero and are not stored in the instruction,
7141 giving a 28 bit signed byte offset.
7143 BFD_RELOC_AARCH64_LDST16_LO12
7145 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7146 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7148 BFD_RELOC_AARCH64_LDST32_LO12
7150 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7151 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7153 BFD_RELOC_AARCH64_LDST64_LO12
7155 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7156 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7158 BFD_RELOC_AARCH64_LDST128_LO12
7160 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7161 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7163 BFD_RELOC_AARCH64_GOT_LD_PREL19
7165 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7166 offset of the global offset table entry for a symbol. The lowest two
7167 bits must be zero and are not stored in the instruction, giving a 21
7168 bit signed byte offset. This relocation type requires signed overflow
7171 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7173 Get to the page base of the global offset table entry for a symbol as
7174 part of an ADRP instruction using a 21 bit PC relative value.Used in
7175 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7177 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7179 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7180 the GOT entry for this symbol. Used in conjunction with
7181 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7183 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7185 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7186 the GOT entry for this symbol. Used in conjunction with
7187 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7189 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7191 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7192 for this symbol. Valid in LP64 ABI only.
7194 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7196 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7197 for this symbol. Valid in LP64 ABI only.
7199 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7201 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7202 the GOT entry for this symbol. Valid in LP64 ABI only.
7204 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7206 Scaled 14 bit byte offset to the page base of the global offset table.
7208 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7210 Scaled 15 bit byte offset to the page base of the global offset table.
7212 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7214 Get to the page base of the global offset table entry for a symbols
7215 tls_index structure as part of an adrp instruction using a 21 bit PC
7216 relative value. Used in conjunction with
7217 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7219 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7221 AArch64 TLS General Dynamic
7223 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7225 Unsigned 12 bit byte offset to global offset table entry for a symbols
7226 tls_index structure. Used in conjunction with
7227 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7229 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7231 AArch64 TLS General Dynamic relocation.
7233 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7235 AArch64 TLS General Dynamic relocation.
7237 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7239 AArch64 TLS INITIAL EXEC relocation.
7241 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7243 AArch64 TLS INITIAL EXEC relocation.
7245 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7247 AArch64 TLS INITIAL EXEC relocation.
7249 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7251 AArch64 TLS INITIAL EXEC relocation.
7253 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7255 AArch64 TLS INITIAL EXEC relocation.
7257 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7259 AArch64 TLS INITIAL EXEC relocation.
7261 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7263 bit[23:12] of byte offset to module TLS base address.
7265 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7267 Unsigned 12 bit byte offset to module TLS base address.
7269 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7271 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7273 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7275 Unsigned 12 bit byte offset to global offset table entry for a symbols
7276 tls_index structure. Used in conjunction with
7277 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7279 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7281 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7284 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7286 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7288 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7290 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7293 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7295 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7297 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7299 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7302 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7304 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7306 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7308 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7311 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7313 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7315 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7317 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7320 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7322 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7324 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7326 bit[15:0] of byte offset to module TLS base address.
7328 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7330 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7332 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7334 bit[31:16] of byte offset to module TLS base address.
7336 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7338 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7340 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7342 bit[47:32] of byte offset to module TLS base address.
7344 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7346 AArch64 TLS LOCAL EXEC relocation.
7348 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7350 AArch64 TLS LOCAL EXEC relocation.
7352 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7354 AArch64 TLS LOCAL EXEC relocation.
7356 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7358 AArch64 TLS LOCAL EXEC relocation.
7360 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7362 AArch64 TLS LOCAL EXEC relocation.
7364 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7366 AArch64 TLS LOCAL EXEC relocation.
7368 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7370 AArch64 TLS LOCAL EXEC relocation.
7372 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7374 AArch64 TLS LOCAL EXEC relocation.
7376 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7378 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7381 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7383 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7385 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7387 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7390 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7392 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7394 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7396 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7399 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7401 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7403 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7405 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7408 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7410 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7412 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7414 AArch64 TLS DESC relocation.
7416 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7418 AArch64 TLS DESC relocation.
7420 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7422 AArch64 TLS DESC relocation.
7424 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7426 AArch64 TLS DESC relocation.
7428 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7430 AArch64 TLS DESC relocation.
7432 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7434 AArch64 TLS DESC relocation.
7436 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7438 AArch64 TLS DESC relocation.
7440 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7442 AArch64 TLS DESC relocation.
7444 BFD_RELOC_AARCH64_TLSDESC_LDR
7446 AArch64 TLS DESC relocation.
7448 BFD_RELOC_AARCH64_TLSDESC_ADD
7450 AArch64 TLS DESC relocation.
7452 BFD_RELOC_AARCH64_TLSDESC_CALL
7454 AArch64 TLS DESC relocation.
7456 BFD_RELOC_AARCH64_COPY
7458 AArch64 TLS relocation.
7460 BFD_RELOC_AARCH64_GLOB_DAT
7462 AArch64 TLS relocation.
7464 BFD_RELOC_AARCH64_JUMP_SLOT
7466 AArch64 TLS relocation.
7468 BFD_RELOC_AARCH64_RELATIVE
7470 AArch64 TLS relocation.
7472 BFD_RELOC_AARCH64_TLS_DTPMOD
7474 AArch64 TLS relocation.
7476 BFD_RELOC_AARCH64_TLS_DTPREL
7478 AArch64 TLS relocation.
7480 BFD_RELOC_AARCH64_TLS_TPREL
7482 AArch64 TLS relocation.
7484 BFD_RELOC_AARCH64_TLSDESC
7486 AArch64 TLS relocation.
7488 BFD_RELOC_AARCH64_IRELATIVE
7490 AArch64 support for STT_GNU_IFUNC.
7492 BFD_RELOC_AARCH64_RELOC_END
7494 AArch64 pseudo relocation code to mark the end of the AArch64
7495 relocation enumerators that have direct mapping to ELF reloc codes.
7496 There are a few more enumerators after this one; those are mainly
7497 used by the AArch64 assembler for the internal fixup or to select
7498 one of the above enumerators.
7500 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7502 AArch64 pseudo relocation code to be used internally by the AArch64
7503 assembler and not (currently) written to any object files.
7505 BFD_RELOC_AARCH64_LDST_LO12
7507 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7508 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7510 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7512 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7513 used internally by the AArch64 assembler and not (currently) written to
7516 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7518 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7520 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7522 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7523 used internally by the AArch64 assembler and not (currently) written to
7526 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7528 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7530 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7532 AArch64 pseudo relocation code to be used internally by the AArch64
7533 assembler and not (currently) written to any object files.
7535 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7537 AArch64 pseudo relocation code to be used internally by the AArch64
7538 assembler and not (currently) written to any object files.
7540 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7542 AArch64 pseudo relocation code to be used internally by the AArch64
7543 assembler and not (currently) written to any object files.
7545 BFD_RELOC_TILEPRO_COPY
7547 BFD_RELOC_TILEPRO_GLOB_DAT
7549 BFD_RELOC_TILEPRO_JMP_SLOT
7551 BFD_RELOC_TILEPRO_RELATIVE
7553 BFD_RELOC_TILEPRO_BROFF_X1
7555 BFD_RELOC_TILEPRO_JOFFLONG_X1
7557 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7559 BFD_RELOC_TILEPRO_IMM8_X0
7561 BFD_RELOC_TILEPRO_IMM8_Y0
7563 BFD_RELOC_TILEPRO_IMM8_X1
7565 BFD_RELOC_TILEPRO_IMM8_Y1
7567 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7569 BFD_RELOC_TILEPRO_MT_IMM15_X1
7571 BFD_RELOC_TILEPRO_MF_IMM15_X1
7573 BFD_RELOC_TILEPRO_IMM16_X0
7575 BFD_RELOC_TILEPRO_IMM16_X1
7577 BFD_RELOC_TILEPRO_IMM16_X0_LO
7579 BFD_RELOC_TILEPRO_IMM16_X1_LO
7581 BFD_RELOC_TILEPRO_IMM16_X0_HI
7583 BFD_RELOC_TILEPRO_IMM16_X1_HI
7585 BFD_RELOC_TILEPRO_IMM16_X0_HA
7587 BFD_RELOC_TILEPRO_IMM16_X1_HA
7589 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7591 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7593 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7595 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7597 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7599 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7601 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7603 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7605 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7607 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7609 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7611 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7613 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7615 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7617 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7619 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7621 BFD_RELOC_TILEPRO_MMSTART_X0
7623 BFD_RELOC_TILEPRO_MMEND_X0
7625 BFD_RELOC_TILEPRO_MMSTART_X1
7627 BFD_RELOC_TILEPRO_MMEND_X1
7629 BFD_RELOC_TILEPRO_SHAMT_X0
7631 BFD_RELOC_TILEPRO_SHAMT_X1
7633 BFD_RELOC_TILEPRO_SHAMT_Y0
7635 BFD_RELOC_TILEPRO_SHAMT_Y1
7637 BFD_RELOC_TILEPRO_TLS_GD_CALL
7639 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7641 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7643 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7645 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7647 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7649 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7651 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7653 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7655 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7657 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7659 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7661 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7663 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7665 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7667 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7669 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7671 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7673 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7675 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7677 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7679 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7681 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7683 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7685 BFD_RELOC_TILEPRO_TLS_TPOFF32
7687 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7689 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7691 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7693 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7695 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7697 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7699 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7701 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7703 Tilera TILEPro Relocations.
7705 BFD_RELOC_TILEGX_HW0
7707 BFD_RELOC_TILEGX_HW1
7709 BFD_RELOC_TILEGX_HW2
7711 BFD_RELOC_TILEGX_HW3
7713 BFD_RELOC_TILEGX_HW0_LAST
7715 BFD_RELOC_TILEGX_HW1_LAST
7717 BFD_RELOC_TILEGX_HW2_LAST
7719 BFD_RELOC_TILEGX_COPY
7721 BFD_RELOC_TILEGX_GLOB_DAT
7723 BFD_RELOC_TILEGX_JMP_SLOT
7725 BFD_RELOC_TILEGX_RELATIVE
7727 BFD_RELOC_TILEGX_BROFF_X1
7729 BFD_RELOC_TILEGX_JUMPOFF_X1
7731 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7733 BFD_RELOC_TILEGX_IMM8_X0
7735 BFD_RELOC_TILEGX_IMM8_Y0
7737 BFD_RELOC_TILEGX_IMM8_X1
7739 BFD_RELOC_TILEGX_IMM8_Y1
7741 BFD_RELOC_TILEGX_DEST_IMM8_X1
7743 BFD_RELOC_TILEGX_MT_IMM14_X1
7745 BFD_RELOC_TILEGX_MF_IMM14_X1
7747 BFD_RELOC_TILEGX_MMSTART_X0
7749 BFD_RELOC_TILEGX_MMEND_X0
7751 BFD_RELOC_TILEGX_SHAMT_X0
7753 BFD_RELOC_TILEGX_SHAMT_X1
7755 BFD_RELOC_TILEGX_SHAMT_Y0
7757 BFD_RELOC_TILEGX_SHAMT_Y1
7759 BFD_RELOC_TILEGX_IMM16_X0_HW0
7761 BFD_RELOC_TILEGX_IMM16_X1_HW0
7763 BFD_RELOC_TILEGX_IMM16_X0_HW1
7765 BFD_RELOC_TILEGX_IMM16_X1_HW1
7767 BFD_RELOC_TILEGX_IMM16_X0_HW2
7769 BFD_RELOC_TILEGX_IMM16_X1_HW2
7771 BFD_RELOC_TILEGX_IMM16_X0_HW3
7773 BFD_RELOC_TILEGX_IMM16_X1_HW3
7775 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7777 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7779 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7781 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7783 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7785 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7787 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7789 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7791 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7793 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7795 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7797 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7799 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7801 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7803 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7805 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7807 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7809 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7811 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7813 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7815 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7817 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7819 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7821 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7823 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7825 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7827 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7829 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7831 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7833 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7835 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7837 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7839 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7841 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7843 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7845 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7847 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7849 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7851 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7853 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7855 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7857 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7859 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7861 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7863 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7865 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7867 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7869 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7871 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7873 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7875 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7877 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7879 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7881 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7883 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7885 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7887 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7889 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7891 BFD_RELOC_TILEGX_TLS_DTPMOD64
7893 BFD_RELOC_TILEGX_TLS_DTPOFF64
7895 BFD_RELOC_TILEGX_TLS_TPOFF64
7897 BFD_RELOC_TILEGX_TLS_DTPMOD32
7899 BFD_RELOC_TILEGX_TLS_DTPOFF32
7901 BFD_RELOC_TILEGX_TLS_TPOFF32
7903 BFD_RELOC_TILEGX_TLS_GD_CALL
7905 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7907 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7909 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7911 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7913 BFD_RELOC_TILEGX_TLS_IE_LOAD
7915 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7917 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7919 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7921 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7923 Tilera TILE-Gx Relocations.
7932 BFD_RELOC_BPF_DISP16
7934 BFD_RELOC_BPF_DISP32
7936 Linux eBPF relocations.
7939 BFD_RELOC_EPIPHANY_SIMM8
7941 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7943 BFD_RELOC_EPIPHANY_SIMM24
7945 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7947 BFD_RELOC_EPIPHANY_HIGH
7949 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7951 BFD_RELOC_EPIPHANY_LOW
7953 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7955 BFD_RELOC_EPIPHANY_SIMM11
7957 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7959 BFD_RELOC_EPIPHANY_IMM11
7961 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7963 BFD_RELOC_EPIPHANY_IMM8
7965 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7968 BFD_RELOC_VISIUM_HI16
7970 BFD_RELOC_VISIUM_LO16
7972 BFD_RELOC_VISIUM_IM16
7974 BFD_RELOC_VISIUM_REL16
7976 BFD_RELOC_VISIUM_HI16_PCREL
7978 BFD_RELOC_VISIUM_LO16_PCREL
7980 BFD_RELOC_VISIUM_IM16_PCREL
7985 BFD_RELOC_WASM32_LEB128
7987 BFD_RELOC_WASM32_LEB128_GOT
7989 BFD_RELOC_WASM32_LEB128_GOT_CODE
7991 BFD_RELOC_WASM32_LEB128_PLT
7993 BFD_RELOC_WASM32_PLT_INDEX
7995 BFD_RELOC_WASM32_ABS32_CODE
7997 BFD_RELOC_WASM32_COPY
7999 BFD_RELOC_WASM32_CODE_POINTER
8001 BFD_RELOC_WASM32_INDEX
8003 BFD_RELOC_WASM32_PLT_SIG
8005 WebAssembly relocations.
8008 BFD_RELOC_CKCORE_NONE
8010 BFD_RELOC_CKCORE_ADDR32
8012 BFD_RELOC_CKCORE_PCREL_IMM8BY4
8014 BFD_RELOC_CKCORE_PCREL_IMM11BY2
8016 BFD_RELOC_CKCORE_PCREL_IMM4BY2
8018 BFD_RELOC_CKCORE_PCREL32
8020 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
8022 BFD_RELOC_CKCORE_GNU_VTINHERIT
8024 BFD_RELOC_CKCORE_GNU_VTENTRY
8026 BFD_RELOC_CKCORE_RELATIVE
8028 BFD_RELOC_CKCORE_COPY
8030 BFD_RELOC_CKCORE_GLOB_DAT
8032 BFD_RELOC_CKCORE_JUMP_SLOT
8034 BFD_RELOC_CKCORE_GOTOFF
8036 BFD_RELOC_CKCORE_GOTPC
8038 BFD_RELOC_CKCORE_GOT32
8040 BFD_RELOC_CKCORE_PLT32
8042 BFD_RELOC_CKCORE_ADDRGOT
8044 BFD_RELOC_CKCORE_ADDRPLT
8046 BFD_RELOC_CKCORE_PCREL_IMM26BY2
8048 BFD_RELOC_CKCORE_PCREL_IMM16BY2
8050 BFD_RELOC_CKCORE_PCREL_IMM16BY4
8052 BFD_RELOC_CKCORE_PCREL_IMM10BY2
8054 BFD_RELOC_CKCORE_PCREL_IMM10BY4
8056 BFD_RELOC_CKCORE_ADDR_HI16
8058 BFD_RELOC_CKCORE_ADDR_LO16
8060 BFD_RELOC_CKCORE_GOTPC_HI16
8062 BFD_RELOC_CKCORE_GOTPC_LO16
8064 BFD_RELOC_CKCORE_GOTOFF_HI16
8066 BFD_RELOC_CKCORE_GOTOFF_LO16
8068 BFD_RELOC_CKCORE_GOT12
8070 BFD_RELOC_CKCORE_GOT_HI16
8072 BFD_RELOC_CKCORE_GOT_LO16
8074 BFD_RELOC_CKCORE_PLT12
8076 BFD_RELOC_CKCORE_PLT_HI16
8078 BFD_RELOC_CKCORE_PLT_LO16
8080 BFD_RELOC_CKCORE_ADDRGOT_HI16
8082 BFD_RELOC_CKCORE_ADDRGOT_LO16
8084 BFD_RELOC_CKCORE_ADDRPLT_HI16
8086 BFD_RELOC_CKCORE_ADDRPLT_LO16
8088 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
8090 BFD_RELOC_CKCORE_TOFFSET_LO16
8092 BFD_RELOC_CKCORE_DOFFSET_LO16
8094 BFD_RELOC_CKCORE_PCREL_IMM18BY2
8096 BFD_RELOC_CKCORE_DOFFSET_IMM18
8098 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
8100 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
8102 BFD_RELOC_CKCORE_GOTOFF_IMM18
8104 BFD_RELOC_CKCORE_GOT_IMM18BY4
8106 BFD_RELOC_CKCORE_PLT_IMM18BY4
8108 BFD_RELOC_CKCORE_PCREL_IMM7BY4
8110 BFD_RELOC_CKCORE_TLS_LE32
8112 BFD_RELOC_CKCORE_TLS_IE32
8114 BFD_RELOC_CKCORE_TLS_GD32
8116 BFD_RELOC_CKCORE_TLS_LDM32
8118 BFD_RELOC_CKCORE_TLS_LDO32
8120 BFD_RELOC_CKCORE_TLS_DTPMOD32
8122 BFD_RELOC_CKCORE_TLS_DTPOFF32
8124 BFD_RELOC_CKCORE_TLS_TPOFF32
8126 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
8128 BFD_RELOC_CKCORE_NOJSRI
8130 BFD_RELOC_CKCORE_CALLGRAPH
8132 BFD_RELOC_CKCORE_IRELATIVE
8134 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8136 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8146 BFD_RELOC_LARCH_TLS_DTPMOD32
8148 BFD_RELOC_LARCH_TLS_DTPREL32
8150 BFD_RELOC_LARCH_TLS_DTPMOD64
8152 BFD_RELOC_LARCH_TLS_DTPREL64
8154 BFD_RELOC_LARCH_TLS_TPREL32
8156 BFD_RELOC_LARCH_TLS_TPREL64
8158 BFD_RELOC_LARCH_MARK_LA
8160 BFD_RELOC_LARCH_MARK_PCREL
8162 BFD_RELOC_LARCH_SOP_PUSH_PCREL
8164 BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE
8166 BFD_RELOC_LARCH_SOP_PUSH_DUP
8168 BFD_RELOC_LARCH_SOP_PUSH_GPREL
8170 BFD_RELOC_LARCH_SOP_PUSH_TLS_TPREL
8172 BFD_RELOC_LARCH_SOP_PUSH_TLS_GOT
8174 BFD_RELOC_LARCH_SOP_PUSH_TLS_GD
8176 BFD_RELOC_LARCH_SOP_PUSH_PLT_PCREL
8178 BFD_RELOC_LARCH_SOP_ASSERT
8180 BFD_RELOC_LARCH_SOP_NOT
8182 BFD_RELOC_LARCH_SOP_SUB
8184 BFD_RELOC_LARCH_SOP_SL
8186 BFD_RELOC_LARCH_SOP_SR
8188 BFD_RELOC_LARCH_SOP_ADD
8190 BFD_RELOC_LARCH_SOP_AND
8192 BFD_RELOC_LARCH_SOP_IF_ELSE
8194 BFD_RELOC_LARCH_SOP_POP_32_S_10_5
8196 BFD_RELOC_LARCH_SOP_POP_32_U_10_12
8198 BFD_RELOC_LARCH_SOP_POP_32_S_10_12
8200 BFD_RELOC_LARCH_SOP_POP_32_S_10_16
8202 BFD_RELOC_LARCH_SOP_POP_32_S_10_16_S2
8204 BFD_RELOC_LARCH_SOP_POP_32_S_5_20
8206 BFD_RELOC_LARCH_SOP_POP_32_S_0_5_10_16_S2
8208 BFD_RELOC_LARCH_SOP_POP_32_S_0_10_10_16_S2
8210 BFD_RELOC_LARCH_SOP_POP_32_U
8212 BFD_RELOC_LARCH_ADD8
8214 BFD_RELOC_LARCH_ADD16
8216 BFD_RELOC_LARCH_ADD24
8218 BFD_RELOC_LARCH_ADD32
8220 BFD_RELOC_LARCH_ADD64
8222 BFD_RELOC_LARCH_SUB8
8224 BFD_RELOC_LARCH_SUB16
8226 BFD_RELOC_LARCH_SUB24
8228 BFD_RELOC_LARCH_SUB32
8230 BFD_RELOC_LARCH_SUB64
8240 BFD_RELOC_LARCH_ABS_HI20
8242 BFD_RELOC_LARCH_ABS_LO12
8244 BFD_RELOC_LARCH_ABS64_LO20
8246 BFD_RELOC_LARCH_ABS64_HI12
8249 BFD_RELOC_LARCH_PCALA_HI20
8251 BFD_RELOC_LARCH_PCALA_LO12
8253 BFD_RELOC_LARCH_PCALA64_LO20
8255 BFD_RELOC_LARCH_PCALA64_HI12
8258 BFD_RELOC_LARCH_GOT_PC_HI20
8260 BFD_RELOC_LARCH_GOT_PC_LO12
8262 BFD_RELOC_LARCH_GOT64_PC_LO20
8264 BFD_RELOC_LARCH_GOT64_PC_HI12
8266 BFD_RELOC_LARCH_GOT_HI20
8268 BFD_RELOC_LARCH_GOT_LO12
8270 BFD_RELOC_LARCH_GOT64_LO20
8272 BFD_RELOC_LARCH_GOT64_HI12
8275 BFD_RELOC_LARCH_TLS_LE_HI20
8277 BFD_RELOC_LARCH_TLS_LE_LO12
8279 BFD_RELOC_LARCH_TLS_LE64_LO20
8281 BFD_RELOC_LARCH_TLS_LE64_HI12
8283 BFD_RELOC_LARCH_TLS_IE_PC_HI20
8285 BFD_RELOC_LARCH_TLS_IE_PC_LO12
8287 BFD_RELOC_LARCH_TLS_IE64_PC_LO20
8289 BFD_RELOC_LARCH_TLS_IE64_PC_HI12
8291 BFD_RELOC_LARCH_TLS_IE_HI20
8293 BFD_RELOC_LARCH_TLS_IE_LO12
8295 BFD_RELOC_LARCH_TLS_IE64_LO20
8297 BFD_RELOC_LARCH_TLS_IE64_HI12
8299 BFD_RELOC_LARCH_TLS_LD_PC_HI20
8301 BFD_RELOC_LARCH_TLS_LD_HI20
8303 BFD_RELOC_LARCH_TLS_GD_PC_HI20
8305 BFD_RELOC_LARCH_TLS_GD_HI20
8308 BFD_RELOC_LARCH_32_PCREL
8311 BFD_RELOC_LARCH_RELAX
8320 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8325 bfd_reloc_type_lookup
8326 bfd_reloc_name_lookup
8329 reloc_howto_type *bfd_reloc_type_lookup
8330 (bfd *abfd, bfd_reloc_code_real_type code);
8331 reloc_howto_type *bfd_reloc_name_lookup
8332 (bfd *abfd, const char *reloc_name);
8335 Return a pointer to a howto structure which, when
8336 invoked, will perform the relocation @var{code} on data from the
8342 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8344 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
8348 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
8350 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
8353 static reloc_howto_type bfd_howto_32
=
8354 HOWTO (0, 00, 4, 32, false, 0, complain_overflow_dont
, 0, "VRT32", false, 0xffffffff, 0xffffffff, true);
8358 bfd_default_reloc_type_lookup
8361 reloc_howto_type *bfd_default_reloc_type_lookup
8362 (bfd *abfd, bfd_reloc_code_real_type code);
8365 Provides a default relocation lookup routine for any architecture.
8370 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8372 /* Very limited support is provided for relocs in generic targets
8373 such as elf32-little. FIXME: Should we always return NULL? */
8374 if (code
== BFD_RELOC_CTOR
8375 && bfd_arch_bits_per_address (abfd
) == 32)
8376 return &bfd_howto_32
;
8382 bfd_get_reloc_code_name
8385 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8388 Provides a printable name for the supplied relocation code.
8389 Useful mainly for printing error messages.
8393 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
8395 if (code
> BFD_RELOC_UNUSED
)
8397 return bfd_reloc_code_real_names
[code
];
8402 bfd_generic_relax_section
8405 bool bfd_generic_relax_section
8408 struct bfd_link_info *,
8412 Provides default handling for relaxing for back ends which
8417 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8418 asection
*section ATTRIBUTE_UNUSED
,
8419 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8422 if (bfd_link_relocatable (link_info
))
8423 (*link_info
->callbacks
->einfo
)
8424 (_("%P%F: --relax and -r may not be used together\n"));
8432 bfd_generic_gc_sections
8435 bool bfd_generic_gc_sections
8436 (bfd *, struct bfd_link_info *);
8439 Provides default handling for relaxing for back ends which
8440 don't do section gc -- i.e., does nothing.
8444 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8445 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8452 bfd_generic_lookup_section_flags
8455 bool bfd_generic_lookup_section_flags
8456 (struct bfd_link_info *, struct flag_info *, asection *);
8459 Provides default handling for section flags lookup
8460 -- i.e., does nothing.
8461 Returns FALSE if the section should be omitted, otherwise TRUE.
8465 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8466 struct flag_info
*flaginfo
,
8467 asection
*section ATTRIBUTE_UNUSED
)
8469 if (flaginfo
!= NULL
)
8471 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8479 bfd_generic_merge_sections
8482 bool bfd_generic_merge_sections
8483 (bfd *, struct bfd_link_info *);
8486 Provides default handling for SEC_MERGE section merging for back ends
8487 which don't have SEC_MERGE support -- i.e., does nothing.
8491 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8492 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8499 bfd_generic_get_relocated_section_contents
8502 bfd_byte *bfd_generic_get_relocated_section_contents
8504 struct bfd_link_info *link_info,
8505 struct bfd_link_order *link_order,
8511 Provides default handling of relocation effort for back ends
8512 which can't be bothered to do it efficiently.
8517 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8518 struct bfd_link_info
*link_info
,
8519 struct bfd_link_order
*link_order
,
8524 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8525 asection
*input_section
= link_order
->u
.indirect
.section
;
8527 arelent
**reloc_vector
;
8530 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8534 /* Read in the section. */
8535 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8541 if (reloc_size
== 0)
8544 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8545 if (reloc_vector
== NULL
)
8548 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8552 if (reloc_count
< 0)
8555 if (reloc_count
> 0)
8559 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8561 char *error_message
= NULL
;
8563 bfd_reloc_status_type r
;
8565 symbol
= *(*parent
)->sym_ptr_ptr
;
8566 /* PR ld/19628: A specially crafted input file
8567 can result in a NULL symbol pointer here. */
8570 link_info
->callbacks
->einfo
8571 /* xgettext:c-format */
8572 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8573 abfd
, input_section
, (* parent
)->address
);
8577 /* Zap reloc field when the symbol is from a discarded
8578 section, ignoring any addend. Do the same when called
8579 from bfd_simple_get_relocated_section_contents for
8580 undefined symbols in debug sections. This is to keep
8581 debug info reasonably sane, in particular so that
8582 DW_FORM_ref_addr to another file's .debug_info isn't
8583 confused with an offset into the current file's
8585 if ((symbol
->section
!= NULL
&& discarded_section (symbol
->section
))
8586 || (symbol
->section
== bfd_und_section_ptr
8587 && (input_section
->flags
& SEC_DEBUGGING
) != 0
8588 && link_info
->input_bfds
== link_info
->output_bfd
))
8591 static reloc_howto_type none_howto
8592 = HOWTO (0, 0, 0, 0, false, 0, complain_overflow_dont
, NULL
,
8593 "unused", false, 0, 0, false);
8595 off
= ((*parent
)->address
8596 * bfd_octets_per_byte (input_bfd
, input_section
));
8597 _bfd_clear_contents ((*parent
)->howto
, input_bfd
,
8598 input_section
, data
, off
);
8599 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8600 (*parent
)->addend
= 0;
8601 (*parent
)->howto
= &none_howto
;
8605 r
= bfd_perform_relocation (input_bfd
,
8609 relocatable
? abfd
: NULL
,
8614 asection
*os
= input_section
->output_section
;
8616 /* A partial link, so keep the relocs. */
8617 os
->orelocation
[os
->reloc_count
] = *parent
;
8621 if (r
!= bfd_reloc_ok
)
8625 case bfd_reloc_undefined
:
8626 (*link_info
->callbacks
->undefined_symbol
)
8627 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8628 input_bfd
, input_section
, (*parent
)->address
, true);
8630 case bfd_reloc_dangerous
:
8631 BFD_ASSERT (error_message
!= NULL
);
8632 (*link_info
->callbacks
->reloc_dangerous
)
8633 (link_info
, error_message
,
8634 input_bfd
, input_section
, (*parent
)->address
);
8636 case bfd_reloc_overflow
:
8637 (*link_info
->callbacks
->reloc_overflow
)
8639 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8640 (*parent
)->howto
->name
, (*parent
)->addend
,
8641 input_bfd
, input_section
, (*parent
)->address
);
8643 case bfd_reloc_outofrange
:
8645 This error can result when processing some partially
8646 complete binaries. Do not abort, but issue an error
8648 link_info
->callbacks
->einfo
8649 /* xgettext:c-format */
8650 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8651 abfd
, input_section
, * parent
);
8654 case bfd_reloc_notsupported
:
8656 This error can result when processing a corrupt binary.
8657 Do not abort. Issue an error message instead. */
8658 link_info
->callbacks
->einfo
8659 /* xgettext:c-format */
8660 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8661 abfd
, input_section
, * parent
);
8665 /* PR 17512; file: 90c2a92e.
8666 Report unexpected results, without aborting. */
8667 link_info
->callbacks
->einfo
8668 /* xgettext:c-format */
8669 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8670 abfd
, input_section
, * parent
, r
);
8678 free (reloc_vector
);
8682 free (reloc_vector
);
8688 _bfd_generic_set_reloc
8691 void _bfd_generic_set_reloc
8695 unsigned int count);
8698 Installs a new set of internal relocations in SECTION.
8702 _bfd_generic_set_reloc (bfd
*abfd ATTRIBUTE_UNUSED
,
8707 section
->orelocation
= relptr
;
8708 section
->reloc_count
= count
;
8713 _bfd_unrecognized_reloc
8716 bool _bfd_unrecognized_reloc
8719 unsigned int r_type);
8722 Reports an unrecognized reloc.
8723 Written as a function in order to reduce code duplication.
8724 Returns FALSE so that it can be called from a return statement.
8728 _bfd_unrecognized_reloc (bfd
* abfd
, sec_ptr section
, unsigned int r_type
)
8730 /* xgettext:c-format */
8731 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8732 abfd
, r_type
, section
);
8734 /* PR 21803: Suggest the most likely cause of this error. */
8735 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8736 BFD_VERSION_STRING
);
8738 bfd_set_error (bfd_error_bad_value
);
8743 _bfd_norelocs_bfd_reloc_type_lookup
8745 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED
)
8747 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8751 _bfd_norelocs_bfd_reloc_name_lookup (bfd
*abfd
,
8752 const char *reloc_name ATTRIBUTE_UNUSED
)
8754 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8758 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd
*abfd
,
8759 arelent
**relp ATTRIBUTE_UNUSED
,
8760 asymbol
**symp ATTRIBUTE_UNUSED
)
8762 return _bfd_long_bfd_n1_error (abfd
);