1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2014 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
56 typedef arelent, howto manager, Relocations, Relocations
61 This is the structure of a relocation entry:
65 .typedef enum bfd_reloc_status
67 . {* No errors detected. *}
70 . {* The relocation was performed, but there was an overflow. *}
73 . {* The address to relocate was not within the section supplied. *}
74 . bfd_reloc_outofrange,
76 . {* Used by special functions. *}
79 . {* Unsupported relocation size requested. *}
80 . bfd_reloc_notsupported,
85 . {* The symbol to relocate against was undefined. *}
86 . bfd_reloc_undefined,
88 . {* The relocation was performed, but may not be ok - presently
89 . generated only when linking i960 coff files with i960 b.out
90 . symbols. If this type is returned, the error_message argument
91 . to bfd_perform_relocation will be set. *}
94 . bfd_reloc_status_type;
97 .typedef struct reloc_cache_entry
99 . {* A pointer into the canonical table of pointers. *}
100 . struct bfd_symbol **sym_ptr_ptr;
102 . {* offset in section. *}
103 . bfd_size_type address;
105 . {* addend for relocation value. *}
108 . {* Pointer to how to perform the required relocation. *}
109 . reloc_howto_type *howto;
119 Here is a description of each of the fields within an <<arelent>>:
123 The symbol table pointer points to a pointer to the symbol
124 associated with the relocation request. It is the pointer
125 into the table returned by the back end's
126 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
127 referenced through a pointer to a pointer so that tools like
128 the linker can fix up all the symbols of the same name by
129 modifying only one pointer. The relocation routine looks in
130 the symbol and uses the base of the section the symbol is
131 attached to and the value of the symbol as the initial
132 relocation offset. If the symbol pointer is zero, then the
133 section provided is looked up.
137 The <<address>> field gives the offset in bytes from the base of
138 the section data which owns the relocation record to the first
139 byte of relocatable information. The actual data relocated
140 will be relative to this point; for example, a relocation
141 type which modifies the bottom two bytes of a four byte word
142 would not touch the first byte pointed to in a big endian
147 The <<addend>> is a value provided by the back end to be added (!)
148 to the relocation offset. Its interpretation is dependent upon
149 the howto. For example, on the 68k the code:
154 | return foo[0x12345678];
157 Could be compiled into:
160 | moveb @@#12345678,d0
165 This could create a reloc pointing to <<foo>>, but leave the
166 offset in the data, something like:
168 |RELOCATION RECORDS FOR [.text]:
172 |00000000 4e56 fffc ; linkw fp,#-4
173 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
174 |0000000a 49c0 ; extbl d0
175 |0000000c 4e5e ; unlk fp
178 Using coff and an 88k, some instructions don't have enough
179 space in them to represent the full address range, and
180 pointers have to be loaded in two parts. So you'd get something like:
182 | or.u r13,r0,hi16(_foo+0x12345678)
183 | ld.b r2,r13,lo16(_foo+0x12345678)
186 This should create two relocs, both pointing to <<_foo>>, and with
187 0x12340000 in their addend field. The data would consist of:
189 |RELOCATION RECORDS FOR [.text]:
191 |00000002 HVRT16 _foo+0x12340000
192 |00000006 LVRT16 _foo+0x12340000
194 |00000000 5da05678 ; or.u r13,r0,0x5678
195 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
196 |00000008 f400c001 ; jmp r1
198 The relocation routine digs out the value from the data, adds
199 it to the addend to get the original offset, and then adds the
200 value of <<_foo>>. Note that all 32 bits have to be kept around
201 somewhere, to cope with carry from bit 15 to bit 16.
203 One further example is the sparc and the a.out format. The
204 sparc has a similar problem to the 88k, in that some
205 instructions don't have room for an entire offset, but on the
206 sparc the parts are created in odd sized lumps. The designers of
207 the a.out format chose to not use the data within the section
208 for storing part of the offset; all the offset is kept within
209 the reloc. Anything in the data should be ignored.
212 | sethi %hi(_foo+0x12345678),%g2
213 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
217 Both relocs contain a pointer to <<foo>>, and the offsets
220 |RELOCATION RECORDS FOR [.text]:
222 |00000004 HI22 _foo+0x12345678
223 |00000008 LO10 _foo+0x12345678
225 |00000000 9de3bf90 ; save %sp,-112,%sp
226 |00000004 05000000 ; sethi %hi(_foo+0),%g2
227 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
228 |0000000c 81c7e008 ; ret
229 |00000010 81e80000 ; restore
233 The <<howto>> field can be imagined as a
234 relocation instruction. It is a pointer to a structure which
235 contains information on what to do with all of the other
236 information in the reloc record and data section. A back end
237 would normally have a relocation instruction set and turn
238 relocations into pointers to the correct structure on input -
239 but it would be possible to create each howto field on demand.
245 <<enum complain_overflow>>
247 Indicates what sort of overflow checking should be done when
248 performing a relocation.
252 .enum complain_overflow
254 . {* Do not complain on overflow. *}
255 . complain_overflow_dont,
257 . {* Complain if the value overflows when considered as a signed
258 . number one bit larger than the field. ie. A bitfield of N bits
259 . is allowed to represent -2**n to 2**n-1. *}
260 . complain_overflow_bitfield,
262 . {* Complain if the value overflows when considered as a signed
264 . complain_overflow_signed,
266 . {* Complain if the value overflows when considered as an
267 . unsigned number. *}
268 . complain_overflow_unsigned
277 The <<reloc_howto_type>> is a structure which contains all the
278 information that libbfd needs to know to tie up a back end's data.
281 .struct bfd_symbol; {* Forward declaration. *}
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's
287 . external idea of what a reloc number is stored
288 . in this field. For example, a PC relative word relocation
289 . in a coff environment has the type 023 - because that's
290 . what the outside world calls a R_PCRWORD reloc. *}
293 . {* The value the final relocation is shifted right by. This drops
294 . unwanted data from the relocation. *}
295 . unsigned int rightshift;
297 . {* The size of the item to be relocated. This is *not* a
298 . power-of-two measure. To get the number of bytes operated
299 . on by a type of relocation, use bfd_get_reloc_size. *}
302 . {* The number of bits in the item to be relocated. This is used
303 . when doing overflow checking. *}
304 . unsigned int bitsize;
306 . {* The relocation is relative to the field being relocated. *}
307 . bfd_boolean pc_relative;
309 . {* The bit position of the reloc value in the destination.
310 . The relocated value is left shifted by this amount. *}
311 . unsigned int bitpos;
313 . {* What type of overflow error should be checked for when
315 . enum complain_overflow complain_on_overflow;
317 . {* If this field is non null, then the supplied function is
318 . called rather than the normal function. This allows really
319 . strange relocation methods to be accommodated (e.g., i960 callj
321 . bfd_reloc_status_type (*special_function)
322 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
325 . {* The textual name of the relocation type. *}
328 . {* Some formats record a relocation addend in the section contents
329 . rather than with the relocation. For ELF formats this is the
330 . distinction between USE_REL and USE_RELA (though the code checks
331 . for USE_REL == 1/0). The value of this field is TRUE if the
332 . addend is recorded with the section contents; when performing a
333 . partial link (ld -r) the section contents (the data) will be
334 . modified. The value of this field is FALSE if addends are
335 . recorded with the relocation (in arelent.addend); when performing
336 . a partial link the relocation will be modified.
337 . All relocations for all ELF USE_RELA targets should set this field
338 . to FALSE (values of TRUE should be looked on with suspicion).
339 . However, the converse is not true: not all relocations of all ELF
340 . USE_REL targets set this field to TRUE. Why this is so is peculiar
341 . to each particular target. For relocs that aren't used in partial
342 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
343 . bfd_boolean partial_inplace;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should be zero. Non-zero values for ELF USE_RELA targets are
351 . bogus as in those cases the value in the dst_mask part of the
352 . section contents should be treated as garbage. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* When some formats create PC relative instructions, they leave
360 . the value of the pc of the place being relocated in the offset
361 . slot of the instruction, so that a PC relative relocation can
362 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
363 . Some formats leave the displacement part of an instruction
364 . empty (e.g., m88k bcs); this flag signals the fact. *}
365 . bfd_boolean pcrel_offset;
375 The HOWTO define is horrible and will go away.
377 .#define HOWTO(C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC) \
378 . { (unsigned) C, R, S, B, P, BI, O, SF, NAME, INPLACE, MASKSRC, MASKDST, PC }
381 And will be replaced with the totally magic way. But for the
382 moment, we are compatible, so do it this way.
384 .#define NEWHOWTO(FUNCTION, NAME, SIZE, REL, IN) \
385 . HOWTO (0, 0, SIZE, 0, REL, 0, complain_overflow_dont, FUNCTION, \
386 . NAME, FALSE, 0, 0, IN)
390 This is used to fill in an empty howto entry in an array.
392 .#define EMPTY_HOWTO(C) \
393 . HOWTO ((C), 0, 0, 0, FALSE, 0, complain_overflow_dont, NULL, \
394 . NULL, FALSE, 0, 0, FALSE)
398 Helper routine to turn a symbol into a relocation value.
400 .#define HOWTO_PREPARE(relocation, symbol) \
402 . if (symbol != NULL) \
404 . if (bfd_is_com_section (symbol->section)) \
410 . relocation = symbol->value; \
422 unsigned int bfd_get_reloc_size (reloc_howto_type *);
425 For a reloc_howto_type that operates on a fixed number of bytes,
426 this returns the number of bytes operated on.
430 bfd_get_reloc_size (reloc_howto_type
*howto
)
451 How relocs are tied together in an <<asection>>:
453 .typedef struct relent_chain
456 . struct relent_chain *next;
462 /* N_ONES produces N one bits, without overflowing machine arithmetic. */
463 #define N_ONES(n) (((((bfd_vma) 1 << ((n) - 1)) - 1) << 1) | 1)
470 bfd_reloc_status_type bfd_check_overflow
471 (enum complain_overflow how,
472 unsigned int bitsize,
473 unsigned int rightshift,
474 unsigned int addrsize,
478 Perform overflow checking on @var{relocation} which has
479 @var{bitsize} significant bits and will be shifted right by
480 @var{rightshift} bits, on a machine with addresses containing
481 @var{addrsize} significant bits. The result is either of
482 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
486 bfd_reloc_status_type
487 bfd_check_overflow (enum complain_overflow how
,
488 unsigned int bitsize
,
489 unsigned int rightshift
,
490 unsigned int addrsize
,
493 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
494 bfd_reloc_status_type flag
= bfd_reloc_ok
;
496 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
497 we'll be permissive: extra bits in the field mask will
498 automatically extend the address mask for purposes of the
500 fieldmask
= N_ONES (bitsize
);
501 signmask
= ~fieldmask
;
502 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
503 a
= (relocation
& addrmask
) >> rightshift
;
507 case complain_overflow_dont
:
510 case complain_overflow_signed
:
511 /* If any sign bits are set, all sign bits must be set. That
512 is, A must be a valid negative address after shifting. */
513 signmask
= ~ (fieldmask
>> 1);
516 case complain_overflow_bitfield
:
517 /* Bitfields are sometimes signed, sometimes unsigned. We
518 explicitly allow an address wrap too, which means a bitfield
519 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
520 if the value has some, but not all, bits set outside the
523 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
524 flag
= bfd_reloc_overflow
;
527 case complain_overflow_unsigned
:
528 /* We have an overflow if the address does not fit in the field. */
529 if ((a
& signmask
) != 0)
530 flag
= bfd_reloc_overflow
;
542 bfd_perform_relocation
545 bfd_reloc_status_type bfd_perform_relocation
547 arelent *reloc_entry,
549 asection *input_section,
551 char **error_message);
554 If @var{output_bfd} is supplied to this function, the
555 generated image will be relocatable; the relocations are
556 copied to the output file after they have been changed to
557 reflect the new state of the world. There are two ways of
558 reflecting the results of partial linkage in an output file:
559 by modifying the output data in place, and by modifying the
560 relocation record. Some native formats (e.g., basic a.out and
561 basic coff) have no way of specifying an addend in the
562 relocation type, so the addend has to go in the output data.
563 This is no big deal since in these formats the output data
564 slot will always be big enough for the addend. Complex reloc
565 types with addends were invented to solve just this problem.
566 The @var{error_message} argument is set to an error message if
567 this return @code{bfd_reloc_dangerous}.
571 bfd_reloc_status_type
572 bfd_perform_relocation (bfd
*abfd
,
573 arelent
*reloc_entry
,
575 asection
*input_section
,
577 char **error_message
)
580 bfd_reloc_status_type flag
= bfd_reloc_ok
;
581 bfd_size_type octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
582 bfd_vma output_base
= 0;
583 reloc_howto_type
*howto
= reloc_entry
->howto
;
584 asection
*reloc_target_output_section
;
587 symbol
= *(reloc_entry
->sym_ptr_ptr
);
588 if (bfd_is_abs_section (symbol
->section
)
589 && output_bfd
!= NULL
)
591 reloc_entry
->address
+= input_section
->output_offset
;
595 /* If we are not producing relocatable output, return an error if
596 the symbol is not defined. An undefined weak symbol is
597 considered to have a value of zero (SVR4 ABI, p. 4-27). */
598 if (bfd_is_und_section (symbol
->section
)
599 && (symbol
->flags
& BSF_WEAK
) == 0
600 && output_bfd
== NULL
)
601 flag
= bfd_reloc_undefined
;
603 /* If there is a function supplied to handle this relocation type,
604 call it. It'll return `bfd_reloc_continue' if further processing
606 if (howto
->special_function
)
608 bfd_reloc_status_type cont
;
609 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
610 input_section
, output_bfd
,
612 if (cont
!= bfd_reloc_continue
)
616 /* Is the address of the relocation really within the section? */
617 if (reloc_entry
->address
> bfd_get_section_limit (abfd
, input_section
))
618 return bfd_reloc_outofrange
;
620 /* Work out which section the relocation is targeted at and the
621 initial relocation command value. */
623 /* Get symbol value. (Common symbols are special.) */
624 if (bfd_is_com_section (symbol
->section
))
627 relocation
= symbol
->value
;
629 reloc_target_output_section
= symbol
->section
->output_section
;
631 /* Convert input-section-relative symbol value to absolute. */
632 if ((output_bfd
&& ! howto
->partial_inplace
)
633 || reloc_target_output_section
== NULL
)
636 output_base
= reloc_target_output_section
->vma
;
638 relocation
+= output_base
+ symbol
->section
->output_offset
;
640 /* Add in supplied addend. */
641 relocation
+= reloc_entry
->addend
;
643 /* Here the variable relocation holds the final address of the
644 symbol we are relocating against, plus any addend. */
646 if (howto
->pc_relative
)
648 /* This is a PC relative relocation. We want to set RELOCATION
649 to the distance between the address of the symbol and the
650 location. RELOCATION is already the address of the symbol.
652 We start by subtracting the address of the section containing
655 If pcrel_offset is set, we must further subtract the position
656 of the location within the section. Some targets arrange for
657 the addend to be the negative of the position of the location
658 within the section; for example, i386-aout does this. For
659 i386-aout, pcrel_offset is FALSE. Some other targets do not
660 include the position of the location; for example, m88kbcs,
661 or ELF. For those targets, pcrel_offset is TRUE.
663 If we are producing relocatable output, then we must ensure
664 that this reloc will be correctly computed when the final
665 relocation is done. If pcrel_offset is FALSE we want to wind
666 up with the negative of the location within the section,
667 which means we must adjust the existing addend by the change
668 in the location within the section. If pcrel_offset is TRUE
669 we do not want to adjust the existing addend at all.
671 FIXME: This seems logical to me, but for the case of
672 producing relocatable output it is not what the code
673 actually does. I don't want to change it, because it seems
674 far too likely that something will break. */
677 input_section
->output_section
->vma
+ input_section
->output_offset
;
679 if (howto
->pcrel_offset
)
680 relocation
-= reloc_entry
->address
;
683 if (output_bfd
!= NULL
)
685 if (! howto
->partial_inplace
)
687 /* This is a partial relocation, and we want to apply the relocation
688 to the reloc entry rather than the raw data. Modify the reloc
689 inplace to reflect what we now know. */
690 reloc_entry
->addend
= relocation
;
691 reloc_entry
->address
+= input_section
->output_offset
;
696 /* This is a partial relocation, but inplace, so modify the
699 If we've relocated with a symbol with a section, change
700 into a ref to the section belonging to the symbol. */
702 reloc_entry
->address
+= input_section
->output_offset
;
705 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
706 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
707 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
709 /* For m68k-coff, the addend was being subtracted twice during
710 relocation with -r. Removing the line below this comment
711 fixes that problem; see PR 2953.
713 However, Ian wrote the following, regarding removing the line below,
714 which explains why it is still enabled: --djm
716 If you put a patch like that into BFD you need to check all the COFF
717 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
718 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
719 problem in a different way. There may very well be a reason that the
720 code works as it does.
722 Hmmm. The first obvious point is that bfd_perform_relocation should
723 not have any tests that depend upon the flavour. It's seem like
724 entirely the wrong place for such a thing. The second obvious point
725 is that the current code ignores the reloc addend when producing
726 relocatable output for COFF. That's peculiar. In fact, I really
727 have no idea what the point of the line you want to remove is.
729 A typical COFF reloc subtracts the old value of the symbol and adds in
730 the new value to the location in the object file (if it's a pc
731 relative reloc it adds the difference between the symbol value and the
732 location). When relocating we need to preserve that property.
734 BFD handles this by setting the addend to the negative of the old
735 value of the symbol. Unfortunately it handles common symbols in a
736 non-standard way (it doesn't subtract the old value) but that's a
737 different story (we can't change it without losing backward
738 compatibility with old object files) (coff-i386 does subtract the old
739 value, to be compatible with existing coff-i386 targets, like SCO).
741 So everything works fine when not producing relocatable output. When
742 we are producing relocatable output, logically we should do exactly
743 what we do when not producing relocatable output. Therefore, your
744 patch is correct. In fact, it should probably always just set
745 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
746 add the value into the object file. This won't hurt the COFF code,
747 which doesn't use the addend; I'm not sure what it will do to other
748 formats (the thing to check for would be whether any formats both use
749 the addend and set partial_inplace).
751 When I wanted to make coff-i386 produce relocatable output, I ran
752 into the problem that you are running into: I wanted to remove that
753 line. Rather than risk it, I made the coff-i386 relocs use a special
754 function; it's coff_i386_reloc in coff-i386.c. The function
755 specifically adds the addend field into the object file, knowing that
756 bfd_perform_relocation is not going to. If you remove that line, then
757 coff-i386.c will wind up adding the addend field in twice. It's
758 trivial to fix; it just needs to be done.
760 The problem with removing the line is just that it may break some
761 working code. With BFD it's hard to be sure of anything. The right
762 way to deal with this is simply to build and test at least all the
763 supported COFF targets. It should be straightforward if time and disk
764 space consuming. For each target:
766 2) generate some executable, and link it using -r (I would
767 probably use paranoia.o and link against newlib/libc.a, which
768 for all the supported targets would be available in
769 /usr/cygnus/progressive/H-host/target/lib/libc.a).
770 3) make the change to reloc.c
771 4) rebuild the linker
773 6) if the resulting object files are the same, you have at least
775 7) if they are different you have to figure out which version is
778 relocation
-= reloc_entry
->addend
;
779 reloc_entry
->addend
= 0;
783 reloc_entry
->addend
= relocation
;
788 /* FIXME: This overflow checking is incomplete, because the value
789 might have overflowed before we get here. For a correct check we
790 need to compute the value in a size larger than bitsize, but we
791 can't reasonably do that for a reloc the same size as a host
793 FIXME: We should also do overflow checking on the result after
794 adding in the value contained in the object file. */
795 if (howto
->complain_on_overflow
!= complain_overflow_dont
796 && flag
== bfd_reloc_ok
)
797 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
800 bfd_arch_bits_per_address (abfd
),
803 /* Either we are relocating all the way, or we don't want to apply
804 the relocation to the reloc entry (probably because there isn't
805 any room in the output format to describe addends to relocs). */
807 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
808 (OSF version 1.3, compiler version 3.11). It miscompiles the
822 x <<= (unsigned long) s.i0;
826 printf ("succeeded (%lx)\n", x);
830 relocation
>>= (bfd_vma
) howto
->rightshift
;
832 /* Shift everything up to where it's going to be used. */
833 relocation
<<= (bfd_vma
) howto
->bitpos
;
835 /* Wait for the day when all have the mask in them. */
838 i instruction to be left alone
839 o offset within instruction
840 r relocation offset to apply
849 (( i i i i i o o o o o from bfd_get<size>
850 and S S S S S) to get the size offset we want
851 + r r r r r r r r r r) to get the final value to place
852 and D D D D D to chop to right size
853 -----------------------
856 ( i i i i i o o o o o from bfd_get<size>
857 and N N N N N ) get instruction
858 -----------------------
864 -----------------------
865 = R R R R R R R R R R put into bfd_put<size>
869 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
875 char x
= bfd_get_8 (abfd
, (char *) data
+ octets
);
877 bfd_put_8 (abfd
, x
, (unsigned char *) data
+ octets
);
883 short x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
885 bfd_put_16 (abfd
, (bfd_vma
) x
, (unsigned char *) data
+ octets
);
890 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
892 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
897 long x
= bfd_get_32 (abfd
, (bfd_byte
*) data
+ octets
);
898 relocation
= -relocation
;
900 bfd_put_32 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
906 long x
= bfd_get_16 (abfd
, (bfd_byte
*) data
+ octets
);
907 relocation
= -relocation
;
909 bfd_put_16 (abfd
, (bfd_vma
) x
, (bfd_byte
*) data
+ octets
);
920 bfd_vma x
= bfd_get_64 (abfd
, (bfd_byte
*) data
+ octets
);
922 bfd_put_64 (abfd
, x
, (bfd_byte
*) data
+ octets
);
929 return bfd_reloc_other
;
937 bfd_install_relocation
940 bfd_reloc_status_type bfd_install_relocation
942 arelent *reloc_entry,
943 void *data, bfd_vma data_start,
944 asection *input_section,
945 char **error_message);
948 This looks remarkably like <<bfd_perform_relocation>>, except it
949 does not expect that the section contents have been filled in.
950 I.e., it's suitable for use when creating, rather than applying
953 For now, this function should be considered reserved for the
957 bfd_reloc_status_type
958 bfd_install_relocation (bfd
*abfd
,
959 arelent
*reloc_entry
,
961 bfd_vma data_start_offset
,
962 asection
*input_section
,
963 char **error_message
)
966 bfd_reloc_status_type flag
= bfd_reloc_ok
;
967 bfd_size_type octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
);
968 bfd_vma output_base
= 0;
969 reloc_howto_type
*howto
= reloc_entry
->howto
;
970 asection
*reloc_target_output_section
;
974 symbol
= *(reloc_entry
->sym_ptr_ptr
);
975 if (bfd_is_abs_section (symbol
->section
))
977 reloc_entry
->address
+= input_section
->output_offset
;
981 /* If there is a function supplied to handle this relocation type,
982 call it. It'll return `bfd_reloc_continue' if further processing
984 if (howto
->special_function
)
986 bfd_reloc_status_type cont
;
988 /* XXX - The special_function calls haven't been fixed up to deal
989 with creating new relocations and section contents. */
990 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
991 /* XXX - Non-portable! */
992 ((bfd_byte
*) data_start
993 - data_start_offset
),
994 input_section
, abfd
, error_message
);
995 if (cont
!= bfd_reloc_continue
)
999 /* Is the address of the relocation really within the section? */
1000 if (reloc_entry
->address
> bfd_get_section_limit (abfd
, input_section
))
1001 return bfd_reloc_outofrange
;
1003 /* Work out which section the relocation is targeted at and the
1004 initial relocation command value. */
1006 /* Get symbol value. (Common symbols are special.) */
1007 if (bfd_is_com_section (symbol
->section
))
1010 relocation
= symbol
->value
;
1012 reloc_target_output_section
= symbol
->section
->output_section
;
1014 /* Convert input-section-relative symbol value to absolute. */
1015 if (! howto
->partial_inplace
)
1018 output_base
= reloc_target_output_section
->vma
;
1020 relocation
+= output_base
+ symbol
->section
->output_offset
;
1022 /* Add in supplied addend. */
1023 relocation
+= reloc_entry
->addend
;
1025 /* Here the variable relocation holds the final address of the
1026 symbol we are relocating against, plus any addend. */
1028 if (howto
->pc_relative
)
1030 /* This is a PC relative relocation. We want to set RELOCATION
1031 to the distance between the address of the symbol and the
1032 location. RELOCATION is already the address of the symbol.
1034 We start by subtracting the address of the section containing
1037 If pcrel_offset is set, we must further subtract the position
1038 of the location within the section. Some targets arrange for
1039 the addend to be the negative of the position of the location
1040 within the section; for example, i386-aout does this. For
1041 i386-aout, pcrel_offset is FALSE. Some other targets do not
1042 include the position of the location; for example, m88kbcs,
1043 or ELF. For those targets, pcrel_offset is TRUE.
1045 If we are producing relocatable output, then we must ensure
1046 that this reloc will be correctly computed when the final
1047 relocation is done. If pcrel_offset is FALSE we want to wind
1048 up with the negative of the location within the section,
1049 which means we must adjust the existing addend by the change
1050 in the location within the section. If pcrel_offset is TRUE
1051 we do not want to adjust the existing addend at all.
1053 FIXME: This seems logical to me, but for the case of
1054 producing relocatable output it is not what the code
1055 actually does. I don't want to change it, because it seems
1056 far too likely that something will break. */
1059 input_section
->output_section
->vma
+ input_section
->output_offset
;
1061 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1062 relocation
-= reloc_entry
->address
;
1065 if (! howto
->partial_inplace
)
1067 /* This is a partial relocation, and we want to apply the relocation
1068 to the reloc entry rather than the raw data. Modify the reloc
1069 inplace to reflect what we now know. */
1070 reloc_entry
->addend
= relocation
;
1071 reloc_entry
->address
+= input_section
->output_offset
;
1076 /* This is a partial relocation, but inplace, so modify the
1079 If we've relocated with a symbol with a section, change
1080 into a ref to the section belonging to the symbol. */
1081 reloc_entry
->address
+= input_section
->output_offset
;
1084 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
1085 && strcmp (abfd
->xvec
->name
, "coff-Intel-little") != 0
1086 && strcmp (abfd
->xvec
->name
, "coff-Intel-big") != 0)
1089 /* For m68k-coff, the addend was being subtracted twice during
1090 relocation with -r. Removing the line below this comment
1091 fixes that problem; see PR 2953.
1093 However, Ian wrote the following, regarding removing the line below,
1094 which explains why it is still enabled: --djm
1096 If you put a patch like that into BFD you need to check all the COFF
1097 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
1098 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
1099 problem in a different way. There may very well be a reason that the
1100 code works as it does.
1102 Hmmm. The first obvious point is that bfd_install_relocation should
1103 not have any tests that depend upon the flavour. It's seem like
1104 entirely the wrong place for such a thing. The second obvious point
1105 is that the current code ignores the reloc addend when producing
1106 relocatable output for COFF. That's peculiar. In fact, I really
1107 have no idea what the point of the line you want to remove is.
1109 A typical COFF reloc subtracts the old value of the symbol and adds in
1110 the new value to the location in the object file (if it's a pc
1111 relative reloc it adds the difference between the symbol value and the
1112 location). When relocating we need to preserve that property.
1114 BFD handles this by setting the addend to the negative of the old
1115 value of the symbol. Unfortunately it handles common symbols in a
1116 non-standard way (it doesn't subtract the old value) but that's a
1117 different story (we can't change it without losing backward
1118 compatibility with old object files) (coff-i386 does subtract the old
1119 value, to be compatible with existing coff-i386 targets, like SCO).
1121 So everything works fine when not producing relocatable output. When
1122 we are producing relocatable output, logically we should do exactly
1123 what we do when not producing relocatable output. Therefore, your
1124 patch is correct. In fact, it should probably always just set
1125 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
1126 add the value into the object file. This won't hurt the COFF code,
1127 which doesn't use the addend; I'm not sure what it will do to other
1128 formats (the thing to check for would be whether any formats both use
1129 the addend and set partial_inplace).
1131 When I wanted to make coff-i386 produce relocatable output, I ran
1132 into the problem that you are running into: I wanted to remove that
1133 line. Rather than risk it, I made the coff-i386 relocs use a special
1134 function; it's coff_i386_reloc in coff-i386.c. The function
1135 specifically adds the addend field into the object file, knowing that
1136 bfd_install_relocation is not going to. If you remove that line, then
1137 coff-i386.c will wind up adding the addend field in twice. It's
1138 trivial to fix; it just needs to be done.
1140 The problem with removing the line is just that it may break some
1141 working code. With BFD it's hard to be sure of anything. The right
1142 way to deal with this is simply to build and test at least all the
1143 supported COFF targets. It should be straightforward if time and disk
1144 space consuming. For each target:
1146 2) generate some executable, and link it using -r (I would
1147 probably use paranoia.o and link against newlib/libc.a, which
1148 for all the supported targets would be available in
1149 /usr/cygnus/progressive/H-host/target/lib/libc.a).
1150 3) make the change to reloc.c
1151 4) rebuild the linker
1153 6) if the resulting object files are the same, you have at least
1155 7) if they are different you have to figure out which version is
1157 relocation
-= reloc_entry
->addend
;
1158 /* FIXME: There should be no target specific code here... */
1159 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1160 reloc_entry
->addend
= 0;
1164 reloc_entry
->addend
= relocation
;
1168 /* FIXME: This overflow checking is incomplete, because the value
1169 might have overflowed before we get here. For a correct check we
1170 need to compute the value in a size larger than bitsize, but we
1171 can't reasonably do that for a reloc the same size as a host
1173 FIXME: We should also do overflow checking on the result after
1174 adding in the value contained in the object file. */
1175 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1176 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1179 bfd_arch_bits_per_address (abfd
),
1182 /* Either we are relocating all the way, or we don't want to apply
1183 the relocation to the reloc entry (probably because there isn't
1184 any room in the output format to describe addends to relocs). */
1186 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
1187 (OSF version 1.3, compiler version 3.11). It miscompiles the
1201 x <<= (unsigned long) s.i0;
1203 printf ("failed\n");
1205 printf ("succeeded (%lx)\n", x);
1209 relocation
>>= (bfd_vma
) howto
->rightshift
;
1211 /* Shift everything up to where it's going to be used. */
1212 relocation
<<= (bfd_vma
) howto
->bitpos
;
1214 /* Wait for the day when all have the mask in them. */
1217 i instruction to be left alone
1218 o offset within instruction
1219 r relocation offset to apply
1228 (( i i i i i o o o o o from bfd_get<size>
1229 and S S S S S) to get the size offset we want
1230 + r r r r r r r r r r) to get the final value to place
1231 and D D D D D to chop to right size
1232 -----------------------
1235 ( i i i i i o o o o o from bfd_get<size>
1236 and N N N N N ) get instruction
1237 -----------------------
1243 -----------------------
1244 = R R R R R R R R R R put into bfd_put<size>
1248 x = ( (x & ~howto->dst_mask) | (((x & howto->src_mask) + relocation) & howto->dst_mask))
1250 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1252 switch (howto
->size
)
1256 char x
= bfd_get_8 (abfd
, data
);
1258 bfd_put_8 (abfd
, x
, data
);
1264 short x
= bfd_get_16 (abfd
, data
);
1266 bfd_put_16 (abfd
, (bfd_vma
) x
, data
);
1271 long x
= bfd_get_32 (abfd
, data
);
1273 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1278 long x
= bfd_get_32 (abfd
, data
);
1279 relocation
= -relocation
;
1281 bfd_put_32 (abfd
, (bfd_vma
) x
, data
);
1291 bfd_vma x
= bfd_get_64 (abfd
, data
);
1293 bfd_put_64 (abfd
, x
, data
);
1297 return bfd_reloc_other
;
1303 /* This relocation routine is used by some of the backend linkers.
1304 They do not construct asymbol or arelent structures, so there is no
1305 reason for them to use bfd_perform_relocation. Also,
1306 bfd_perform_relocation is so hacked up it is easier to write a new
1307 function than to try to deal with it.
1309 This routine does a final relocation. Whether it is useful for a
1310 relocatable link depends upon how the object format defines
1313 FIXME: This routine ignores any special_function in the HOWTO,
1314 since the existing special_function values have been written for
1315 bfd_perform_relocation.
1317 HOWTO is the reloc howto information.
1318 INPUT_BFD is the BFD which the reloc applies to.
1319 INPUT_SECTION is the section which the reloc applies to.
1320 CONTENTS is the contents of the section.
1321 ADDRESS is the address of the reloc within INPUT_SECTION.
1322 VALUE is the value of the symbol the reloc refers to.
1323 ADDEND is the addend of the reloc. */
1325 bfd_reloc_status_type
1326 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1328 asection
*input_section
,
1336 /* Sanity check the address. */
1337 if (address
> bfd_get_section_limit (input_bfd
, input_section
))
1338 return bfd_reloc_outofrange
;
1340 /* This function assumes that we are dealing with a basic relocation
1341 against a symbol. We want to compute the value of the symbol to
1342 relocate to. This is just VALUE, the value of the symbol, plus
1343 ADDEND, any addend associated with the reloc. */
1344 relocation
= value
+ addend
;
1346 /* If the relocation is PC relative, we want to set RELOCATION to
1347 the distance between the symbol (currently in RELOCATION) and the
1348 location we are relocating. Some targets (e.g., i386-aout)
1349 arrange for the contents of the section to be the negative of the
1350 offset of the location within the section; for such targets
1351 pcrel_offset is FALSE. Other targets (e.g., m88kbcs or ELF)
1352 simply leave the contents of the section as zero; for such
1353 targets pcrel_offset is TRUE. If pcrel_offset is FALSE we do not
1354 need to subtract out the offset of the location within the
1355 section (which is just ADDRESS). */
1356 if (howto
->pc_relative
)
1358 relocation
-= (input_section
->output_section
->vma
1359 + input_section
->output_offset
);
1360 if (howto
->pcrel_offset
)
1361 relocation
-= address
;
1364 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1365 contents
+ address
);
1368 /* Relocate a given location using a given value and howto. */
1370 bfd_reloc_status_type
1371 _bfd_relocate_contents (reloc_howto_type
*howto
,
1378 bfd_reloc_status_type flag
;
1379 unsigned int rightshift
= howto
->rightshift
;
1380 unsigned int bitpos
= howto
->bitpos
;
1382 /* If the size is negative, negate RELOCATION. This isn't very
1384 if (howto
->size
< 0)
1385 relocation
= -relocation
;
1387 /* Get the value we are going to relocate. */
1388 size
= bfd_get_reloc_size (howto
);
1395 x
= bfd_get_8 (input_bfd
, location
);
1398 x
= bfd_get_16 (input_bfd
, location
);
1401 x
= bfd_get_32 (input_bfd
, location
);
1405 x
= bfd_get_64 (input_bfd
, location
);
1412 /* Check for overflow. FIXME: We may drop bits during the addition
1413 which we don't check for. We must either check at every single
1414 operation, which would be tedious, or we must do the computations
1415 in a type larger than bfd_vma, which would be inefficient. */
1416 flag
= bfd_reloc_ok
;
1417 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1419 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1422 /* Get the values to be added together. For signed and unsigned
1423 relocations, we assume that all values should be truncated to
1424 the size of an address. For bitfields, all the bits matter.
1425 See also bfd_check_overflow. */
1426 fieldmask
= N_ONES (howto
->bitsize
);
1427 signmask
= ~fieldmask
;
1428 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1429 | (fieldmask
<< rightshift
));
1430 a
= (relocation
& addrmask
) >> rightshift
;
1431 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1432 addrmask
>>= rightshift
;
1434 switch (howto
->complain_on_overflow
)
1436 case complain_overflow_signed
:
1437 /* If any sign bits are set, all sign bits must be set.
1438 That is, A must be a valid negative address after
1440 signmask
= ~(fieldmask
>> 1);
1443 case complain_overflow_bitfield
:
1444 /* Much like the signed check, but for a field one bit
1445 wider. We allow a bitfield to represent numbers in the
1446 range -2**n to 2**n-1, where n is the number of bits in the
1447 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1448 can't overflow, which is exactly what we want. */
1450 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1451 flag
= bfd_reloc_overflow
;
1453 /* We only need this next bit of code if the sign bit of B
1454 is below the sign bit of A. This would only happen if
1455 SRC_MASK had fewer bits than BITSIZE. Note that if
1456 SRC_MASK has more bits than BITSIZE, we can get into
1457 trouble; we would need to verify that B is in range, as
1458 we do for A above. */
1459 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1462 /* Set all the bits above the sign bit. */
1465 /* Now we can do the addition. */
1468 /* See if the result has the correct sign. Bits above the
1469 sign bit are junk now; ignore them. If the sum is
1470 positive, make sure we did not have all negative inputs;
1471 if the sum is negative, make sure we did not have all
1472 positive inputs. The test below looks only at the sign
1473 bits, and it really just
1474 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1476 We mask with addrmask here to explicitly allow an address
1477 wrap-around. The Linux kernel relies on it, and it is
1478 the only way to write assembler code which can run when
1479 loaded at a location 0x80000000 away from the location at
1480 which it is linked. */
1481 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1482 flag
= bfd_reloc_overflow
;
1485 case complain_overflow_unsigned
:
1486 /* Checking for an unsigned overflow is relatively easy:
1487 trim the addresses and add, and trim the result as well.
1488 Overflow is normally indicated when the result does not
1489 fit in the field. However, we also need to consider the
1490 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1491 input is 0x80000000, and bfd_vma is only 32 bits; then we
1492 will get sum == 0, but there is an overflow, since the
1493 inputs did not fit in the field. Instead of doing a
1494 separate test, we can check for this by or-ing in the
1495 operands when testing for the sum overflowing its final
1497 sum
= (a
+ b
) & addrmask
;
1498 if ((a
| b
| sum
) & signmask
)
1499 flag
= bfd_reloc_overflow
;
1507 /* Put RELOCATION in the right bits. */
1508 relocation
>>= (bfd_vma
) rightshift
;
1509 relocation
<<= (bfd_vma
) bitpos
;
1511 /* Add RELOCATION to the right bits of X. */
1512 x
= ((x
& ~howto
->dst_mask
)
1513 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1515 /* Put the relocated value back in the object file. */
1521 bfd_put_8 (input_bfd
, x
, location
);
1524 bfd_put_16 (input_bfd
, x
, location
);
1527 bfd_put_32 (input_bfd
, x
, location
);
1531 bfd_put_64 (input_bfd
, x
, location
);
1541 /* Clear a given location using a given howto, by applying a fixed relocation
1542 value and discarding any in-place addend. This is used for fixed-up
1543 relocations against discarded symbols, to make ignorable debug or unwind
1544 information more obvious. */
1547 _bfd_clear_contents (reloc_howto_type
*howto
,
1549 asection
*input_section
,
1555 /* Get the value we are going to relocate. */
1556 size
= bfd_get_reloc_size (howto
);
1563 x
= bfd_get_8 (input_bfd
, location
);
1566 x
= bfd_get_16 (input_bfd
, location
);
1569 x
= bfd_get_32 (input_bfd
, location
);
1573 x
= bfd_get_64 (input_bfd
, location
);
1580 /* Zero out the unwanted bits of X. */
1581 x
&= ~howto
->dst_mask
;
1583 /* For a range list, use 1 instead of 0 as placeholder. 0
1584 would terminate the list, hiding any later entries. */
1585 if (strcmp (bfd_get_section_name (input_bfd
, input_section
),
1586 ".debug_ranges") == 0
1587 && (howto
->dst_mask
& 1) != 0)
1590 /* Put the relocated value back in the object file. */
1597 bfd_put_8 (input_bfd
, x
, location
);
1600 bfd_put_16 (input_bfd
, x
, location
);
1603 bfd_put_32 (input_bfd
, x
, location
);
1607 bfd_put_64 (input_bfd
, x
, location
);
1618 howto manager, , typedef arelent, Relocations
1623 When an application wants to create a relocation, but doesn't
1624 know what the target machine might call it, it can find out by
1625 using this bit of code.
1634 The insides of a reloc code. The idea is that, eventually, there
1635 will be one enumerator for every type of relocation we ever do.
1636 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1637 return a howto pointer.
1639 This does mean that the application must determine the correct
1640 enumerator value; you can't get a howto pointer from a random set
1661 Basic absolute relocations of N bits.
1676 PC-relative relocations. Sometimes these are relative to the address
1677 of the relocation itself; sometimes they are relative to the start of
1678 the section containing the relocation. It depends on the specific target.
1680 The 24-bit relocation is used in some Intel 960 configurations.
1685 Section relative relocations. Some targets need this for DWARF2.
1688 BFD_RELOC_32_GOT_PCREL
1690 BFD_RELOC_16_GOT_PCREL
1692 BFD_RELOC_8_GOT_PCREL
1698 BFD_RELOC_LO16_GOTOFF
1700 BFD_RELOC_HI16_GOTOFF
1702 BFD_RELOC_HI16_S_GOTOFF
1706 BFD_RELOC_64_PLT_PCREL
1708 BFD_RELOC_32_PLT_PCREL
1710 BFD_RELOC_24_PLT_PCREL
1712 BFD_RELOC_16_PLT_PCREL
1714 BFD_RELOC_8_PLT_PCREL
1722 BFD_RELOC_LO16_PLTOFF
1724 BFD_RELOC_HI16_PLTOFF
1726 BFD_RELOC_HI16_S_PLTOFF
1740 BFD_RELOC_68K_GLOB_DAT
1742 BFD_RELOC_68K_JMP_SLOT
1744 BFD_RELOC_68K_RELATIVE
1746 BFD_RELOC_68K_TLS_GD32
1748 BFD_RELOC_68K_TLS_GD16
1750 BFD_RELOC_68K_TLS_GD8
1752 BFD_RELOC_68K_TLS_LDM32
1754 BFD_RELOC_68K_TLS_LDM16
1756 BFD_RELOC_68K_TLS_LDM8
1758 BFD_RELOC_68K_TLS_LDO32
1760 BFD_RELOC_68K_TLS_LDO16
1762 BFD_RELOC_68K_TLS_LDO8
1764 BFD_RELOC_68K_TLS_IE32
1766 BFD_RELOC_68K_TLS_IE16
1768 BFD_RELOC_68K_TLS_IE8
1770 BFD_RELOC_68K_TLS_LE32
1772 BFD_RELOC_68K_TLS_LE16
1774 BFD_RELOC_68K_TLS_LE8
1776 Relocations used by 68K ELF.
1779 BFD_RELOC_32_BASEREL
1781 BFD_RELOC_16_BASEREL
1783 BFD_RELOC_LO16_BASEREL
1785 BFD_RELOC_HI16_BASEREL
1787 BFD_RELOC_HI16_S_BASEREL
1793 Linkage-table relative.
1798 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1801 BFD_RELOC_32_PCREL_S2
1803 BFD_RELOC_16_PCREL_S2
1805 BFD_RELOC_23_PCREL_S2
1807 These PC-relative relocations are stored as word displacements --
1808 i.e., byte displacements shifted right two bits. The 30-bit word
1809 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1810 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1811 signed 16-bit displacement is used on the MIPS, and the 23-bit
1812 displacement is used on the Alpha.
1819 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1820 the target word. These are used on the SPARC.
1827 For systems that allocate a Global Pointer register, these are
1828 displacements off that register. These relocation types are
1829 handled specially, because the value the register will have is
1830 decided relatively late.
1833 BFD_RELOC_I960_CALLJ
1835 Reloc types used for i960/b.out.
1840 BFD_RELOC_SPARC_WDISP22
1846 BFD_RELOC_SPARC_GOT10
1848 BFD_RELOC_SPARC_GOT13
1850 BFD_RELOC_SPARC_GOT22
1852 BFD_RELOC_SPARC_PC10
1854 BFD_RELOC_SPARC_PC22
1856 BFD_RELOC_SPARC_WPLT30
1858 BFD_RELOC_SPARC_COPY
1860 BFD_RELOC_SPARC_GLOB_DAT
1862 BFD_RELOC_SPARC_JMP_SLOT
1864 BFD_RELOC_SPARC_RELATIVE
1866 BFD_RELOC_SPARC_UA16
1868 BFD_RELOC_SPARC_UA32
1870 BFD_RELOC_SPARC_UA64
1872 BFD_RELOC_SPARC_GOTDATA_HIX22
1874 BFD_RELOC_SPARC_GOTDATA_LOX10
1876 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1878 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1880 BFD_RELOC_SPARC_GOTDATA_OP
1882 BFD_RELOC_SPARC_JMP_IREL
1884 BFD_RELOC_SPARC_IRELATIVE
1886 SPARC ELF relocations. There is probably some overlap with other
1887 relocation types already defined.
1890 BFD_RELOC_SPARC_BASE13
1892 BFD_RELOC_SPARC_BASE22
1894 I think these are specific to SPARC a.out (e.g., Sun 4).
1904 BFD_RELOC_SPARC_OLO10
1906 BFD_RELOC_SPARC_HH22
1908 BFD_RELOC_SPARC_HM10
1910 BFD_RELOC_SPARC_LM22
1912 BFD_RELOC_SPARC_PC_HH22
1914 BFD_RELOC_SPARC_PC_HM10
1916 BFD_RELOC_SPARC_PC_LM22
1918 BFD_RELOC_SPARC_WDISP16
1920 BFD_RELOC_SPARC_WDISP19
1928 BFD_RELOC_SPARC_DISP64
1931 BFD_RELOC_SPARC_PLT32
1933 BFD_RELOC_SPARC_PLT64
1935 BFD_RELOC_SPARC_HIX22
1937 BFD_RELOC_SPARC_LOX10
1945 BFD_RELOC_SPARC_REGISTER
1949 BFD_RELOC_SPARC_SIZE32
1951 BFD_RELOC_SPARC_SIZE64
1953 BFD_RELOC_SPARC_WDISP10
1958 BFD_RELOC_SPARC_REV32
1960 SPARC little endian relocation
1962 BFD_RELOC_SPARC_TLS_GD_HI22
1964 BFD_RELOC_SPARC_TLS_GD_LO10
1966 BFD_RELOC_SPARC_TLS_GD_ADD
1968 BFD_RELOC_SPARC_TLS_GD_CALL
1970 BFD_RELOC_SPARC_TLS_LDM_HI22
1972 BFD_RELOC_SPARC_TLS_LDM_LO10
1974 BFD_RELOC_SPARC_TLS_LDM_ADD
1976 BFD_RELOC_SPARC_TLS_LDM_CALL
1978 BFD_RELOC_SPARC_TLS_LDO_HIX22
1980 BFD_RELOC_SPARC_TLS_LDO_LOX10
1982 BFD_RELOC_SPARC_TLS_LDO_ADD
1984 BFD_RELOC_SPARC_TLS_IE_HI22
1986 BFD_RELOC_SPARC_TLS_IE_LO10
1988 BFD_RELOC_SPARC_TLS_IE_LD
1990 BFD_RELOC_SPARC_TLS_IE_LDX
1992 BFD_RELOC_SPARC_TLS_IE_ADD
1994 BFD_RELOC_SPARC_TLS_LE_HIX22
1996 BFD_RELOC_SPARC_TLS_LE_LOX10
1998 BFD_RELOC_SPARC_TLS_DTPMOD32
2000 BFD_RELOC_SPARC_TLS_DTPMOD64
2002 BFD_RELOC_SPARC_TLS_DTPOFF32
2004 BFD_RELOC_SPARC_TLS_DTPOFF64
2006 BFD_RELOC_SPARC_TLS_TPOFF32
2008 BFD_RELOC_SPARC_TLS_TPOFF64
2010 SPARC TLS relocations
2019 BFD_RELOC_SPU_IMM10W
2023 BFD_RELOC_SPU_IMM16W
2027 BFD_RELOC_SPU_PCREL9a
2029 BFD_RELOC_SPU_PCREL9b
2031 BFD_RELOC_SPU_PCREL16
2041 BFD_RELOC_SPU_ADD_PIC
2046 BFD_RELOC_ALPHA_GPDISP_HI16
2048 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
2049 "addend" in some special way.
2050 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
2051 writing; when reading, it will be the absolute section symbol. The
2052 addend is the displacement in bytes of the "lda" instruction from
2053 the "ldah" instruction (which is at the address of this reloc).
2055 BFD_RELOC_ALPHA_GPDISP_LO16
2057 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
2058 with GPDISP_HI16 relocs. The addend is ignored when writing the
2059 relocations out, and is filled in with the file's GP value on
2060 reading, for convenience.
2063 BFD_RELOC_ALPHA_GPDISP
2065 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
2066 relocation except that there is no accompanying GPDISP_LO16
2070 BFD_RELOC_ALPHA_LITERAL
2072 BFD_RELOC_ALPHA_ELF_LITERAL
2074 BFD_RELOC_ALPHA_LITUSE
2076 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
2077 the assembler turns it into a LDQ instruction to load the address of
2078 the symbol, and then fills in a register in the real instruction.
2080 The LITERAL reloc, at the LDQ instruction, refers to the .lita
2081 section symbol. The addend is ignored when writing, but is filled
2082 in with the file's GP value on reading, for convenience, as with the
2085 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
2086 It should refer to the symbol to be referenced, as with 16_GOTOFF,
2087 but it generates output not based on the position within the .got
2088 section, but relative to the GP value chosen for the file during the
2091 The LITUSE reloc, on the instruction using the loaded address, gives
2092 information to the linker that it might be able to use to optimize
2093 away some literal section references. The symbol is ignored (read
2094 as the absolute section symbol), and the "addend" indicates the type
2095 of instruction using the register:
2096 1 - "memory" fmt insn
2097 2 - byte-manipulation (byte offset reg)
2098 3 - jsr (target of branch)
2101 BFD_RELOC_ALPHA_HINT
2103 The HINT relocation indicates a value that should be filled into the
2104 "hint" field of a jmp/jsr/ret instruction, for possible branch-
2105 prediction logic which may be provided on some processors.
2108 BFD_RELOC_ALPHA_LINKAGE
2110 The LINKAGE relocation outputs a linkage pair in the object file,
2111 which is filled by the linker.
2114 BFD_RELOC_ALPHA_CODEADDR
2116 The CODEADDR relocation outputs a STO_CA in the object file,
2117 which is filled by the linker.
2120 BFD_RELOC_ALPHA_GPREL_HI16
2122 BFD_RELOC_ALPHA_GPREL_LO16
2124 The GPREL_HI/LO relocations together form a 32-bit offset from the
2128 BFD_RELOC_ALPHA_BRSGP
2130 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
2131 share a common GP, and the target address is adjusted for
2132 STO_ALPHA_STD_GPLOAD.
2137 The NOP relocation outputs a NOP if the longword displacement
2138 between two procedure entry points is < 2^21.
2143 The BSR relocation outputs a BSR if the longword displacement
2144 between two procedure entry points is < 2^21.
2149 The LDA relocation outputs a LDA if the longword displacement
2150 between two procedure entry points is < 2^16.
2155 The BOH relocation outputs a BSR if the longword displacement
2156 between two procedure entry points is < 2^21, or else a hint.
2159 BFD_RELOC_ALPHA_TLSGD
2161 BFD_RELOC_ALPHA_TLSLDM
2163 BFD_RELOC_ALPHA_DTPMOD64
2165 BFD_RELOC_ALPHA_GOTDTPREL16
2167 BFD_RELOC_ALPHA_DTPREL64
2169 BFD_RELOC_ALPHA_DTPREL_HI16
2171 BFD_RELOC_ALPHA_DTPREL_LO16
2173 BFD_RELOC_ALPHA_DTPREL16
2175 BFD_RELOC_ALPHA_GOTTPREL16
2177 BFD_RELOC_ALPHA_TPREL64
2179 BFD_RELOC_ALPHA_TPREL_HI16
2181 BFD_RELOC_ALPHA_TPREL_LO16
2183 BFD_RELOC_ALPHA_TPREL16
2185 Alpha thread-local storage relocations.
2190 BFD_RELOC_MICROMIPS_JMP
2192 The MIPS jump instruction.
2195 BFD_RELOC_MIPS16_JMP
2197 The MIPS16 jump instruction.
2200 BFD_RELOC_MIPS16_GPREL
2202 MIPS16 GP relative reloc.
2207 High 16 bits of 32-bit value; simple reloc.
2212 High 16 bits of 32-bit value but the low 16 bits will be sign
2213 extended and added to form the final result. If the low 16
2214 bits form a negative number, we need to add one to the high value
2215 to compensate for the borrow when the low bits are added.
2223 BFD_RELOC_HI16_PCREL
2225 High 16 bits of 32-bit pc-relative value
2227 BFD_RELOC_HI16_S_PCREL
2229 High 16 bits of 32-bit pc-relative value, adjusted
2231 BFD_RELOC_LO16_PCREL
2233 Low 16 bits of pc-relative value
2236 BFD_RELOC_MIPS16_GOT16
2238 BFD_RELOC_MIPS16_CALL16
2240 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
2241 16-bit immediate fields
2243 BFD_RELOC_MIPS16_HI16
2245 MIPS16 high 16 bits of 32-bit value.
2247 BFD_RELOC_MIPS16_HI16_S
2249 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
2250 extended and added to form the final result. If the low 16
2251 bits form a negative number, we need to add one to the high value
2252 to compensate for the borrow when the low bits are added.
2254 BFD_RELOC_MIPS16_LO16
2259 BFD_RELOC_MIPS16_TLS_GD
2261 BFD_RELOC_MIPS16_TLS_LDM
2263 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2265 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2267 BFD_RELOC_MIPS16_TLS_GOTTPREL
2269 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2271 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2273 MIPS16 TLS relocations
2276 BFD_RELOC_MIPS_LITERAL
2278 BFD_RELOC_MICROMIPS_LITERAL
2280 Relocation against a MIPS literal section.
2283 BFD_RELOC_MICROMIPS_7_PCREL_S1
2285 BFD_RELOC_MICROMIPS_10_PCREL_S1
2287 BFD_RELOC_MICROMIPS_16_PCREL_S1
2289 microMIPS PC-relative relocations.
2292 BFD_RELOC_MICROMIPS_GPREL16
2294 BFD_RELOC_MICROMIPS_HI16
2296 BFD_RELOC_MICROMIPS_HI16_S
2298 BFD_RELOC_MICROMIPS_LO16
2300 microMIPS versions of generic BFD relocs.
2303 BFD_RELOC_MIPS_GOT16
2305 BFD_RELOC_MICROMIPS_GOT16
2307 BFD_RELOC_MIPS_CALL16
2309 BFD_RELOC_MICROMIPS_CALL16
2311 BFD_RELOC_MIPS_GOT_HI16
2313 BFD_RELOC_MICROMIPS_GOT_HI16
2315 BFD_RELOC_MIPS_GOT_LO16
2317 BFD_RELOC_MICROMIPS_GOT_LO16
2319 BFD_RELOC_MIPS_CALL_HI16
2321 BFD_RELOC_MICROMIPS_CALL_HI16
2323 BFD_RELOC_MIPS_CALL_LO16
2325 BFD_RELOC_MICROMIPS_CALL_LO16
2329 BFD_RELOC_MICROMIPS_SUB
2331 BFD_RELOC_MIPS_GOT_PAGE
2333 BFD_RELOC_MICROMIPS_GOT_PAGE
2335 BFD_RELOC_MIPS_GOT_OFST
2337 BFD_RELOC_MICROMIPS_GOT_OFST
2339 BFD_RELOC_MIPS_GOT_DISP
2341 BFD_RELOC_MICROMIPS_GOT_DISP
2343 BFD_RELOC_MIPS_SHIFT5
2345 BFD_RELOC_MIPS_SHIFT6
2347 BFD_RELOC_MIPS_INSERT_A
2349 BFD_RELOC_MIPS_INSERT_B
2351 BFD_RELOC_MIPS_DELETE
2353 BFD_RELOC_MIPS_HIGHEST
2355 BFD_RELOC_MICROMIPS_HIGHEST
2357 BFD_RELOC_MIPS_HIGHER
2359 BFD_RELOC_MICROMIPS_HIGHER
2361 BFD_RELOC_MIPS_SCN_DISP
2363 BFD_RELOC_MICROMIPS_SCN_DISP
2365 BFD_RELOC_MIPS_REL16
2367 BFD_RELOC_MIPS_RELGOT
2371 BFD_RELOC_MICROMIPS_JALR
2373 BFD_RELOC_MIPS_TLS_DTPMOD32
2375 BFD_RELOC_MIPS_TLS_DTPREL32
2377 BFD_RELOC_MIPS_TLS_DTPMOD64
2379 BFD_RELOC_MIPS_TLS_DTPREL64
2381 BFD_RELOC_MIPS_TLS_GD
2383 BFD_RELOC_MICROMIPS_TLS_GD
2385 BFD_RELOC_MIPS_TLS_LDM
2387 BFD_RELOC_MICROMIPS_TLS_LDM
2389 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2391 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2393 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2395 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2397 BFD_RELOC_MIPS_TLS_GOTTPREL
2399 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2401 BFD_RELOC_MIPS_TLS_TPREL32
2403 BFD_RELOC_MIPS_TLS_TPREL64
2405 BFD_RELOC_MIPS_TLS_TPREL_HI16
2407 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2409 BFD_RELOC_MIPS_TLS_TPREL_LO16
2411 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2415 MIPS ELF relocations.
2421 BFD_RELOC_MIPS_JUMP_SLOT
2423 MIPS ELF relocations (VxWorks and PLT extensions).
2427 BFD_RELOC_MOXIE_10_PCREL
2429 Moxie ELF relocations.
2433 BFD_RELOC_FRV_LABEL16
2435 BFD_RELOC_FRV_LABEL24
2441 BFD_RELOC_FRV_GPREL12
2443 BFD_RELOC_FRV_GPRELU12
2445 BFD_RELOC_FRV_GPREL32
2447 BFD_RELOC_FRV_GPRELHI
2449 BFD_RELOC_FRV_GPRELLO
2457 BFD_RELOC_FRV_FUNCDESC
2459 BFD_RELOC_FRV_FUNCDESC_GOT12
2461 BFD_RELOC_FRV_FUNCDESC_GOTHI
2463 BFD_RELOC_FRV_FUNCDESC_GOTLO
2465 BFD_RELOC_FRV_FUNCDESC_VALUE
2467 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2469 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2471 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2473 BFD_RELOC_FRV_GOTOFF12
2475 BFD_RELOC_FRV_GOTOFFHI
2477 BFD_RELOC_FRV_GOTOFFLO
2479 BFD_RELOC_FRV_GETTLSOFF
2481 BFD_RELOC_FRV_TLSDESC_VALUE
2483 BFD_RELOC_FRV_GOTTLSDESC12
2485 BFD_RELOC_FRV_GOTTLSDESCHI
2487 BFD_RELOC_FRV_GOTTLSDESCLO
2489 BFD_RELOC_FRV_TLSMOFF12
2491 BFD_RELOC_FRV_TLSMOFFHI
2493 BFD_RELOC_FRV_TLSMOFFLO
2495 BFD_RELOC_FRV_GOTTLSOFF12
2497 BFD_RELOC_FRV_GOTTLSOFFHI
2499 BFD_RELOC_FRV_GOTTLSOFFLO
2501 BFD_RELOC_FRV_TLSOFF
2503 BFD_RELOC_FRV_TLSDESC_RELAX
2505 BFD_RELOC_FRV_GETTLSOFF_RELAX
2507 BFD_RELOC_FRV_TLSOFF_RELAX
2509 BFD_RELOC_FRV_TLSMOFF
2511 Fujitsu Frv Relocations.
2515 BFD_RELOC_MN10300_GOTOFF24
2517 This is a 24bit GOT-relative reloc for the mn10300.
2519 BFD_RELOC_MN10300_GOT32
2521 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2524 BFD_RELOC_MN10300_GOT24
2526 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2529 BFD_RELOC_MN10300_GOT16
2531 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2534 BFD_RELOC_MN10300_COPY
2536 Copy symbol at runtime.
2538 BFD_RELOC_MN10300_GLOB_DAT
2542 BFD_RELOC_MN10300_JMP_SLOT
2546 BFD_RELOC_MN10300_RELATIVE
2548 Adjust by program base.
2550 BFD_RELOC_MN10300_SYM_DIFF
2552 Together with another reloc targeted at the same location,
2553 allows for a value that is the difference of two symbols
2554 in the same section.
2556 BFD_RELOC_MN10300_ALIGN
2558 The addend of this reloc is an alignment power that must
2559 be honoured at the offset's location, regardless of linker
2562 BFD_RELOC_MN10300_TLS_GD
2564 BFD_RELOC_MN10300_TLS_LD
2566 BFD_RELOC_MN10300_TLS_LDO
2568 BFD_RELOC_MN10300_TLS_GOTIE
2570 BFD_RELOC_MN10300_TLS_IE
2572 BFD_RELOC_MN10300_TLS_LE
2574 BFD_RELOC_MN10300_TLS_DTPMOD
2576 BFD_RELOC_MN10300_TLS_DTPOFF
2578 BFD_RELOC_MN10300_TLS_TPOFF
2580 Various TLS-related relocations.
2582 BFD_RELOC_MN10300_32_PCREL
2584 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2587 BFD_RELOC_MN10300_16_PCREL
2589 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2600 BFD_RELOC_386_GLOB_DAT
2602 BFD_RELOC_386_JUMP_SLOT
2604 BFD_RELOC_386_RELATIVE
2606 BFD_RELOC_386_GOTOFF
2610 BFD_RELOC_386_TLS_TPOFF
2612 BFD_RELOC_386_TLS_IE
2614 BFD_RELOC_386_TLS_GOTIE
2616 BFD_RELOC_386_TLS_LE
2618 BFD_RELOC_386_TLS_GD
2620 BFD_RELOC_386_TLS_LDM
2622 BFD_RELOC_386_TLS_LDO_32
2624 BFD_RELOC_386_TLS_IE_32
2626 BFD_RELOC_386_TLS_LE_32
2628 BFD_RELOC_386_TLS_DTPMOD32
2630 BFD_RELOC_386_TLS_DTPOFF32
2632 BFD_RELOC_386_TLS_TPOFF32
2634 BFD_RELOC_386_TLS_GOTDESC
2636 BFD_RELOC_386_TLS_DESC_CALL
2638 BFD_RELOC_386_TLS_DESC
2640 BFD_RELOC_386_IRELATIVE
2642 i386/elf relocations
2645 BFD_RELOC_X86_64_GOT32
2647 BFD_RELOC_X86_64_PLT32
2649 BFD_RELOC_X86_64_COPY
2651 BFD_RELOC_X86_64_GLOB_DAT
2653 BFD_RELOC_X86_64_JUMP_SLOT
2655 BFD_RELOC_X86_64_RELATIVE
2657 BFD_RELOC_X86_64_GOTPCREL
2659 BFD_RELOC_X86_64_32S
2661 BFD_RELOC_X86_64_DTPMOD64
2663 BFD_RELOC_X86_64_DTPOFF64
2665 BFD_RELOC_X86_64_TPOFF64
2667 BFD_RELOC_X86_64_TLSGD
2669 BFD_RELOC_X86_64_TLSLD
2671 BFD_RELOC_X86_64_DTPOFF32
2673 BFD_RELOC_X86_64_GOTTPOFF
2675 BFD_RELOC_X86_64_TPOFF32
2677 BFD_RELOC_X86_64_GOTOFF64
2679 BFD_RELOC_X86_64_GOTPC32
2681 BFD_RELOC_X86_64_GOT64
2683 BFD_RELOC_X86_64_GOTPCREL64
2685 BFD_RELOC_X86_64_GOTPC64
2687 BFD_RELOC_X86_64_GOTPLT64
2689 BFD_RELOC_X86_64_PLTOFF64
2691 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2693 BFD_RELOC_X86_64_TLSDESC_CALL
2695 BFD_RELOC_X86_64_TLSDESC
2697 BFD_RELOC_X86_64_IRELATIVE
2699 BFD_RELOC_X86_64_PC32_BND
2701 BFD_RELOC_X86_64_PLT32_BND
2703 x86-64/elf relocations
2706 BFD_RELOC_NS32K_IMM_8
2708 BFD_RELOC_NS32K_IMM_16
2710 BFD_RELOC_NS32K_IMM_32
2712 BFD_RELOC_NS32K_IMM_8_PCREL
2714 BFD_RELOC_NS32K_IMM_16_PCREL
2716 BFD_RELOC_NS32K_IMM_32_PCREL
2718 BFD_RELOC_NS32K_DISP_8
2720 BFD_RELOC_NS32K_DISP_16
2722 BFD_RELOC_NS32K_DISP_32
2724 BFD_RELOC_NS32K_DISP_8_PCREL
2726 BFD_RELOC_NS32K_DISP_16_PCREL
2728 BFD_RELOC_NS32K_DISP_32_PCREL
2733 BFD_RELOC_PDP11_DISP_8_PCREL
2735 BFD_RELOC_PDP11_DISP_6_PCREL
2740 BFD_RELOC_PJ_CODE_HI16
2742 BFD_RELOC_PJ_CODE_LO16
2744 BFD_RELOC_PJ_CODE_DIR16
2746 BFD_RELOC_PJ_CODE_DIR32
2748 BFD_RELOC_PJ_CODE_REL16
2750 BFD_RELOC_PJ_CODE_REL32
2752 Picojava relocs. Not all of these appear in object files.
2763 BFD_RELOC_PPC_B16_BRTAKEN
2765 BFD_RELOC_PPC_B16_BRNTAKEN
2769 BFD_RELOC_PPC_BA16_BRTAKEN
2771 BFD_RELOC_PPC_BA16_BRNTAKEN
2775 BFD_RELOC_PPC_GLOB_DAT
2777 BFD_RELOC_PPC_JMP_SLOT
2779 BFD_RELOC_PPC_RELATIVE
2781 BFD_RELOC_PPC_LOCAL24PC
2783 BFD_RELOC_PPC_EMB_NADDR32
2785 BFD_RELOC_PPC_EMB_NADDR16
2787 BFD_RELOC_PPC_EMB_NADDR16_LO
2789 BFD_RELOC_PPC_EMB_NADDR16_HI
2791 BFD_RELOC_PPC_EMB_NADDR16_HA
2793 BFD_RELOC_PPC_EMB_SDAI16
2795 BFD_RELOC_PPC_EMB_SDA2I16
2797 BFD_RELOC_PPC_EMB_SDA2REL
2799 BFD_RELOC_PPC_EMB_SDA21
2801 BFD_RELOC_PPC_EMB_MRKREF
2803 BFD_RELOC_PPC_EMB_RELSEC16
2805 BFD_RELOC_PPC_EMB_RELST_LO
2807 BFD_RELOC_PPC_EMB_RELST_HI
2809 BFD_RELOC_PPC_EMB_RELST_HA
2811 BFD_RELOC_PPC_EMB_BIT_FLD
2813 BFD_RELOC_PPC_EMB_RELSDA
2815 BFD_RELOC_PPC_VLE_REL8
2817 BFD_RELOC_PPC_VLE_REL15
2819 BFD_RELOC_PPC_VLE_REL24
2821 BFD_RELOC_PPC_VLE_LO16A
2823 BFD_RELOC_PPC_VLE_LO16D
2825 BFD_RELOC_PPC_VLE_HI16A
2827 BFD_RELOC_PPC_VLE_HI16D
2829 BFD_RELOC_PPC_VLE_HA16A
2831 BFD_RELOC_PPC_VLE_HA16D
2833 BFD_RELOC_PPC_VLE_SDA21
2835 BFD_RELOC_PPC_VLE_SDA21_LO
2837 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2839 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2841 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2843 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2845 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2847 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2849 BFD_RELOC_PPC64_HIGHER
2851 BFD_RELOC_PPC64_HIGHER_S
2853 BFD_RELOC_PPC64_HIGHEST
2855 BFD_RELOC_PPC64_HIGHEST_S
2857 BFD_RELOC_PPC64_TOC16_LO
2859 BFD_RELOC_PPC64_TOC16_HI
2861 BFD_RELOC_PPC64_TOC16_HA
2865 BFD_RELOC_PPC64_PLTGOT16
2867 BFD_RELOC_PPC64_PLTGOT16_LO
2869 BFD_RELOC_PPC64_PLTGOT16_HI
2871 BFD_RELOC_PPC64_PLTGOT16_HA
2873 BFD_RELOC_PPC64_ADDR16_DS
2875 BFD_RELOC_PPC64_ADDR16_LO_DS
2877 BFD_RELOC_PPC64_GOT16_DS
2879 BFD_RELOC_PPC64_GOT16_LO_DS
2881 BFD_RELOC_PPC64_PLT16_LO_DS
2883 BFD_RELOC_PPC64_SECTOFF_DS
2885 BFD_RELOC_PPC64_SECTOFF_LO_DS
2887 BFD_RELOC_PPC64_TOC16_DS
2889 BFD_RELOC_PPC64_TOC16_LO_DS
2891 BFD_RELOC_PPC64_PLTGOT16_DS
2893 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2895 BFD_RELOC_PPC64_ADDR16_HIGH
2897 BFD_RELOC_PPC64_ADDR16_HIGHA
2899 BFD_RELOC_PPC64_ADDR64_LOCAL
2901 Power(rs6000) and PowerPC relocations.
2910 BFD_RELOC_PPC_DTPMOD
2912 BFD_RELOC_PPC_TPREL16
2914 BFD_RELOC_PPC_TPREL16_LO
2916 BFD_RELOC_PPC_TPREL16_HI
2918 BFD_RELOC_PPC_TPREL16_HA
2922 BFD_RELOC_PPC_DTPREL16
2924 BFD_RELOC_PPC_DTPREL16_LO
2926 BFD_RELOC_PPC_DTPREL16_HI
2928 BFD_RELOC_PPC_DTPREL16_HA
2930 BFD_RELOC_PPC_DTPREL
2932 BFD_RELOC_PPC_GOT_TLSGD16
2934 BFD_RELOC_PPC_GOT_TLSGD16_LO
2936 BFD_RELOC_PPC_GOT_TLSGD16_HI
2938 BFD_RELOC_PPC_GOT_TLSGD16_HA
2940 BFD_RELOC_PPC_GOT_TLSLD16
2942 BFD_RELOC_PPC_GOT_TLSLD16_LO
2944 BFD_RELOC_PPC_GOT_TLSLD16_HI
2946 BFD_RELOC_PPC_GOT_TLSLD16_HA
2948 BFD_RELOC_PPC_GOT_TPREL16
2950 BFD_RELOC_PPC_GOT_TPREL16_LO
2952 BFD_RELOC_PPC_GOT_TPREL16_HI
2954 BFD_RELOC_PPC_GOT_TPREL16_HA
2956 BFD_RELOC_PPC_GOT_DTPREL16
2958 BFD_RELOC_PPC_GOT_DTPREL16_LO
2960 BFD_RELOC_PPC_GOT_DTPREL16_HI
2962 BFD_RELOC_PPC_GOT_DTPREL16_HA
2964 BFD_RELOC_PPC64_TPREL16_DS
2966 BFD_RELOC_PPC64_TPREL16_LO_DS
2968 BFD_RELOC_PPC64_TPREL16_HIGHER
2970 BFD_RELOC_PPC64_TPREL16_HIGHERA
2972 BFD_RELOC_PPC64_TPREL16_HIGHEST
2974 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2976 BFD_RELOC_PPC64_DTPREL16_DS
2978 BFD_RELOC_PPC64_DTPREL16_LO_DS
2980 BFD_RELOC_PPC64_DTPREL16_HIGHER
2982 BFD_RELOC_PPC64_DTPREL16_HIGHERA
2984 BFD_RELOC_PPC64_DTPREL16_HIGHEST
2986 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
2988 BFD_RELOC_PPC64_TPREL16_HIGH
2990 BFD_RELOC_PPC64_TPREL16_HIGHA
2992 BFD_RELOC_PPC64_DTPREL16_HIGH
2994 BFD_RELOC_PPC64_DTPREL16_HIGHA
2996 PowerPC and PowerPC64 thread-local storage relocations.
3001 IBM 370/390 relocations
3006 The type of reloc used to build a constructor table - at the moment
3007 probably a 32 bit wide absolute relocation, but the target can choose.
3008 It generally does map to one of the other relocation types.
3011 BFD_RELOC_ARM_PCREL_BRANCH
3013 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
3014 not stored in the instruction.
3016 BFD_RELOC_ARM_PCREL_BLX
3018 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
3019 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3020 field in the instruction.
3022 BFD_RELOC_THUMB_PCREL_BLX
3024 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
3025 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
3026 field in the instruction.
3028 BFD_RELOC_ARM_PCREL_CALL
3030 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
3032 BFD_RELOC_ARM_PCREL_JUMP
3034 ARM 26-bit pc-relative branch for B or conditional BL instruction.
3037 BFD_RELOC_THUMB_PCREL_BRANCH7
3039 BFD_RELOC_THUMB_PCREL_BRANCH9
3041 BFD_RELOC_THUMB_PCREL_BRANCH12
3043 BFD_RELOC_THUMB_PCREL_BRANCH20
3045 BFD_RELOC_THUMB_PCREL_BRANCH23
3047 BFD_RELOC_THUMB_PCREL_BRANCH25
3049 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
3050 The lowest bit must be zero and is not stored in the instruction.
3051 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
3052 "nn" one smaller in all cases. Note further that BRANCH23
3053 corresponds to R_ARM_THM_CALL.
3056 BFD_RELOC_ARM_OFFSET_IMM
3058 12-bit immediate offset, used in ARM-format ldr and str instructions.
3061 BFD_RELOC_ARM_THUMB_OFFSET
3063 5-bit immediate offset, used in Thumb-format ldr and str instructions.
3066 BFD_RELOC_ARM_TARGET1
3068 Pc-relative or absolute relocation depending on target. Used for
3069 entries in .init_array sections.
3071 BFD_RELOC_ARM_ROSEGREL32
3073 Read-only segment base relative address.
3075 BFD_RELOC_ARM_SBREL32
3077 Data segment base relative address.
3079 BFD_RELOC_ARM_TARGET2
3081 This reloc is used for references to RTTI data from exception handling
3082 tables. The actual definition depends on the target. It may be a
3083 pc-relative or some form of GOT-indirect relocation.
3085 BFD_RELOC_ARM_PREL31
3087 31-bit PC relative address.
3093 BFD_RELOC_ARM_MOVW_PCREL
3095 BFD_RELOC_ARM_MOVT_PCREL
3097 BFD_RELOC_ARM_THUMB_MOVW
3099 BFD_RELOC_ARM_THUMB_MOVT
3101 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3103 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3105 Low and High halfword relocations for MOVW and MOVT instructions.
3108 BFD_RELOC_ARM_JUMP_SLOT
3110 BFD_RELOC_ARM_GLOB_DAT
3116 BFD_RELOC_ARM_RELATIVE
3118 BFD_RELOC_ARM_GOTOFF
3122 BFD_RELOC_ARM_GOT_PREL
3124 Relocations for setting up GOTs and PLTs for shared libraries.
3127 BFD_RELOC_ARM_TLS_GD32
3129 BFD_RELOC_ARM_TLS_LDO32
3131 BFD_RELOC_ARM_TLS_LDM32
3133 BFD_RELOC_ARM_TLS_DTPOFF32
3135 BFD_RELOC_ARM_TLS_DTPMOD32
3137 BFD_RELOC_ARM_TLS_TPOFF32
3139 BFD_RELOC_ARM_TLS_IE32
3141 BFD_RELOC_ARM_TLS_LE32
3143 BFD_RELOC_ARM_TLS_GOTDESC
3145 BFD_RELOC_ARM_TLS_CALL
3147 BFD_RELOC_ARM_THM_TLS_CALL
3149 BFD_RELOC_ARM_TLS_DESCSEQ
3151 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3153 BFD_RELOC_ARM_TLS_DESC
3155 ARM thread-local storage relocations.
3158 BFD_RELOC_ARM_ALU_PC_G0_NC
3160 BFD_RELOC_ARM_ALU_PC_G0
3162 BFD_RELOC_ARM_ALU_PC_G1_NC
3164 BFD_RELOC_ARM_ALU_PC_G1
3166 BFD_RELOC_ARM_ALU_PC_G2
3168 BFD_RELOC_ARM_LDR_PC_G0
3170 BFD_RELOC_ARM_LDR_PC_G1
3172 BFD_RELOC_ARM_LDR_PC_G2
3174 BFD_RELOC_ARM_LDRS_PC_G0
3176 BFD_RELOC_ARM_LDRS_PC_G1
3178 BFD_RELOC_ARM_LDRS_PC_G2
3180 BFD_RELOC_ARM_LDC_PC_G0
3182 BFD_RELOC_ARM_LDC_PC_G1
3184 BFD_RELOC_ARM_LDC_PC_G2
3186 BFD_RELOC_ARM_ALU_SB_G0_NC
3188 BFD_RELOC_ARM_ALU_SB_G0
3190 BFD_RELOC_ARM_ALU_SB_G1_NC
3192 BFD_RELOC_ARM_ALU_SB_G1
3194 BFD_RELOC_ARM_ALU_SB_G2
3196 BFD_RELOC_ARM_LDR_SB_G0
3198 BFD_RELOC_ARM_LDR_SB_G1
3200 BFD_RELOC_ARM_LDR_SB_G2
3202 BFD_RELOC_ARM_LDRS_SB_G0
3204 BFD_RELOC_ARM_LDRS_SB_G1
3206 BFD_RELOC_ARM_LDRS_SB_G2
3208 BFD_RELOC_ARM_LDC_SB_G0
3210 BFD_RELOC_ARM_LDC_SB_G1
3212 BFD_RELOC_ARM_LDC_SB_G2
3214 ARM group relocations.
3219 Annotation of BX instructions.
3222 BFD_RELOC_ARM_IRELATIVE
3224 ARM support for STT_GNU_IFUNC.
3227 BFD_RELOC_ARM_IMMEDIATE
3229 BFD_RELOC_ARM_ADRL_IMMEDIATE
3231 BFD_RELOC_ARM_T32_IMMEDIATE
3233 BFD_RELOC_ARM_T32_ADD_IMM
3235 BFD_RELOC_ARM_T32_IMM12
3237 BFD_RELOC_ARM_T32_ADD_PC12
3239 BFD_RELOC_ARM_SHIFT_IMM
3249 BFD_RELOC_ARM_CP_OFF_IMM
3251 BFD_RELOC_ARM_CP_OFF_IMM_S2
3253 BFD_RELOC_ARM_T32_CP_OFF_IMM
3255 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3257 BFD_RELOC_ARM_ADR_IMM
3259 BFD_RELOC_ARM_LDR_IMM
3261 BFD_RELOC_ARM_LITERAL
3263 BFD_RELOC_ARM_IN_POOL
3265 BFD_RELOC_ARM_OFFSET_IMM8
3267 BFD_RELOC_ARM_T32_OFFSET_U8
3269 BFD_RELOC_ARM_T32_OFFSET_IMM
3271 BFD_RELOC_ARM_HWLITERAL
3273 BFD_RELOC_ARM_THUMB_ADD
3275 BFD_RELOC_ARM_THUMB_IMM
3277 BFD_RELOC_ARM_THUMB_SHIFT
3279 These relocs are only used within the ARM assembler. They are not
3280 (at present) written to any object files.
3283 BFD_RELOC_SH_PCDISP8BY2
3285 BFD_RELOC_SH_PCDISP12BY2
3293 BFD_RELOC_SH_DISP12BY2
3295 BFD_RELOC_SH_DISP12BY4
3297 BFD_RELOC_SH_DISP12BY8
3301 BFD_RELOC_SH_DISP20BY8
3305 BFD_RELOC_SH_IMM4BY2
3307 BFD_RELOC_SH_IMM4BY4
3311 BFD_RELOC_SH_IMM8BY2
3313 BFD_RELOC_SH_IMM8BY4
3315 BFD_RELOC_SH_PCRELIMM8BY2
3317 BFD_RELOC_SH_PCRELIMM8BY4
3319 BFD_RELOC_SH_SWITCH16
3321 BFD_RELOC_SH_SWITCH32
3335 BFD_RELOC_SH_LOOP_START
3337 BFD_RELOC_SH_LOOP_END
3341 BFD_RELOC_SH_GLOB_DAT
3343 BFD_RELOC_SH_JMP_SLOT
3345 BFD_RELOC_SH_RELATIVE
3349 BFD_RELOC_SH_GOT_LOW16
3351 BFD_RELOC_SH_GOT_MEDLOW16
3353 BFD_RELOC_SH_GOT_MEDHI16
3355 BFD_RELOC_SH_GOT_HI16
3357 BFD_RELOC_SH_GOTPLT_LOW16
3359 BFD_RELOC_SH_GOTPLT_MEDLOW16
3361 BFD_RELOC_SH_GOTPLT_MEDHI16
3363 BFD_RELOC_SH_GOTPLT_HI16
3365 BFD_RELOC_SH_PLT_LOW16
3367 BFD_RELOC_SH_PLT_MEDLOW16
3369 BFD_RELOC_SH_PLT_MEDHI16
3371 BFD_RELOC_SH_PLT_HI16
3373 BFD_RELOC_SH_GOTOFF_LOW16
3375 BFD_RELOC_SH_GOTOFF_MEDLOW16
3377 BFD_RELOC_SH_GOTOFF_MEDHI16
3379 BFD_RELOC_SH_GOTOFF_HI16
3381 BFD_RELOC_SH_GOTPC_LOW16
3383 BFD_RELOC_SH_GOTPC_MEDLOW16
3385 BFD_RELOC_SH_GOTPC_MEDHI16
3387 BFD_RELOC_SH_GOTPC_HI16
3391 BFD_RELOC_SH_GLOB_DAT64
3393 BFD_RELOC_SH_JMP_SLOT64
3395 BFD_RELOC_SH_RELATIVE64
3397 BFD_RELOC_SH_GOT10BY4
3399 BFD_RELOC_SH_GOT10BY8
3401 BFD_RELOC_SH_GOTPLT10BY4
3403 BFD_RELOC_SH_GOTPLT10BY8
3405 BFD_RELOC_SH_GOTPLT32
3407 BFD_RELOC_SH_SHMEDIA_CODE
3413 BFD_RELOC_SH_IMMS6BY32
3419 BFD_RELOC_SH_IMMS10BY2
3421 BFD_RELOC_SH_IMMS10BY4
3423 BFD_RELOC_SH_IMMS10BY8
3429 BFD_RELOC_SH_IMM_LOW16
3431 BFD_RELOC_SH_IMM_LOW16_PCREL
3433 BFD_RELOC_SH_IMM_MEDLOW16
3435 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3437 BFD_RELOC_SH_IMM_MEDHI16
3439 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3441 BFD_RELOC_SH_IMM_HI16
3443 BFD_RELOC_SH_IMM_HI16_PCREL
3447 BFD_RELOC_SH_TLS_GD_32
3449 BFD_RELOC_SH_TLS_LD_32
3451 BFD_RELOC_SH_TLS_LDO_32
3453 BFD_RELOC_SH_TLS_IE_32
3455 BFD_RELOC_SH_TLS_LE_32
3457 BFD_RELOC_SH_TLS_DTPMOD32
3459 BFD_RELOC_SH_TLS_DTPOFF32
3461 BFD_RELOC_SH_TLS_TPOFF32
3465 BFD_RELOC_SH_GOTOFF20
3467 BFD_RELOC_SH_GOTFUNCDESC
3469 BFD_RELOC_SH_GOTFUNCDESC20
3471 BFD_RELOC_SH_GOTOFFFUNCDESC
3473 BFD_RELOC_SH_GOTOFFFUNCDESC20
3475 BFD_RELOC_SH_FUNCDESC
3477 Renesas / SuperH SH relocs. Not all of these appear in object files.
3480 BFD_RELOC_ARC_B22_PCREL
3483 ARC 22 bit pc-relative branch. The lowest two bits must be zero and are
3484 not stored in the instruction. The high 20 bits are installed in bits 26
3485 through 7 of the instruction.
3489 ARC 26 bit absolute branch. The lowest two bits must be zero and are not
3490 stored in the instruction. The high 24 bits are installed in bits 23
3494 BFD_RELOC_BFIN_16_IMM
3496 ADI Blackfin 16 bit immediate absolute reloc.
3498 BFD_RELOC_BFIN_16_HIGH
3500 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3502 BFD_RELOC_BFIN_4_PCREL
3504 ADI Blackfin 'a' part of LSETUP.
3506 BFD_RELOC_BFIN_5_PCREL
3510 BFD_RELOC_BFIN_16_LOW
3512 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3514 BFD_RELOC_BFIN_10_PCREL
3518 BFD_RELOC_BFIN_11_PCREL
3520 ADI Blackfin 'b' part of LSETUP.
3522 BFD_RELOC_BFIN_12_PCREL_JUMP
3526 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3528 ADI Blackfin Short jump, pcrel.
3530 BFD_RELOC_BFIN_24_PCREL_CALL_X
3532 ADI Blackfin Call.x not implemented.
3534 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3536 ADI Blackfin Long Jump pcrel.
3538 BFD_RELOC_BFIN_GOT17M4
3540 BFD_RELOC_BFIN_GOTHI
3542 BFD_RELOC_BFIN_GOTLO
3544 BFD_RELOC_BFIN_FUNCDESC
3546 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3548 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3550 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3552 BFD_RELOC_BFIN_FUNCDESC_VALUE
3554 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3556 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3558 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3560 BFD_RELOC_BFIN_GOTOFF17M4
3562 BFD_RELOC_BFIN_GOTOFFHI
3564 BFD_RELOC_BFIN_GOTOFFLO
3566 ADI Blackfin FD-PIC relocations.
3570 ADI Blackfin GOT relocation.
3572 BFD_RELOC_BFIN_PLTPC
3574 ADI Blackfin PLTPC relocation.
3576 BFD_ARELOC_BFIN_PUSH
3578 ADI Blackfin arithmetic relocation.
3580 BFD_ARELOC_BFIN_CONST
3582 ADI Blackfin arithmetic relocation.
3586 ADI Blackfin arithmetic relocation.
3590 ADI Blackfin arithmetic relocation.
3592 BFD_ARELOC_BFIN_MULT
3594 ADI Blackfin arithmetic relocation.
3598 ADI Blackfin arithmetic relocation.
3602 ADI Blackfin arithmetic relocation.
3604 BFD_ARELOC_BFIN_LSHIFT
3606 ADI Blackfin arithmetic relocation.
3608 BFD_ARELOC_BFIN_RSHIFT
3610 ADI Blackfin arithmetic relocation.
3614 ADI Blackfin arithmetic relocation.
3618 ADI Blackfin arithmetic relocation.
3622 ADI Blackfin arithmetic relocation.
3624 BFD_ARELOC_BFIN_LAND
3626 ADI Blackfin arithmetic relocation.
3630 ADI Blackfin arithmetic relocation.
3634 ADI Blackfin arithmetic relocation.
3638 ADI Blackfin arithmetic relocation.
3640 BFD_ARELOC_BFIN_COMP
3642 ADI Blackfin arithmetic relocation.
3644 BFD_ARELOC_BFIN_PAGE
3646 ADI Blackfin arithmetic relocation.
3648 BFD_ARELOC_BFIN_HWPAGE
3650 ADI Blackfin arithmetic relocation.
3652 BFD_ARELOC_BFIN_ADDR
3654 ADI Blackfin arithmetic relocation.
3657 BFD_RELOC_D10V_10_PCREL_R
3659 Mitsubishi D10V relocs.
3660 This is a 10-bit reloc with the right 2 bits
3663 BFD_RELOC_D10V_10_PCREL_L
3665 Mitsubishi D10V relocs.
3666 This is a 10-bit reloc with the right 2 bits
3667 assumed to be 0. This is the same as the previous reloc
3668 except it is in the left container, i.e.,
3669 shifted left 15 bits.
3673 This is an 18-bit reloc with the right 2 bits
3676 BFD_RELOC_D10V_18_PCREL
3678 This is an 18-bit reloc with the right 2 bits
3684 Mitsubishi D30V relocs.
3685 This is a 6-bit absolute reloc.
3687 BFD_RELOC_D30V_9_PCREL
3689 This is a 6-bit pc-relative reloc with
3690 the right 3 bits assumed to be 0.
3692 BFD_RELOC_D30V_9_PCREL_R
3694 This is a 6-bit pc-relative reloc with
3695 the right 3 bits assumed to be 0. Same
3696 as the previous reloc but on the right side
3701 This is a 12-bit absolute reloc with the
3702 right 3 bitsassumed to be 0.
3704 BFD_RELOC_D30V_15_PCREL
3706 This is a 12-bit pc-relative reloc with
3707 the right 3 bits assumed to be 0.
3709 BFD_RELOC_D30V_15_PCREL_R
3711 This is a 12-bit pc-relative reloc with
3712 the right 3 bits assumed to be 0. Same
3713 as the previous reloc but on the right side
3718 This is an 18-bit absolute reloc with
3719 the right 3 bits assumed to be 0.
3721 BFD_RELOC_D30V_21_PCREL
3723 This is an 18-bit pc-relative reloc with
3724 the right 3 bits assumed to be 0.
3726 BFD_RELOC_D30V_21_PCREL_R
3728 This is an 18-bit pc-relative reloc with
3729 the right 3 bits assumed to be 0. Same
3730 as the previous reloc but on the right side
3735 This is a 32-bit absolute reloc.
3737 BFD_RELOC_D30V_32_PCREL
3739 This is a 32-bit pc-relative reloc.
3742 BFD_RELOC_DLX_HI16_S
3757 BFD_RELOC_M32C_RL_JUMP
3759 BFD_RELOC_M32C_RL_1ADDR
3761 BFD_RELOC_M32C_RL_2ADDR
3763 Renesas M16C/M32C Relocations.
3768 Renesas M32R (formerly Mitsubishi M32R) relocs.
3769 This is a 24 bit absolute address.
3771 BFD_RELOC_M32R_10_PCREL
3773 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3775 BFD_RELOC_M32R_18_PCREL
3777 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3779 BFD_RELOC_M32R_26_PCREL
3781 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3783 BFD_RELOC_M32R_HI16_ULO
3785 This is a 16-bit reloc containing the high 16 bits of an address
3786 used when the lower 16 bits are treated as unsigned.
3788 BFD_RELOC_M32R_HI16_SLO
3790 This is a 16-bit reloc containing the high 16 bits of an address
3791 used when the lower 16 bits are treated as signed.
3795 This is a 16-bit reloc containing the lower 16 bits of an address.
3797 BFD_RELOC_M32R_SDA16
3799 This is a 16-bit reloc containing the small data area offset for use in
3800 add3, load, and store instructions.
3802 BFD_RELOC_M32R_GOT24
3804 BFD_RELOC_M32R_26_PLTREL
3808 BFD_RELOC_M32R_GLOB_DAT
3810 BFD_RELOC_M32R_JMP_SLOT
3812 BFD_RELOC_M32R_RELATIVE
3814 BFD_RELOC_M32R_GOTOFF
3816 BFD_RELOC_M32R_GOTOFF_HI_ULO
3818 BFD_RELOC_M32R_GOTOFF_HI_SLO
3820 BFD_RELOC_M32R_GOTOFF_LO
3822 BFD_RELOC_M32R_GOTPC24
3824 BFD_RELOC_M32R_GOT16_HI_ULO
3826 BFD_RELOC_M32R_GOT16_HI_SLO
3828 BFD_RELOC_M32R_GOT16_LO
3830 BFD_RELOC_M32R_GOTPC_HI_ULO
3832 BFD_RELOC_M32R_GOTPC_HI_SLO
3834 BFD_RELOC_M32R_GOTPC_LO
3843 This is a 20 bit absolute address.
3845 BFD_RELOC_NDS32_9_PCREL
3847 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3849 BFD_RELOC_NDS32_WORD_9_PCREL
3851 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3853 BFD_RELOC_NDS32_15_PCREL
3855 This is an 15-bit reloc with the right 1 bit assumed to be 0.
3857 BFD_RELOC_NDS32_17_PCREL
3859 This is an 17-bit reloc with the right 1 bit assumed to be 0.
3861 BFD_RELOC_NDS32_25_PCREL
3863 This is a 25-bit reloc with the right 1 bit assumed to be 0.
3865 BFD_RELOC_NDS32_HI20
3867 This is a 20-bit reloc containing the high 20 bits of an address
3868 used with the lower 12 bits
3870 BFD_RELOC_NDS32_LO12S3
3872 This is a 12-bit reloc containing the lower 12 bits of an address
3873 then shift right by 3. This is used with ldi,sdi...
3875 BFD_RELOC_NDS32_LO12S2
3877 This is a 12-bit reloc containing the lower 12 bits of an address
3878 then shift left by 2. This is used with lwi,swi...
3880 BFD_RELOC_NDS32_LO12S1
3882 This is a 12-bit reloc containing the lower 12 bits of an address
3883 then shift left by 1. This is used with lhi,shi...
3885 BFD_RELOC_NDS32_LO12S0
3887 This is a 12-bit reloc containing the lower 12 bits of an address
3888 then shift left by 0. This is used with lbisbi...
3890 BFD_RELOC_NDS32_LO12S0_ORI
3892 This is a 12-bit reloc containing the lower 12 bits of an address
3893 then shift left by 0. This is only used with branch relaxations
3895 BFD_RELOC_NDS32_SDA15S3
3897 This is a 15-bit reloc containing the small data area 18-bit signed offset
3898 and shift left by 3 for use in ldi, sdi...
3900 BFD_RELOC_NDS32_SDA15S2
3902 This is a 15-bit reloc containing the small data area 17-bit signed offset
3903 and shift left by 2 for use in lwi, swi...
3905 BFD_RELOC_NDS32_SDA15S1
3907 This is a 15-bit reloc containing the small data area 16-bit signed offset
3908 and shift left by 1 for use in lhi, shi...
3910 BFD_RELOC_NDS32_SDA15S0
3912 This is a 15-bit reloc containing the small data area 15-bit signed offset
3913 and shift left by 0 for use in lbi, sbi...
3915 BFD_RELOC_NDS32_SDA16S3
3917 This is a 16-bit reloc containing the small data area 16-bit signed offset
3920 BFD_RELOC_NDS32_SDA17S2
3922 This is a 17-bit reloc containing the small data area 17-bit signed offset
3923 and shift left by 2 for use in lwi.gp, swi.gp...
3925 BFD_RELOC_NDS32_SDA18S1
3927 This is a 18-bit reloc containing the small data area 18-bit signed offset
3928 and shift left by 1 for use in lhi.gp, shi.gp...
3930 BFD_RELOC_NDS32_SDA19S0
3932 This is a 19-bit reloc containing the small data area 19-bit signed offset
3933 and shift left by 0 for use in lbi.gp, sbi.gp...
3935 BFD_RELOC_NDS32_GOT20
3937 BFD_RELOC_NDS32_9_PLTREL
3939 BFD_RELOC_NDS32_25_PLTREL
3941 BFD_RELOC_NDS32_COPY
3943 BFD_RELOC_NDS32_GLOB_DAT
3945 BFD_RELOC_NDS32_JMP_SLOT
3947 BFD_RELOC_NDS32_RELATIVE
3949 BFD_RELOC_NDS32_GOTOFF
3951 BFD_RELOC_NDS32_GOTOFF_HI20
3953 BFD_RELOC_NDS32_GOTOFF_LO12
3955 BFD_RELOC_NDS32_GOTPC20
3957 BFD_RELOC_NDS32_GOT_HI20
3959 BFD_RELOC_NDS32_GOT_LO12
3961 BFD_RELOC_NDS32_GOTPC_HI20
3963 BFD_RELOC_NDS32_GOTPC_LO12
3967 BFD_RELOC_NDS32_INSN16
3969 BFD_RELOC_NDS32_LABEL
3971 BFD_RELOC_NDS32_LONGCALL1
3973 BFD_RELOC_NDS32_LONGCALL2
3975 BFD_RELOC_NDS32_LONGCALL3
3977 BFD_RELOC_NDS32_LONGJUMP1
3979 BFD_RELOC_NDS32_LONGJUMP2
3981 BFD_RELOC_NDS32_LONGJUMP3
3983 BFD_RELOC_NDS32_LOADSTORE
3985 BFD_RELOC_NDS32_9_FIXED
3987 BFD_RELOC_NDS32_15_FIXED
3989 BFD_RELOC_NDS32_17_FIXED
3991 BFD_RELOC_NDS32_25_FIXED
3995 BFD_RELOC_NDS32_PLTREL_HI20
3997 BFD_RELOC_NDS32_PLTREL_LO12
3999 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4001 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4005 BFD_RELOC_NDS32_SDA12S2_DP
4007 BFD_RELOC_NDS32_SDA12S2_SP
4009 BFD_RELOC_NDS32_LO12S2_DP
4011 BFD_RELOC_NDS32_LO12S2_SP
4015 BFD_RELOC_NDS32_DWARF2_OP1
4017 BFD_RELOC_NDS32_DWARF2_OP2
4019 BFD_RELOC_NDS32_DWARF2_LEB
4021 for dwarf2 debug_line.
4023 BFD_RELOC_NDS32_UPDATE_TA
4025 for eliminate 16-bit instructions
4027 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4029 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4031 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4033 BFD_RELOC_NDS32_GOT_LO15
4035 BFD_RELOC_NDS32_GOT_LO19
4037 BFD_RELOC_NDS32_GOTOFF_LO15
4039 BFD_RELOC_NDS32_GOTOFF_LO19
4041 BFD_RELOC_NDS32_GOT15S2
4043 BFD_RELOC_NDS32_GOT17S2
4045 for PIC object relaxation
4050 This is a 5 bit absolute address.
4052 BFD_RELOC_NDS32_10_UPCREL
4054 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4056 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4058 If fp were omitted, fp can used as another gp.
4060 BFD_RELOC_NDS32_RELAX_ENTRY
4062 BFD_RELOC_NDS32_GOT_SUFF
4064 BFD_RELOC_NDS32_GOTOFF_SUFF
4066 BFD_RELOC_NDS32_PLT_GOT_SUFF
4068 BFD_RELOC_NDS32_MULCALL_SUFF
4072 BFD_RELOC_NDS32_PTR_COUNT
4074 BFD_RELOC_NDS32_PTR_RESOLVED
4076 BFD_RELOC_NDS32_PLTBLOCK
4078 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4080 BFD_RELOC_NDS32_RELAX_REGION_END
4082 BFD_RELOC_NDS32_MINUEND
4084 BFD_RELOC_NDS32_SUBTRAHEND
4086 BFD_RELOC_NDS32_DIFF8
4088 BFD_RELOC_NDS32_DIFF16
4090 BFD_RELOC_NDS32_DIFF32
4092 BFD_RELOC_NDS32_DIFF_ULEB128
4094 BFD_RELOC_NDS32_25_ABS
4096 BFD_RELOC_NDS32_DATA
4098 BFD_RELOC_NDS32_TRAN
4100 BFD_RELOC_NDS32_17IFC_PCREL
4102 BFD_RELOC_NDS32_10IFCU_PCREL
4104 relaxation relative relocation types
4108 BFD_RELOC_V850_9_PCREL
4110 This is a 9-bit reloc
4112 BFD_RELOC_V850_22_PCREL
4114 This is a 22-bit reloc
4117 BFD_RELOC_V850_SDA_16_16_OFFSET
4119 This is a 16 bit offset from the short data area pointer.
4121 BFD_RELOC_V850_SDA_15_16_OFFSET
4123 This is a 16 bit offset (of which only 15 bits are used) from the
4124 short data area pointer.
4126 BFD_RELOC_V850_ZDA_16_16_OFFSET
4128 This is a 16 bit offset from the zero data area pointer.
4130 BFD_RELOC_V850_ZDA_15_16_OFFSET
4132 This is a 16 bit offset (of which only 15 bits are used) from the
4133 zero data area pointer.
4135 BFD_RELOC_V850_TDA_6_8_OFFSET
4137 This is an 8 bit offset (of which only 6 bits are used) from the
4138 tiny data area pointer.
4140 BFD_RELOC_V850_TDA_7_8_OFFSET
4142 This is an 8bit offset (of which only 7 bits are used) from the tiny
4145 BFD_RELOC_V850_TDA_7_7_OFFSET
4147 This is a 7 bit offset from the tiny data area pointer.
4149 BFD_RELOC_V850_TDA_16_16_OFFSET
4151 This is a 16 bit offset from the tiny data area pointer.
4154 BFD_RELOC_V850_TDA_4_5_OFFSET
4156 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4159 BFD_RELOC_V850_TDA_4_4_OFFSET
4161 This is a 4 bit offset from the tiny data area pointer.
4163 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4165 This is a 16 bit offset from the short data area pointer, with the
4166 bits placed non-contiguously in the instruction.
4168 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4170 This is a 16 bit offset from the zero data area pointer, with the
4171 bits placed non-contiguously in the instruction.
4173 BFD_RELOC_V850_CALLT_6_7_OFFSET
4175 This is a 6 bit offset from the call table base pointer.
4177 BFD_RELOC_V850_CALLT_16_16_OFFSET
4179 This is a 16 bit offset from the call table base pointer.
4181 BFD_RELOC_V850_LONGCALL
4183 Used for relaxing indirect function calls.
4185 BFD_RELOC_V850_LONGJUMP
4187 Used for relaxing indirect jumps.
4189 BFD_RELOC_V850_ALIGN
4191 Used to maintain alignment whilst relaxing.
4193 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4195 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4198 BFD_RELOC_V850_16_PCREL
4200 This is a 16-bit reloc.
4202 BFD_RELOC_V850_17_PCREL
4204 This is a 17-bit reloc.
4208 This is a 23-bit reloc.
4210 BFD_RELOC_V850_32_PCREL
4212 This is a 32-bit reloc.
4214 BFD_RELOC_V850_32_ABS
4216 This is a 32-bit reloc.
4218 BFD_RELOC_V850_16_SPLIT_OFFSET
4220 This is a 16-bit reloc.
4222 BFD_RELOC_V850_16_S1
4224 This is a 16-bit reloc.
4226 BFD_RELOC_V850_LO16_S1
4228 Low 16 bits. 16 bit shifted by 1.
4230 BFD_RELOC_V850_CALLT_15_16_OFFSET
4232 This is a 16 bit offset from the call table base pointer.
4234 BFD_RELOC_V850_32_GOTPCREL
4238 BFD_RELOC_V850_16_GOT
4242 BFD_RELOC_V850_32_GOT
4246 BFD_RELOC_V850_22_PLT_PCREL
4250 BFD_RELOC_V850_32_PLT_PCREL
4258 BFD_RELOC_V850_GLOB_DAT
4262 BFD_RELOC_V850_JMP_SLOT
4266 BFD_RELOC_V850_RELATIVE
4270 BFD_RELOC_V850_16_GOTOFF
4274 BFD_RELOC_V850_32_GOTOFF
4289 This is a 8bit DP reloc for the tms320c30, where the most
4290 significant 8 bits of a 24 bit word are placed into the least
4291 significant 8 bits of the opcode.
4294 BFD_RELOC_TIC54X_PARTLS7
4296 This is a 7bit reloc for the tms320c54x, where the least
4297 significant 7 bits of a 16 bit word are placed into the least
4298 significant 7 bits of the opcode.
4301 BFD_RELOC_TIC54X_PARTMS9
4303 This is a 9bit DP reloc for the tms320c54x, where the most
4304 significant 9 bits of a 16 bit word are placed into the least
4305 significant 9 bits of the opcode.
4310 This is an extended address 23-bit reloc for the tms320c54x.
4313 BFD_RELOC_TIC54X_16_OF_23
4315 This is a 16-bit reloc for the tms320c54x, where the least
4316 significant 16 bits of a 23-bit extended address are placed into
4320 BFD_RELOC_TIC54X_MS7_OF_23
4322 This is a reloc for the tms320c54x, where the most
4323 significant 7 bits of a 23-bit extended address are placed into
4327 BFD_RELOC_C6000_PCR_S21
4329 BFD_RELOC_C6000_PCR_S12
4331 BFD_RELOC_C6000_PCR_S10
4333 BFD_RELOC_C6000_PCR_S7
4335 BFD_RELOC_C6000_ABS_S16
4337 BFD_RELOC_C6000_ABS_L16
4339 BFD_RELOC_C6000_ABS_H16
4341 BFD_RELOC_C6000_SBR_U15_B
4343 BFD_RELOC_C6000_SBR_U15_H
4345 BFD_RELOC_C6000_SBR_U15_W
4347 BFD_RELOC_C6000_SBR_S16
4349 BFD_RELOC_C6000_SBR_L16_B
4351 BFD_RELOC_C6000_SBR_L16_H
4353 BFD_RELOC_C6000_SBR_L16_W
4355 BFD_RELOC_C6000_SBR_H16_B
4357 BFD_RELOC_C6000_SBR_H16_H
4359 BFD_RELOC_C6000_SBR_H16_W
4361 BFD_RELOC_C6000_SBR_GOT_U15_W
4363 BFD_RELOC_C6000_SBR_GOT_L16_W
4365 BFD_RELOC_C6000_SBR_GOT_H16_W
4367 BFD_RELOC_C6000_DSBT_INDEX
4369 BFD_RELOC_C6000_PREL31
4371 BFD_RELOC_C6000_COPY
4373 BFD_RELOC_C6000_JUMP_SLOT
4375 BFD_RELOC_C6000_EHTYPE
4377 BFD_RELOC_C6000_PCR_H16
4379 BFD_RELOC_C6000_PCR_L16
4381 BFD_RELOC_C6000_ALIGN
4383 BFD_RELOC_C6000_FPHEAD
4385 BFD_RELOC_C6000_NOCMP
4387 TMS320C6000 relocations.
4392 This is a 48 bit reloc for the FR30 that stores 32 bits.
4396 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4399 BFD_RELOC_FR30_6_IN_4
4401 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4404 BFD_RELOC_FR30_8_IN_8
4406 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4409 BFD_RELOC_FR30_9_IN_8
4411 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4414 BFD_RELOC_FR30_10_IN_8
4416 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4419 BFD_RELOC_FR30_9_PCREL
4421 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4422 short offset into 8 bits.
4424 BFD_RELOC_FR30_12_PCREL
4426 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4427 short offset into 11 bits.
4430 BFD_RELOC_MCORE_PCREL_IMM8BY4
4432 BFD_RELOC_MCORE_PCREL_IMM11BY2
4434 BFD_RELOC_MCORE_PCREL_IMM4BY2
4436 BFD_RELOC_MCORE_PCREL_32
4438 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4442 Motorola Mcore relocations.
4451 BFD_RELOC_MEP_PCREL8A2
4453 BFD_RELOC_MEP_PCREL12A2
4455 BFD_RELOC_MEP_PCREL17A2
4457 BFD_RELOC_MEP_PCREL24A2
4459 BFD_RELOC_MEP_PCABS24A2
4471 BFD_RELOC_MEP_TPREL7
4473 BFD_RELOC_MEP_TPREL7A2
4475 BFD_RELOC_MEP_TPREL7A4
4477 BFD_RELOC_MEP_UIMM24
4479 BFD_RELOC_MEP_ADDR24A4
4481 BFD_RELOC_MEP_GNU_VTINHERIT
4483 BFD_RELOC_MEP_GNU_VTENTRY
4485 Toshiba Media Processor Relocations.
4489 BFD_RELOC_METAG_HIADDR16
4491 BFD_RELOC_METAG_LOADDR16
4493 BFD_RELOC_METAG_RELBRANCH
4495 BFD_RELOC_METAG_GETSETOFF
4497 BFD_RELOC_METAG_HIOG
4499 BFD_RELOC_METAG_LOOG
4501 BFD_RELOC_METAG_REL8
4503 BFD_RELOC_METAG_REL16
4505 BFD_RELOC_METAG_HI16_GOTOFF
4507 BFD_RELOC_METAG_LO16_GOTOFF
4509 BFD_RELOC_METAG_GETSET_GOTOFF
4511 BFD_RELOC_METAG_GETSET_GOT
4513 BFD_RELOC_METAG_HI16_GOTPC
4515 BFD_RELOC_METAG_LO16_GOTPC
4517 BFD_RELOC_METAG_HI16_PLT
4519 BFD_RELOC_METAG_LO16_PLT
4521 BFD_RELOC_METAG_RELBRANCH_PLT
4523 BFD_RELOC_METAG_GOTOFF
4527 BFD_RELOC_METAG_COPY
4529 BFD_RELOC_METAG_JMP_SLOT
4531 BFD_RELOC_METAG_RELATIVE
4533 BFD_RELOC_METAG_GLOB_DAT
4535 BFD_RELOC_METAG_TLS_GD
4537 BFD_RELOC_METAG_TLS_LDM
4539 BFD_RELOC_METAG_TLS_LDO_HI16
4541 BFD_RELOC_METAG_TLS_LDO_LO16
4543 BFD_RELOC_METAG_TLS_LDO
4545 BFD_RELOC_METAG_TLS_IE
4547 BFD_RELOC_METAG_TLS_IENONPIC
4549 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4551 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4553 BFD_RELOC_METAG_TLS_TPOFF
4555 BFD_RELOC_METAG_TLS_DTPMOD
4557 BFD_RELOC_METAG_TLS_DTPOFF
4559 BFD_RELOC_METAG_TLS_LE
4561 BFD_RELOC_METAG_TLS_LE_HI16
4563 BFD_RELOC_METAG_TLS_LE_LO16
4565 Imagination Technologies Meta relocations.
4570 BFD_RELOC_MMIX_GETA_1
4572 BFD_RELOC_MMIX_GETA_2
4574 BFD_RELOC_MMIX_GETA_3
4576 These are relocations for the GETA instruction.
4578 BFD_RELOC_MMIX_CBRANCH
4580 BFD_RELOC_MMIX_CBRANCH_J
4582 BFD_RELOC_MMIX_CBRANCH_1
4584 BFD_RELOC_MMIX_CBRANCH_2
4586 BFD_RELOC_MMIX_CBRANCH_3
4588 These are relocations for a conditional branch instruction.
4590 BFD_RELOC_MMIX_PUSHJ
4592 BFD_RELOC_MMIX_PUSHJ_1
4594 BFD_RELOC_MMIX_PUSHJ_2
4596 BFD_RELOC_MMIX_PUSHJ_3
4598 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4600 These are relocations for the PUSHJ instruction.
4604 BFD_RELOC_MMIX_JMP_1
4606 BFD_RELOC_MMIX_JMP_2
4608 BFD_RELOC_MMIX_JMP_3
4610 These are relocations for the JMP instruction.
4612 BFD_RELOC_MMIX_ADDR19
4614 This is a relocation for a relative address as in a GETA instruction or
4617 BFD_RELOC_MMIX_ADDR27
4619 This is a relocation for a relative address as in a JMP instruction.
4621 BFD_RELOC_MMIX_REG_OR_BYTE
4623 This is a relocation for an instruction field that may be a general
4624 register or a value 0..255.
4628 This is a relocation for an instruction field that may be a general
4631 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4633 This is a relocation for two instruction fields holding a register and
4634 an offset, the equivalent of the relocation.
4636 BFD_RELOC_MMIX_LOCAL
4638 This relocation is an assertion that the expression is not allocated as
4639 a global register. It does not modify contents.
4642 BFD_RELOC_AVR_7_PCREL
4644 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4645 short offset into 7 bits.
4647 BFD_RELOC_AVR_13_PCREL
4649 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4650 short offset into 12 bits.
4654 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4655 program memory address) into 16 bits.
4657 BFD_RELOC_AVR_LO8_LDI
4659 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4660 data memory address) into 8 bit immediate value of LDI insn.
4662 BFD_RELOC_AVR_HI8_LDI
4664 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4665 of data memory address) into 8 bit immediate value of LDI insn.
4667 BFD_RELOC_AVR_HH8_LDI
4669 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4670 of program memory address) into 8 bit immediate value of LDI insn.
4672 BFD_RELOC_AVR_MS8_LDI
4674 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4675 of 32 bit value) into 8 bit immediate value of LDI insn.
4677 BFD_RELOC_AVR_LO8_LDI_NEG
4679 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4680 (usually data memory address) into 8 bit immediate value of SUBI insn.
4682 BFD_RELOC_AVR_HI8_LDI_NEG
4684 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4685 (high 8 bit of data memory address) into 8 bit immediate value of
4688 BFD_RELOC_AVR_HH8_LDI_NEG
4690 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4691 (most high 8 bit of program memory address) into 8 bit immediate value
4692 of LDI or SUBI insn.
4694 BFD_RELOC_AVR_MS8_LDI_NEG
4696 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4697 of 32 bit value) into 8 bit immediate value of LDI insn.
4699 BFD_RELOC_AVR_LO8_LDI_PM
4701 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4702 command address) into 8 bit immediate value of LDI insn.
4704 BFD_RELOC_AVR_LO8_LDI_GS
4706 This is a 16 bit reloc for the AVR that stores 8 bit value
4707 (command address) into 8 bit immediate value of LDI insn. If the address
4708 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4711 BFD_RELOC_AVR_HI8_LDI_PM
4713 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4714 of command address) into 8 bit immediate value of LDI insn.
4716 BFD_RELOC_AVR_HI8_LDI_GS
4718 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4719 of command address) into 8 bit immediate value of LDI insn. If the address
4720 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4723 BFD_RELOC_AVR_HH8_LDI_PM
4725 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4726 of command address) into 8 bit immediate value of LDI insn.
4728 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4730 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4731 (usually command address) into 8 bit immediate value of SUBI insn.
4733 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4735 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4736 (high 8 bit of 16 bit command address) into 8 bit immediate value
4739 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4741 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4742 (high 6 bit of 22 bit command address) into 8 bit immediate
4747 This is a 32 bit reloc for the AVR that stores 23 bit value
4752 This is a 16 bit reloc for the AVR that stores all needed bits
4753 for absolute addressing with ldi with overflow check to linktime
4757 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4760 BFD_RELOC_AVR_6_ADIW
4762 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4767 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4768 in .byte lo8(symbol)
4772 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4773 in .byte hi8(symbol)
4777 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4778 in .byte hlo8(symbol)
4782 BFD_RELOC_AVR_DIFF16
4784 BFD_RELOC_AVR_DIFF32
4786 AVR relocations to mark the difference of two local symbols.
4787 These are only needed to support linker relaxation and can be ignored
4788 when not relaxing. The field is set to the value of the difference
4789 assuming no relaxation. The relocation encodes the position of the
4790 second symbol so the linker can determine whether to adjust the field
4793 BFD_RELOC_AVR_LDS_STS_16
4795 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
4796 lds and sts instructions supported only tiny core.
4800 BFD_RELOC_RL78_NEG16
4802 BFD_RELOC_RL78_NEG24
4804 BFD_RELOC_RL78_NEG32
4806 BFD_RELOC_RL78_16_OP
4808 BFD_RELOC_RL78_24_OP
4810 BFD_RELOC_RL78_32_OP
4818 BFD_RELOC_RL78_DIR3U_PCREL
4822 BFD_RELOC_RL78_GPRELB
4824 BFD_RELOC_RL78_GPRELW
4826 BFD_RELOC_RL78_GPRELL
4830 BFD_RELOC_RL78_OP_SUBTRACT
4832 BFD_RELOC_RL78_OP_NEG
4834 BFD_RELOC_RL78_OP_AND
4836 BFD_RELOC_RL78_OP_SHRA
4840 BFD_RELOC_RL78_ABS16
4842 BFD_RELOC_RL78_ABS16_REV
4844 BFD_RELOC_RL78_ABS32
4846 BFD_RELOC_RL78_ABS32_REV
4848 BFD_RELOC_RL78_ABS16U
4850 BFD_RELOC_RL78_ABS16UW
4852 BFD_RELOC_RL78_ABS16UL
4854 BFD_RELOC_RL78_RELAX
4864 Renesas RL78 Relocations.
4887 BFD_RELOC_RX_DIR3U_PCREL
4899 BFD_RELOC_RX_OP_SUBTRACT
4907 BFD_RELOC_RX_ABS16_REV
4911 BFD_RELOC_RX_ABS32_REV
4915 BFD_RELOC_RX_ABS16UW
4917 BFD_RELOC_RX_ABS16UL
4921 Renesas RX Relocations.
4934 32 bit PC relative PLT address.
4938 Copy symbol at runtime.
4940 BFD_RELOC_390_GLOB_DAT
4944 BFD_RELOC_390_JMP_SLOT
4948 BFD_RELOC_390_RELATIVE
4950 Adjust by program base.
4954 32 bit PC relative offset to GOT.
4960 BFD_RELOC_390_PC12DBL
4962 PC relative 12 bit shifted by 1.
4964 BFD_RELOC_390_PLT12DBL
4966 12 bit PC rel. PLT shifted by 1.
4968 BFD_RELOC_390_PC16DBL
4970 PC relative 16 bit shifted by 1.
4972 BFD_RELOC_390_PLT16DBL
4974 16 bit PC rel. PLT shifted by 1.
4976 BFD_RELOC_390_PC24DBL
4978 PC relative 24 bit shifted by 1.
4980 BFD_RELOC_390_PLT24DBL
4982 24 bit PC rel. PLT shifted by 1.
4984 BFD_RELOC_390_PC32DBL
4986 PC relative 32 bit shifted by 1.
4988 BFD_RELOC_390_PLT32DBL
4990 32 bit PC rel. PLT shifted by 1.
4992 BFD_RELOC_390_GOTPCDBL
4994 32 bit PC rel. GOT shifted by 1.
5002 64 bit PC relative PLT address.
5004 BFD_RELOC_390_GOTENT
5006 32 bit rel. offset to GOT entry.
5008 BFD_RELOC_390_GOTOFF64
5010 64 bit offset to GOT.
5012 BFD_RELOC_390_GOTPLT12
5014 12-bit offset to symbol-entry within GOT, with PLT handling.
5016 BFD_RELOC_390_GOTPLT16
5018 16-bit offset to symbol-entry within GOT, with PLT handling.
5020 BFD_RELOC_390_GOTPLT32
5022 32-bit offset to symbol-entry within GOT, with PLT handling.
5024 BFD_RELOC_390_GOTPLT64
5026 64-bit offset to symbol-entry within GOT, with PLT handling.
5028 BFD_RELOC_390_GOTPLTENT
5030 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5032 BFD_RELOC_390_PLTOFF16
5034 16-bit rel. offset from the GOT to a PLT entry.
5036 BFD_RELOC_390_PLTOFF32
5038 32-bit rel. offset from the GOT to a PLT entry.
5040 BFD_RELOC_390_PLTOFF64
5042 64-bit rel. offset from the GOT to a PLT entry.
5045 BFD_RELOC_390_TLS_LOAD
5047 BFD_RELOC_390_TLS_GDCALL
5049 BFD_RELOC_390_TLS_LDCALL
5051 BFD_RELOC_390_TLS_GD32
5053 BFD_RELOC_390_TLS_GD64
5055 BFD_RELOC_390_TLS_GOTIE12
5057 BFD_RELOC_390_TLS_GOTIE32
5059 BFD_RELOC_390_TLS_GOTIE64
5061 BFD_RELOC_390_TLS_LDM32
5063 BFD_RELOC_390_TLS_LDM64
5065 BFD_RELOC_390_TLS_IE32
5067 BFD_RELOC_390_TLS_IE64
5069 BFD_RELOC_390_TLS_IEENT
5071 BFD_RELOC_390_TLS_LE32
5073 BFD_RELOC_390_TLS_LE64
5075 BFD_RELOC_390_TLS_LDO32
5077 BFD_RELOC_390_TLS_LDO64
5079 BFD_RELOC_390_TLS_DTPMOD
5081 BFD_RELOC_390_TLS_DTPOFF
5083 BFD_RELOC_390_TLS_TPOFF
5085 s390 tls relocations.
5092 BFD_RELOC_390_GOTPLT20
5094 BFD_RELOC_390_TLS_GOTIE20
5096 Long displacement extension.
5099 BFD_RELOC_390_IRELATIVE
5101 STT_GNU_IFUNC relocation.
5104 BFD_RELOC_SCORE_GPREL15
5107 Low 16 bit for load/store
5109 BFD_RELOC_SCORE_DUMMY2
5113 This is a 24-bit reloc with the right 1 bit assumed to be 0
5115 BFD_RELOC_SCORE_BRANCH
5117 This is a 19-bit reloc with the right 1 bit assumed to be 0
5119 BFD_RELOC_SCORE_IMM30
5121 This is a 32-bit reloc for 48-bit instructions.
5123 BFD_RELOC_SCORE_IMM32
5125 This is a 32-bit reloc for 48-bit instructions.
5127 BFD_RELOC_SCORE16_JMP
5129 This is a 11-bit reloc with the right 1 bit assumed to be 0
5131 BFD_RELOC_SCORE16_BRANCH
5133 This is a 8-bit reloc with the right 1 bit assumed to be 0
5135 BFD_RELOC_SCORE_BCMP
5137 This is a 9-bit reloc with the right 1 bit assumed to be 0
5139 BFD_RELOC_SCORE_GOT15
5141 BFD_RELOC_SCORE_GOT_LO16
5143 BFD_RELOC_SCORE_CALL15
5145 BFD_RELOC_SCORE_DUMMY_HI16
5147 Undocumented Score relocs
5152 Scenix IP2K - 9-bit register number / data address
5156 Scenix IP2K - 4-bit register/data bank number
5158 BFD_RELOC_IP2K_ADDR16CJP
5160 Scenix IP2K - low 13 bits of instruction word address
5162 BFD_RELOC_IP2K_PAGE3
5164 Scenix IP2K - high 3 bits of instruction word address
5166 BFD_RELOC_IP2K_LO8DATA
5168 BFD_RELOC_IP2K_HI8DATA
5170 BFD_RELOC_IP2K_EX8DATA
5172 Scenix IP2K - ext/low/high 8 bits of data address
5174 BFD_RELOC_IP2K_LO8INSN
5176 BFD_RELOC_IP2K_HI8INSN
5178 Scenix IP2K - low/high 8 bits of instruction word address
5180 BFD_RELOC_IP2K_PC_SKIP
5182 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5186 Scenix IP2K - 16 bit word address in text section.
5188 BFD_RELOC_IP2K_FR_OFFSET
5190 Scenix IP2K - 7-bit sp or dp offset
5192 BFD_RELOC_VPE4KMATH_DATA
5194 BFD_RELOC_VPE4KMATH_INSN
5196 Scenix VPE4K coprocessor - data/insn-space addressing
5199 BFD_RELOC_VTABLE_INHERIT
5201 BFD_RELOC_VTABLE_ENTRY
5203 These two relocations are used by the linker to determine which of
5204 the entries in a C++ virtual function table are actually used. When
5205 the --gc-sections option is given, the linker will zero out the entries
5206 that are not used, so that the code for those functions need not be
5207 included in the output.
5209 VTABLE_INHERIT is a zero-space relocation used to describe to the
5210 linker the inheritance tree of a C++ virtual function table. The
5211 relocation's symbol should be the parent class' vtable, and the
5212 relocation should be located at the child vtable.
5214 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5215 virtual function table entry. The reloc's symbol should refer to the
5216 table of the class mentioned in the code. Off of that base, an offset
5217 describes the entry that is being used. For Rela hosts, this offset
5218 is stored in the reloc's addend. For Rel hosts, we are forced to put
5219 this offset in the reloc's section offset.
5222 BFD_RELOC_IA64_IMM14
5224 BFD_RELOC_IA64_IMM22
5226 BFD_RELOC_IA64_IMM64
5228 BFD_RELOC_IA64_DIR32MSB
5230 BFD_RELOC_IA64_DIR32LSB
5232 BFD_RELOC_IA64_DIR64MSB
5234 BFD_RELOC_IA64_DIR64LSB
5236 BFD_RELOC_IA64_GPREL22
5238 BFD_RELOC_IA64_GPREL64I
5240 BFD_RELOC_IA64_GPREL32MSB
5242 BFD_RELOC_IA64_GPREL32LSB
5244 BFD_RELOC_IA64_GPREL64MSB
5246 BFD_RELOC_IA64_GPREL64LSB
5248 BFD_RELOC_IA64_LTOFF22
5250 BFD_RELOC_IA64_LTOFF64I
5252 BFD_RELOC_IA64_PLTOFF22
5254 BFD_RELOC_IA64_PLTOFF64I
5256 BFD_RELOC_IA64_PLTOFF64MSB
5258 BFD_RELOC_IA64_PLTOFF64LSB
5260 BFD_RELOC_IA64_FPTR64I
5262 BFD_RELOC_IA64_FPTR32MSB
5264 BFD_RELOC_IA64_FPTR32LSB
5266 BFD_RELOC_IA64_FPTR64MSB
5268 BFD_RELOC_IA64_FPTR64LSB
5270 BFD_RELOC_IA64_PCREL21B
5272 BFD_RELOC_IA64_PCREL21BI
5274 BFD_RELOC_IA64_PCREL21M
5276 BFD_RELOC_IA64_PCREL21F
5278 BFD_RELOC_IA64_PCREL22
5280 BFD_RELOC_IA64_PCREL60B
5282 BFD_RELOC_IA64_PCREL64I
5284 BFD_RELOC_IA64_PCREL32MSB
5286 BFD_RELOC_IA64_PCREL32LSB
5288 BFD_RELOC_IA64_PCREL64MSB
5290 BFD_RELOC_IA64_PCREL64LSB
5292 BFD_RELOC_IA64_LTOFF_FPTR22
5294 BFD_RELOC_IA64_LTOFF_FPTR64I
5296 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5298 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5300 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5302 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5304 BFD_RELOC_IA64_SEGREL32MSB
5306 BFD_RELOC_IA64_SEGREL32LSB
5308 BFD_RELOC_IA64_SEGREL64MSB
5310 BFD_RELOC_IA64_SEGREL64LSB
5312 BFD_RELOC_IA64_SECREL32MSB
5314 BFD_RELOC_IA64_SECREL32LSB
5316 BFD_RELOC_IA64_SECREL64MSB
5318 BFD_RELOC_IA64_SECREL64LSB
5320 BFD_RELOC_IA64_REL32MSB
5322 BFD_RELOC_IA64_REL32LSB
5324 BFD_RELOC_IA64_REL64MSB
5326 BFD_RELOC_IA64_REL64LSB
5328 BFD_RELOC_IA64_LTV32MSB
5330 BFD_RELOC_IA64_LTV32LSB
5332 BFD_RELOC_IA64_LTV64MSB
5334 BFD_RELOC_IA64_LTV64LSB
5336 BFD_RELOC_IA64_IPLTMSB
5338 BFD_RELOC_IA64_IPLTLSB
5342 BFD_RELOC_IA64_LTOFF22X
5344 BFD_RELOC_IA64_LDXMOV
5346 BFD_RELOC_IA64_TPREL14
5348 BFD_RELOC_IA64_TPREL22
5350 BFD_RELOC_IA64_TPREL64I
5352 BFD_RELOC_IA64_TPREL64MSB
5354 BFD_RELOC_IA64_TPREL64LSB
5356 BFD_RELOC_IA64_LTOFF_TPREL22
5358 BFD_RELOC_IA64_DTPMOD64MSB
5360 BFD_RELOC_IA64_DTPMOD64LSB
5362 BFD_RELOC_IA64_LTOFF_DTPMOD22
5364 BFD_RELOC_IA64_DTPREL14
5366 BFD_RELOC_IA64_DTPREL22
5368 BFD_RELOC_IA64_DTPREL64I
5370 BFD_RELOC_IA64_DTPREL32MSB
5372 BFD_RELOC_IA64_DTPREL32LSB
5374 BFD_RELOC_IA64_DTPREL64MSB
5376 BFD_RELOC_IA64_DTPREL64LSB
5378 BFD_RELOC_IA64_LTOFF_DTPREL22
5380 Intel IA64 Relocations.
5383 BFD_RELOC_M68HC11_HI8
5385 Motorola 68HC11 reloc.
5386 This is the 8 bit high part of an absolute address.
5388 BFD_RELOC_M68HC11_LO8
5390 Motorola 68HC11 reloc.
5391 This is the 8 bit low part of an absolute address.
5393 BFD_RELOC_M68HC11_3B
5395 Motorola 68HC11 reloc.
5396 This is the 3 bit of a value.
5398 BFD_RELOC_M68HC11_RL_JUMP
5400 Motorola 68HC11 reloc.
5401 This reloc marks the beginning of a jump/call instruction.
5402 It is used for linker relaxation to correctly identify beginning
5403 of instruction and change some branches to use PC-relative
5406 BFD_RELOC_M68HC11_RL_GROUP
5408 Motorola 68HC11 reloc.
5409 This reloc marks a group of several instructions that gcc generates
5410 and for which the linker relaxation pass can modify and/or remove
5413 BFD_RELOC_M68HC11_LO16
5415 Motorola 68HC11 reloc.
5416 This is the 16-bit lower part of an address. It is used for 'call'
5417 instruction to specify the symbol address without any special
5418 transformation (due to memory bank window).
5420 BFD_RELOC_M68HC11_PAGE
5422 Motorola 68HC11 reloc.
5423 This is a 8-bit reloc that specifies the page number of an address.
5424 It is used by 'call' instruction to specify the page number of
5427 BFD_RELOC_M68HC11_24
5429 Motorola 68HC11 reloc.
5430 This is a 24-bit reloc that represents the address with a 16-bit
5431 value and a 8-bit page number. The symbol address is transformed
5432 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5434 BFD_RELOC_M68HC12_5B
5436 Motorola 68HC12 reloc.
5437 This is the 5 bits of a value.
5439 BFD_RELOC_XGATE_RL_JUMP
5441 Freescale XGATE reloc.
5442 This reloc marks the beginning of a bra/jal instruction.
5444 BFD_RELOC_XGATE_RL_GROUP
5446 Freescale XGATE reloc.
5447 This reloc marks a group of several instructions that gcc generates
5448 and for which the linker relaxation pass can modify and/or remove
5451 BFD_RELOC_XGATE_LO16
5453 Freescale XGATE reloc.
5454 This is the 16-bit lower part of an address. It is used for the '16-bit'
5457 BFD_RELOC_XGATE_GPAGE
5459 Freescale XGATE reloc.
5463 Freescale XGATE reloc.
5465 BFD_RELOC_XGATE_PCREL_9
5467 Freescale XGATE reloc.
5468 This is a 9-bit pc-relative reloc.
5470 BFD_RELOC_XGATE_PCREL_10
5472 Freescale XGATE reloc.
5473 This is a 10-bit pc-relative reloc.
5475 BFD_RELOC_XGATE_IMM8_LO
5477 Freescale XGATE reloc.
5478 This is the 16-bit lower part of an address. It is used for the '16-bit'
5481 BFD_RELOC_XGATE_IMM8_HI
5483 Freescale XGATE reloc.
5484 This is the 16-bit higher part of an address. It is used for the '16-bit'
5487 BFD_RELOC_XGATE_IMM3
5489 Freescale XGATE reloc.
5490 This is a 3-bit pc-relative reloc.
5492 BFD_RELOC_XGATE_IMM4
5494 Freescale XGATE reloc.
5495 This is a 4-bit pc-relative reloc.
5497 BFD_RELOC_XGATE_IMM5
5499 Freescale XGATE reloc.
5500 This is a 5-bit pc-relative reloc.
5502 BFD_RELOC_M68HC12_9B
5504 Motorola 68HC12 reloc.
5505 This is the 9 bits of a value.
5507 BFD_RELOC_M68HC12_16B
5509 Motorola 68HC12 reloc.
5510 This is the 16 bits of a value.
5512 BFD_RELOC_M68HC12_9_PCREL
5514 Motorola 68HC12/XGATE reloc.
5515 This is a PCREL9 branch.
5517 BFD_RELOC_M68HC12_10_PCREL
5519 Motorola 68HC12/XGATE reloc.
5520 This is a PCREL10 branch.
5522 BFD_RELOC_M68HC12_LO8XG
5524 Motorola 68HC12/XGATE reloc.
5525 This is the 8 bit low part of an absolute address and immediately precedes
5526 a matching HI8XG part.
5528 BFD_RELOC_M68HC12_HI8XG
5530 Motorola 68HC12/XGATE reloc.
5531 This is the 8 bit high part of an absolute address and immediately follows
5532 a matching LO8XG part.
5536 BFD_RELOC_16C_NUM08_C
5540 BFD_RELOC_16C_NUM16_C
5544 BFD_RELOC_16C_NUM32_C
5546 BFD_RELOC_16C_DISP04
5548 BFD_RELOC_16C_DISP04_C
5550 BFD_RELOC_16C_DISP08
5552 BFD_RELOC_16C_DISP08_C
5554 BFD_RELOC_16C_DISP16
5556 BFD_RELOC_16C_DISP16_C
5558 BFD_RELOC_16C_DISP24
5560 BFD_RELOC_16C_DISP24_C
5562 BFD_RELOC_16C_DISP24a
5564 BFD_RELOC_16C_DISP24a_C
5568 BFD_RELOC_16C_REG04_C
5570 BFD_RELOC_16C_REG04a
5572 BFD_RELOC_16C_REG04a_C
5576 BFD_RELOC_16C_REG14_C
5580 BFD_RELOC_16C_REG16_C
5584 BFD_RELOC_16C_REG20_C
5588 BFD_RELOC_16C_ABS20_C
5592 BFD_RELOC_16C_ABS24_C
5596 BFD_RELOC_16C_IMM04_C
5600 BFD_RELOC_16C_IMM16_C
5604 BFD_RELOC_16C_IMM20_C
5608 BFD_RELOC_16C_IMM24_C
5612 BFD_RELOC_16C_IMM32_C
5614 NS CR16C Relocations.
5619 BFD_RELOC_CR16_NUM16
5621 BFD_RELOC_CR16_NUM32
5623 BFD_RELOC_CR16_NUM32a
5625 BFD_RELOC_CR16_REGREL0
5627 BFD_RELOC_CR16_REGREL4
5629 BFD_RELOC_CR16_REGREL4a
5631 BFD_RELOC_CR16_REGREL14
5633 BFD_RELOC_CR16_REGREL14a
5635 BFD_RELOC_CR16_REGREL16
5637 BFD_RELOC_CR16_REGREL20
5639 BFD_RELOC_CR16_REGREL20a
5641 BFD_RELOC_CR16_ABS20
5643 BFD_RELOC_CR16_ABS24
5649 BFD_RELOC_CR16_IMM16
5651 BFD_RELOC_CR16_IMM20
5653 BFD_RELOC_CR16_IMM24
5655 BFD_RELOC_CR16_IMM32
5657 BFD_RELOC_CR16_IMM32a
5659 BFD_RELOC_CR16_DISP4
5661 BFD_RELOC_CR16_DISP8
5663 BFD_RELOC_CR16_DISP16
5665 BFD_RELOC_CR16_DISP20
5667 BFD_RELOC_CR16_DISP24
5669 BFD_RELOC_CR16_DISP24a
5671 BFD_RELOC_CR16_SWITCH8
5673 BFD_RELOC_CR16_SWITCH16
5675 BFD_RELOC_CR16_SWITCH32
5677 BFD_RELOC_CR16_GOT_REGREL20
5679 BFD_RELOC_CR16_GOTC_REGREL20
5681 BFD_RELOC_CR16_GLOB_DAT
5683 NS CR16 Relocations.
5690 BFD_RELOC_CRX_REL8_CMP
5698 BFD_RELOC_CRX_REGREL12
5700 BFD_RELOC_CRX_REGREL22
5702 BFD_RELOC_CRX_REGREL28
5704 BFD_RELOC_CRX_REGREL32
5720 BFD_RELOC_CRX_SWITCH8
5722 BFD_RELOC_CRX_SWITCH16
5724 BFD_RELOC_CRX_SWITCH32
5729 BFD_RELOC_CRIS_BDISP8
5731 BFD_RELOC_CRIS_UNSIGNED_5
5733 BFD_RELOC_CRIS_SIGNED_6
5735 BFD_RELOC_CRIS_UNSIGNED_6
5737 BFD_RELOC_CRIS_SIGNED_8
5739 BFD_RELOC_CRIS_UNSIGNED_8
5741 BFD_RELOC_CRIS_SIGNED_16
5743 BFD_RELOC_CRIS_UNSIGNED_16
5745 BFD_RELOC_CRIS_LAPCQ_OFFSET
5747 BFD_RELOC_CRIS_UNSIGNED_4
5749 These relocs are only used within the CRIS assembler. They are not
5750 (at present) written to any object files.
5754 BFD_RELOC_CRIS_GLOB_DAT
5756 BFD_RELOC_CRIS_JUMP_SLOT
5758 BFD_RELOC_CRIS_RELATIVE
5760 Relocs used in ELF shared libraries for CRIS.
5762 BFD_RELOC_CRIS_32_GOT
5764 32-bit offset to symbol-entry within GOT.
5766 BFD_RELOC_CRIS_16_GOT
5768 16-bit offset to symbol-entry within GOT.
5770 BFD_RELOC_CRIS_32_GOTPLT
5772 32-bit offset to symbol-entry within GOT, with PLT handling.
5774 BFD_RELOC_CRIS_16_GOTPLT
5776 16-bit offset to symbol-entry within GOT, with PLT handling.
5778 BFD_RELOC_CRIS_32_GOTREL
5780 32-bit offset to symbol, relative to GOT.
5782 BFD_RELOC_CRIS_32_PLT_GOTREL
5784 32-bit offset to symbol with PLT entry, relative to GOT.
5786 BFD_RELOC_CRIS_32_PLT_PCREL
5788 32-bit offset to symbol with PLT entry, relative to this relocation.
5791 BFD_RELOC_CRIS_32_GOT_GD
5793 BFD_RELOC_CRIS_16_GOT_GD
5795 BFD_RELOC_CRIS_32_GD
5799 BFD_RELOC_CRIS_32_DTPREL
5801 BFD_RELOC_CRIS_16_DTPREL
5803 BFD_RELOC_CRIS_32_GOT_TPREL
5805 BFD_RELOC_CRIS_16_GOT_TPREL
5807 BFD_RELOC_CRIS_32_TPREL
5809 BFD_RELOC_CRIS_16_TPREL
5811 BFD_RELOC_CRIS_DTPMOD
5813 BFD_RELOC_CRIS_32_IE
5815 Relocs used in TLS code for CRIS.
5820 BFD_RELOC_860_GLOB_DAT
5822 BFD_RELOC_860_JUMP_SLOT
5824 BFD_RELOC_860_RELATIVE
5834 BFD_RELOC_860_SPLIT0
5838 BFD_RELOC_860_SPLIT1
5842 BFD_RELOC_860_SPLIT2
5846 BFD_RELOC_860_LOGOT0
5848 BFD_RELOC_860_SPGOT0
5850 BFD_RELOC_860_LOGOT1
5852 BFD_RELOC_860_SPGOT1
5854 BFD_RELOC_860_LOGOTOFF0
5856 BFD_RELOC_860_SPGOTOFF0
5858 BFD_RELOC_860_LOGOTOFF1
5860 BFD_RELOC_860_SPGOTOFF1
5862 BFD_RELOC_860_LOGOTOFF2
5864 BFD_RELOC_860_LOGOTOFF3
5868 BFD_RELOC_860_HIGHADJ
5872 BFD_RELOC_860_HAGOTOFF
5880 BFD_RELOC_860_HIGOTOFF
5882 Intel i860 Relocations.
5885 BFD_RELOC_OR1K_REL_26
5887 BFD_RELOC_OR1K_GOTPC_HI16
5889 BFD_RELOC_OR1K_GOTPC_LO16
5891 BFD_RELOC_OR1K_GOT16
5893 BFD_RELOC_OR1K_PLT26
5895 BFD_RELOC_OR1K_GOTOFF_HI16
5897 BFD_RELOC_OR1K_GOTOFF_LO16
5901 BFD_RELOC_OR1K_GLOB_DAT
5903 BFD_RELOC_OR1K_JMP_SLOT
5905 BFD_RELOC_OR1K_RELATIVE
5907 BFD_RELOC_OR1K_TLS_GD_HI16
5909 BFD_RELOC_OR1K_TLS_GD_LO16
5911 BFD_RELOC_OR1K_TLS_LDM_HI16
5913 BFD_RELOC_OR1K_TLS_LDM_LO16
5915 BFD_RELOC_OR1K_TLS_LDO_HI16
5917 BFD_RELOC_OR1K_TLS_LDO_LO16
5919 BFD_RELOC_OR1K_TLS_IE_HI16
5921 BFD_RELOC_OR1K_TLS_IE_LO16
5923 BFD_RELOC_OR1K_TLS_LE_HI16
5925 BFD_RELOC_OR1K_TLS_LE_LO16
5927 BFD_RELOC_OR1K_TLS_TPOFF
5929 BFD_RELOC_OR1K_TLS_DTPOFF
5931 BFD_RELOC_OR1K_TLS_DTPMOD
5933 OpenRISC 1000 Relocations.
5936 BFD_RELOC_H8_DIR16A8
5938 BFD_RELOC_H8_DIR16R8
5940 BFD_RELOC_H8_DIR24A8
5942 BFD_RELOC_H8_DIR24R8
5944 BFD_RELOC_H8_DIR32A16
5946 BFD_RELOC_H8_DISP32A16
5951 BFD_RELOC_XSTORMY16_REL_12
5953 BFD_RELOC_XSTORMY16_12
5955 BFD_RELOC_XSTORMY16_24
5957 BFD_RELOC_XSTORMY16_FPTR16
5959 Sony Xstormy16 Relocations.
5964 Self-describing complex relocations.
5976 Infineon Relocations.
5979 BFD_RELOC_VAX_GLOB_DAT
5981 BFD_RELOC_VAX_JMP_SLOT
5983 BFD_RELOC_VAX_RELATIVE
5985 Relocations used by VAX ELF.
5990 Morpho MT - 16 bit immediate relocation.
5994 Morpho MT - Hi 16 bits of an address.
5998 Morpho MT - Low 16 bits of an address.
6000 BFD_RELOC_MT_GNU_VTINHERIT
6002 Morpho MT - Used to tell the linker which vtable entries are used.
6004 BFD_RELOC_MT_GNU_VTENTRY
6006 Morpho MT - Used to tell the linker which vtable entries are used.
6008 BFD_RELOC_MT_PCINSN8
6010 Morpho MT - 8 bit immediate relocation.
6013 BFD_RELOC_MSP430_10_PCREL
6015 BFD_RELOC_MSP430_16_PCREL
6019 BFD_RELOC_MSP430_16_PCREL_BYTE
6021 BFD_RELOC_MSP430_16_BYTE
6023 BFD_RELOC_MSP430_2X_PCREL
6025 BFD_RELOC_MSP430_RL_PCREL
6027 BFD_RELOC_MSP430_ABS8
6029 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6031 BFD_RELOC_MSP430X_PCR20_EXT_DST
6033 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6035 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6037 BFD_RELOC_MSP430X_ABS20_EXT_DST
6039 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6041 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6043 BFD_RELOC_MSP430X_ABS20_ADR_DST
6045 BFD_RELOC_MSP430X_PCR16
6047 BFD_RELOC_MSP430X_PCR20_CALL
6049 BFD_RELOC_MSP430X_ABS16
6051 BFD_RELOC_MSP430_ABS_HI16
6053 BFD_RELOC_MSP430_PREL31
6055 BFD_RELOC_MSP430_SYM_DIFF
6057 msp430 specific relocation codes
6064 BFD_RELOC_NIOS2_CALL26
6066 BFD_RELOC_NIOS2_IMM5
6068 BFD_RELOC_NIOS2_CACHE_OPX
6070 BFD_RELOC_NIOS2_IMM6
6072 BFD_RELOC_NIOS2_IMM8
6074 BFD_RELOC_NIOS2_HI16
6076 BFD_RELOC_NIOS2_LO16
6078 BFD_RELOC_NIOS2_HIADJ16
6080 BFD_RELOC_NIOS2_GPREL
6082 BFD_RELOC_NIOS2_UJMP
6084 BFD_RELOC_NIOS2_CJMP
6086 BFD_RELOC_NIOS2_CALLR
6088 BFD_RELOC_NIOS2_ALIGN
6090 BFD_RELOC_NIOS2_GOT16
6092 BFD_RELOC_NIOS2_CALL16
6094 BFD_RELOC_NIOS2_GOTOFF_LO
6096 BFD_RELOC_NIOS2_GOTOFF_HA
6098 BFD_RELOC_NIOS2_PCREL_LO
6100 BFD_RELOC_NIOS2_PCREL_HA
6102 BFD_RELOC_NIOS2_TLS_GD16
6104 BFD_RELOC_NIOS2_TLS_LDM16
6106 BFD_RELOC_NIOS2_TLS_LDO16
6108 BFD_RELOC_NIOS2_TLS_IE16
6110 BFD_RELOC_NIOS2_TLS_LE16
6112 BFD_RELOC_NIOS2_TLS_DTPMOD
6114 BFD_RELOC_NIOS2_TLS_DTPREL
6116 BFD_RELOC_NIOS2_TLS_TPREL
6118 BFD_RELOC_NIOS2_COPY
6120 BFD_RELOC_NIOS2_GLOB_DAT
6122 BFD_RELOC_NIOS2_JUMP_SLOT
6124 BFD_RELOC_NIOS2_RELATIVE
6126 BFD_RELOC_NIOS2_GOTOFF
6128 BFD_RELOC_NIOS2_CALL26_NOAT
6130 BFD_RELOC_NIOS2_GOT_LO
6132 BFD_RELOC_NIOS2_GOT_HA
6134 BFD_RELOC_NIOS2_CALL_LO
6136 BFD_RELOC_NIOS2_CALL_HA
6138 Relocations used by the Altera Nios II core.
6141 BFD_RELOC_IQ2000_OFFSET_16
6143 BFD_RELOC_IQ2000_OFFSET_21
6145 BFD_RELOC_IQ2000_UHI16
6150 BFD_RELOC_XTENSA_RTLD
6152 Special Xtensa relocation used only by PLT entries in ELF shared
6153 objects to indicate that the runtime linker should set the value
6154 to one of its own internal functions or data structures.
6156 BFD_RELOC_XTENSA_GLOB_DAT
6158 BFD_RELOC_XTENSA_JMP_SLOT
6160 BFD_RELOC_XTENSA_RELATIVE
6162 Xtensa relocations for ELF shared objects.
6164 BFD_RELOC_XTENSA_PLT
6166 Xtensa relocation used in ELF object files for symbols that may require
6167 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6169 BFD_RELOC_XTENSA_DIFF8
6171 BFD_RELOC_XTENSA_DIFF16
6173 BFD_RELOC_XTENSA_DIFF32
6175 Xtensa relocations to mark the difference of two local symbols.
6176 These are only needed to support linker relaxation and can be ignored
6177 when not relaxing. The field is set to the value of the difference
6178 assuming no relaxation. The relocation encodes the position of the
6179 first symbol so the linker can determine whether to adjust the field
6182 BFD_RELOC_XTENSA_SLOT0_OP
6184 BFD_RELOC_XTENSA_SLOT1_OP
6186 BFD_RELOC_XTENSA_SLOT2_OP
6188 BFD_RELOC_XTENSA_SLOT3_OP
6190 BFD_RELOC_XTENSA_SLOT4_OP
6192 BFD_RELOC_XTENSA_SLOT5_OP
6194 BFD_RELOC_XTENSA_SLOT6_OP
6196 BFD_RELOC_XTENSA_SLOT7_OP
6198 BFD_RELOC_XTENSA_SLOT8_OP
6200 BFD_RELOC_XTENSA_SLOT9_OP
6202 BFD_RELOC_XTENSA_SLOT10_OP
6204 BFD_RELOC_XTENSA_SLOT11_OP
6206 BFD_RELOC_XTENSA_SLOT12_OP
6208 BFD_RELOC_XTENSA_SLOT13_OP
6210 BFD_RELOC_XTENSA_SLOT14_OP
6212 Generic Xtensa relocations for instruction operands. Only the slot
6213 number is encoded in the relocation. The relocation applies to the
6214 last PC-relative immediate operand, or if there are no PC-relative
6215 immediates, to the last immediate operand.
6217 BFD_RELOC_XTENSA_SLOT0_ALT
6219 BFD_RELOC_XTENSA_SLOT1_ALT
6221 BFD_RELOC_XTENSA_SLOT2_ALT
6223 BFD_RELOC_XTENSA_SLOT3_ALT
6225 BFD_RELOC_XTENSA_SLOT4_ALT
6227 BFD_RELOC_XTENSA_SLOT5_ALT
6229 BFD_RELOC_XTENSA_SLOT6_ALT
6231 BFD_RELOC_XTENSA_SLOT7_ALT
6233 BFD_RELOC_XTENSA_SLOT8_ALT
6235 BFD_RELOC_XTENSA_SLOT9_ALT
6237 BFD_RELOC_XTENSA_SLOT10_ALT
6239 BFD_RELOC_XTENSA_SLOT11_ALT
6241 BFD_RELOC_XTENSA_SLOT12_ALT
6243 BFD_RELOC_XTENSA_SLOT13_ALT
6245 BFD_RELOC_XTENSA_SLOT14_ALT
6247 Alternate Xtensa relocations. Only the slot is encoded in the
6248 relocation. The meaning of these relocations is opcode-specific.
6250 BFD_RELOC_XTENSA_OP0
6252 BFD_RELOC_XTENSA_OP1
6254 BFD_RELOC_XTENSA_OP2
6256 Xtensa relocations for backward compatibility. These have all been
6257 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6259 BFD_RELOC_XTENSA_ASM_EXPAND
6261 Xtensa relocation to mark that the assembler expanded the
6262 instructions from an original target. The expansion size is
6263 encoded in the reloc size.
6265 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6267 Xtensa relocation to mark that the linker should simplify
6268 assembler-expanded instructions. This is commonly used
6269 internally by the linker after analysis of a
6270 BFD_RELOC_XTENSA_ASM_EXPAND.
6272 BFD_RELOC_XTENSA_TLSDESC_FN
6274 BFD_RELOC_XTENSA_TLSDESC_ARG
6276 BFD_RELOC_XTENSA_TLS_DTPOFF
6278 BFD_RELOC_XTENSA_TLS_TPOFF
6280 BFD_RELOC_XTENSA_TLS_FUNC
6282 BFD_RELOC_XTENSA_TLS_ARG
6284 BFD_RELOC_XTENSA_TLS_CALL
6286 Xtensa TLS relocations.
6291 8 bit signed offset in (ix+d) or (iy+d).
6309 BFD_RELOC_LM32_BRANCH
6311 BFD_RELOC_LM32_16_GOT
6313 BFD_RELOC_LM32_GOTOFF_HI16
6315 BFD_RELOC_LM32_GOTOFF_LO16
6319 BFD_RELOC_LM32_GLOB_DAT
6321 BFD_RELOC_LM32_JMP_SLOT
6323 BFD_RELOC_LM32_RELATIVE
6325 Lattice Mico32 relocations.
6328 BFD_RELOC_MACH_O_SECTDIFF
6330 Difference between two section addreses. Must be followed by a
6331 BFD_RELOC_MACH_O_PAIR.
6333 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6335 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6337 BFD_RELOC_MACH_O_PAIR
6339 Pair of relocation. Contains the first symbol.
6342 BFD_RELOC_MACH_O_X86_64_BRANCH32
6344 BFD_RELOC_MACH_O_X86_64_BRANCH8
6346 PCREL relocations. They are marked as branch to create PLT entry if
6349 BFD_RELOC_MACH_O_X86_64_GOT
6351 Used when referencing a GOT entry.
6353 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6355 Used when loading a GOT entry with movq. It is specially marked so that
6356 the linker could optimize the movq to a leaq if possible.
6358 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR32
6360 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6362 BFD_RELOC_MACH_O_X86_64_SUBTRACTOR64
6364 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6366 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6368 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6370 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6372 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6374 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6376 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6379 BFD_RELOC_MICROBLAZE_32_LO
6381 This is a 32 bit reloc for the microblaze that stores the
6382 low 16 bits of a value
6384 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6386 This is a 32 bit pc-relative reloc for the microblaze that
6387 stores the low 16 bits of a value
6389 BFD_RELOC_MICROBLAZE_32_ROSDA
6391 This is a 32 bit reloc for the microblaze that stores a
6392 value relative to the read-only small data area anchor
6394 BFD_RELOC_MICROBLAZE_32_RWSDA
6396 This is a 32 bit reloc for the microblaze that stores a
6397 value relative to the read-write small data area anchor
6399 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6401 This is a 32 bit reloc for the microblaze to handle
6402 expressions of the form "Symbol Op Symbol"
6404 BFD_RELOC_MICROBLAZE_64_NONE
6406 This is a 64 bit reloc that stores the 32 bit pc relative
6407 value in two words (with an imm instruction). No relocation is
6408 done here - only used for relaxing
6410 BFD_RELOC_MICROBLAZE_64_GOTPC
6412 This is a 64 bit reloc that stores the 32 bit pc relative
6413 value in two words (with an imm instruction). The relocation is
6414 PC-relative GOT offset
6416 BFD_RELOC_MICROBLAZE_64_GOT
6418 This is a 64 bit reloc that stores the 32 bit pc relative
6419 value in two words (with an imm instruction). The relocation is
6422 BFD_RELOC_MICROBLAZE_64_PLT
6424 This is a 64 bit reloc that stores the 32 bit pc relative
6425 value in two words (with an imm instruction). The relocation is
6426 PC-relative offset into PLT
6428 BFD_RELOC_MICROBLAZE_64_GOTOFF
6430 This is a 64 bit reloc that stores the 32 bit GOT relative
6431 value in two words (with an imm instruction). The relocation is
6432 relative offset from _GLOBAL_OFFSET_TABLE_
6434 BFD_RELOC_MICROBLAZE_32_GOTOFF
6436 This is a 32 bit reloc that stores the 32 bit GOT relative
6437 value in a word. The relocation is relative offset from
6438 _GLOBAL_OFFSET_TABLE_
6440 BFD_RELOC_MICROBLAZE_COPY
6442 This is used to tell the dynamic linker to copy the value out of
6443 the dynamic object into the runtime process image.
6445 BFD_RELOC_MICROBLAZE_64_TLS
6449 BFD_RELOC_MICROBLAZE_64_TLSGD
6451 This is a 64 bit reloc that stores the 32 bit GOT relative value
6452 of the GOT TLS GD info entry in two words (with an imm instruction). The
6453 relocation is GOT offset.
6455 BFD_RELOC_MICROBLAZE_64_TLSLD
6457 This is a 64 bit reloc that stores the 32 bit GOT relative value
6458 of the GOT TLS LD info entry in two words (with an imm instruction). The
6459 relocation is GOT offset.
6461 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6463 This is a 32 bit reloc that stores the Module ID to GOT(n).
6465 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6467 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6469 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6471 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6474 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6476 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6477 to two words (uses imm instruction).
6479 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6481 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6482 to two words (uses imm instruction).
6485 BFD_RELOC_AARCH64_RELOC_START
6487 AArch64 pseudo relocation code to mark the start of the AArch64
6488 relocation enumerators. N.B. the order of the enumerators is
6489 important as several tables in the AArch64 bfd backend are indexed
6490 by these enumerators; make sure they are all synced.
6492 BFD_RELOC_AARCH64_NONE
6494 AArch64 null relocation code.
6496 BFD_RELOC_AARCH64_64
6498 BFD_RELOC_AARCH64_32
6500 BFD_RELOC_AARCH64_16
6502 Basic absolute relocations of N bits. These are equivalent to
6503 BFD_RELOC_N and they were added to assist the indexing of the howto
6506 BFD_RELOC_AARCH64_64_PCREL
6508 BFD_RELOC_AARCH64_32_PCREL
6510 BFD_RELOC_AARCH64_16_PCREL
6512 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
6513 and they were added to assist the indexing of the howto table.
6515 BFD_RELOC_AARCH64_MOVW_G0
6517 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
6518 of an unsigned address/value.
6520 BFD_RELOC_AARCH64_MOVW_G0_NC
6522 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
6523 an address/value. No overflow checking.
6525 BFD_RELOC_AARCH64_MOVW_G1
6527 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
6528 of an unsigned address/value.
6530 BFD_RELOC_AARCH64_MOVW_G1_NC
6532 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
6533 of an address/value. No overflow checking.
6535 BFD_RELOC_AARCH64_MOVW_G2
6537 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
6538 of an unsigned address/value.
6540 BFD_RELOC_AARCH64_MOVW_G2_NC
6542 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
6543 of an address/value. No overflow checking.
6545 BFD_RELOC_AARCH64_MOVW_G3
6547 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
6548 of a signed or unsigned address/value.
6550 BFD_RELOC_AARCH64_MOVW_G0_S
6552 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
6553 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6556 BFD_RELOC_AARCH64_MOVW_G1_S
6558 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
6559 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6562 BFD_RELOC_AARCH64_MOVW_G2_S
6564 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
6565 of a signed value. Changes instruction to MOVZ or MOVN depending on the
6568 BFD_RELOC_AARCH64_LD_LO19_PCREL
6570 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
6571 offset. The lowest two bits must be zero and are not stored in the
6572 instruction, giving a 21 bit signed byte offset.
6574 BFD_RELOC_AARCH64_ADR_LO21_PCREL
6576 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
6578 BFD_RELOC_AARCH64_ADR_HI21_PCREL
6580 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6581 offset, giving a 4KB aligned page base address.
6583 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
6585 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
6586 offset, giving a 4KB aligned page base address, but with no overflow
6589 BFD_RELOC_AARCH64_ADD_LO12
6591 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
6592 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6594 BFD_RELOC_AARCH64_LDST8_LO12
6596 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
6597 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6599 BFD_RELOC_AARCH64_TSTBR14
6601 AArch64 14 bit pc-relative test bit and branch.
6602 The lowest two bits must be zero and are not stored in the instruction,
6603 giving a 16 bit signed byte offset.
6605 BFD_RELOC_AARCH64_BRANCH19
6607 AArch64 19 bit pc-relative conditional branch and compare & branch.
6608 The lowest two bits must be zero and are not stored in the instruction,
6609 giving a 21 bit signed byte offset.
6611 BFD_RELOC_AARCH64_JUMP26
6613 AArch64 26 bit pc-relative unconditional branch.
6614 The lowest two bits must be zero and are not stored in the instruction,
6615 giving a 28 bit signed byte offset.
6617 BFD_RELOC_AARCH64_CALL26
6619 AArch64 26 bit pc-relative unconditional branch and link.
6620 The lowest two bits must be zero and are not stored in the instruction,
6621 giving a 28 bit signed byte offset.
6623 BFD_RELOC_AARCH64_LDST16_LO12
6625 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
6626 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6628 BFD_RELOC_AARCH64_LDST32_LO12
6630 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
6631 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6633 BFD_RELOC_AARCH64_LDST64_LO12
6635 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
6636 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6638 BFD_RELOC_AARCH64_LDST128_LO12
6640 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
6641 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6643 BFD_RELOC_AARCH64_GOT_LD_PREL19
6645 AArch64 Load Literal instruction, holding a 19 bit PC relative word
6646 offset of the global offset table entry for a symbol. The lowest two
6647 bits must be zero and are not stored in the instruction, giving a 21
6648 bit signed byte offset. This relocation type requires signed overflow
6651 BFD_RELOC_AARCH64_ADR_GOT_PAGE
6653 Get to the page base of the global offset table entry for a symbol as
6654 part of an ADRP instruction using a 21 bit PC relative value.Used in
6655 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
6657 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
6659 Unsigned 12 bit byte offset for 64 bit load/store from the page of
6660 the GOT entry for this symbol. Used in conjunction with
6661 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in LP64 ABI only.
6663 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
6665 Unsigned 12 bit byte offset for 32 bit load/store from the page of
6666 the GOT entry for this symbol. Used in conjunction with
6667 BFD_RELOC_AARCH64_ADR_GOTPAGE. Valid in ILP32 ABI only.
6669 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
6671 Get to the page base of the global offset table entry for a symbols
6672 tls_index structure as part of an adrp instruction using a 21 bit PC
6673 relative value. Used in conjunction with
6674 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
6676 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
6678 Unsigned 12 bit byte offset to global offset table entry for a symbols
6679 tls_index structure. Used in conjunction with
6680 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
6682 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
6684 AArch64 TLS INITIAL EXEC relocation.
6686 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
6688 AArch64 TLS INITIAL EXEC relocation.
6690 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
6692 AArch64 TLS INITIAL EXEC relocation.
6694 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
6696 AArch64 TLS INITIAL EXEC relocation.
6698 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
6700 AArch64 TLS INITIAL EXEC relocation.
6702 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
6704 AArch64 TLS INITIAL EXEC relocation.
6706 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
6708 AArch64 TLS LOCAL EXEC relocation.
6710 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
6712 AArch64 TLS LOCAL EXEC relocation.
6714 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
6716 AArch64 TLS LOCAL EXEC relocation.
6718 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
6720 AArch64 TLS LOCAL EXEC relocation.
6722 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
6724 AArch64 TLS LOCAL EXEC relocation.
6726 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
6728 AArch64 TLS LOCAL EXEC relocation.
6730 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
6732 AArch64 TLS LOCAL EXEC relocation.
6734 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
6736 AArch64 TLS LOCAL EXEC relocation.
6738 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
6740 AArch64 TLS DESC relocation.
6742 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
6744 AArch64 TLS DESC relocation.
6746 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
6748 AArch64 TLS DESC relocation.
6750 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12_NC
6752 AArch64 TLS DESC relocation.
6754 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
6756 AArch64 TLS DESC relocation.
6758 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12_NC
6760 AArch64 TLS DESC relocation.
6762 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
6764 AArch64 TLS DESC relocation.
6766 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
6768 AArch64 TLS DESC relocation.
6770 BFD_RELOC_AARCH64_TLSDESC_LDR
6772 AArch64 TLS DESC relocation.
6774 BFD_RELOC_AARCH64_TLSDESC_ADD
6776 AArch64 TLS DESC relocation.
6778 BFD_RELOC_AARCH64_TLSDESC_CALL
6780 AArch64 TLS DESC relocation.
6782 BFD_RELOC_AARCH64_COPY
6784 AArch64 TLS relocation.
6786 BFD_RELOC_AARCH64_GLOB_DAT
6788 AArch64 TLS relocation.
6790 BFD_RELOC_AARCH64_JUMP_SLOT
6792 AArch64 TLS relocation.
6794 BFD_RELOC_AARCH64_RELATIVE
6796 AArch64 TLS relocation.
6798 BFD_RELOC_AARCH64_TLS_DTPMOD
6800 AArch64 TLS relocation.
6802 BFD_RELOC_AARCH64_TLS_DTPREL
6804 AArch64 TLS relocation.
6806 BFD_RELOC_AARCH64_TLS_TPREL
6808 AArch64 TLS relocation.
6810 BFD_RELOC_AARCH64_TLSDESC
6812 AArch64 TLS relocation.
6814 BFD_RELOC_AARCH64_IRELATIVE
6816 AArch64 support for STT_GNU_IFUNC.
6818 BFD_RELOC_AARCH64_RELOC_END
6820 AArch64 pseudo relocation code to mark the end of the AArch64
6821 relocation enumerators that have direct mapping to ELF reloc codes.
6822 There are a few more enumerators after this one; those are mainly
6823 used by the AArch64 assembler for the internal fixup or to select
6824 one of the above enumerators.
6826 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
6828 AArch64 pseudo relocation code to be used internally by the AArch64
6829 assembler and not (currently) written to any object files.
6831 BFD_RELOC_AARCH64_LDST_LO12
6833 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
6834 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
6836 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
6838 AArch64 pseudo relocation code to be used internally by the AArch64
6839 assembler and not (currently) written to any object files.
6841 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
6843 AArch64 pseudo relocation code to be used internally by the AArch64
6844 assembler and not (currently) written to any object files.
6846 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
6848 AArch64 pseudo relocation code to be used internally by the AArch64
6849 assembler and not (currently) written to any object files.
6852 BFD_RELOC_TILEPRO_COPY
6854 BFD_RELOC_TILEPRO_GLOB_DAT
6856 BFD_RELOC_TILEPRO_JMP_SLOT
6858 BFD_RELOC_TILEPRO_RELATIVE
6860 BFD_RELOC_TILEPRO_BROFF_X1
6862 BFD_RELOC_TILEPRO_JOFFLONG_X1
6864 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
6866 BFD_RELOC_TILEPRO_IMM8_X0
6868 BFD_RELOC_TILEPRO_IMM8_Y0
6870 BFD_RELOC_TILEPRO_IMM8_X1
6872 BFD_RELOC_TILEPRO_IMM8_Y1
6874 BFD_RELOC_TILEPRO_DEST_IMM8_X1
6876 BFD_RELOC_TILEPRO_MT_IMM15_X1
6878 BFD_RELOC_TILEPRO_MF_IMM15_X1
6880 BFD_RELOC_TILEPRO_IMM16_X0
6882 BFD_RELOC_TILEPRO_IMM16_X1
6884 BFD_RELOC_TILEPRO_IMM16_X0_LO
6886 BFD_RELOC_TILEPRO_IMM16_X1_LO
6888 BFD_RELOC_TILEPRO_IMM16_X0_HI
6890 BFD_RELOC_TILEPRO_IMM16_X1_HI
6892 BFD_RELOC_TILEPRO_IMM16_X0_HA
6894 BFD_RELOC_TILEPRO_IMM16_X1_HA
6896 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
6898 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
6900 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
6902 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
6904 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
6906 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
6908 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
6910 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
6912 BFD_RELOC_TILEPRO_IMM16_X0_GOT
6914 BFD_RELOC_TILEPRO_IMM16_X1_GOT
6916 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
6918 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
6920 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
6922 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
6924 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
6926 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
6928 BFD_RELOC_TILEPRO_MMSTART_X0
6930 BFD_RELOC_TILEPRO_MMEND_X0
6932 BFD_RELOC_TILEPRO_MMSTART_X1
6934 BFD_RELOC_TILEPRO_MMEND_X1
6936 BFD_RELOC_TILEPRO_SHAMT_X0
6938 BFD_RELOC_TILEPRO_SHAMT_X1
6940 BFD_RELOC_TILEPRO_SHAMT_Y0
6942 BFD_RELOC_TILEPRO_SHAMT_Y1
6944 BFD_RELOC_TILEPRO_TLS_GD_CALL
6946 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
6948 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
6950 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
6952 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
6954 BFD_RELOC_TILEPRO_TLS_IE_LOAD
6956 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
6958 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
6960 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
6962 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
6964 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
6966 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
6968 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
6970 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
6972 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
6974 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
6976 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
6978 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
6980 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
6982 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
6984 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
6986 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
6988 BFD_RELOC_TILEPRO_TLS_DTPMOD32
6990 BFD_RELOC_TILEPRO_TLS_DTPOFF32
6992 BFD_RELOC_TILEPRO_TLS_TPOFF32
6994 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
6996 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
6998 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7000 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7002 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7004 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7006 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7008 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7010 Tilera TILEPro Relocations.
7012 BFD_RELOC_TILEGX_HW0
7014 BFD_RELOC_TILEGX_HW1
7016 BFD_RELOC_TILEGX_HW2
7018 BFD_RELOC_TILEGX_HW3
7020 BFD_RELOC_TILEGX_HW0_LAST
7022 BFD_RELOC_TILEGX_HW1_LAST
7024 BFD_RELOC_TILEGX_HW2_LAST
7026 BFD_RELOC_TILEGX_COPY
7028 BFD_RELOC_TILEGX_GLOB_DAT
7030 BFD_RELOC_TILEGX_JMP_SLOT
7032 BFD_RELOC_TILEGX_RELATIVE
7034 BFD_RELOC_TILEGX_BROFF_X1
7036 BFD_RELOC_TILEGX_JUMPOFF_X1
7038 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7040 BFD_RELOC_TILEGX_IMM8_X0
7042 BFD_RELOC_TILEGX_IMM8_Y0
7044 BFD_RELOC_TILEGX_IMM8_X1
7046 BFD_RELOC_TILEGX_IMM8_Y1
7048 BFD_RELOC_TILEGX_DEST_IMM8_X1
7050 BFD_RELOC_TILEGX_MT_IMM14_X1
7052 BFD_RELOC_TILEGX_MF_IMM14_X1
7054 BFD_RELOC_TILEGX_MMSTART_X0
7056 BFD_RELOC_TILEGX_MMEND_X0
7058 BFD_RELOC_TILEGX_SHAMT_X0
7060 BFD_RELOC_TILEGX_SHAMT_X1
7062 BFD_RELOC_TILEGX_SHAMT_Y0
7064 BFD_RELOC_TILEGX_SHAMT_Y1
7066 BFD_RELOC_TILEGX_IMM16_X0_HW0
7068 BFD_RELOC_TILEGX_IMM16_X1_HW0
7070 BFD_RELOC_TILEGX_IMM16_X0_HW1
7072 BFD_RELOC_TILEGX_IMM16_X1_HW1
7074 BFD_RELOC_TILEGX_IMM16_X0_HW2
7076 BFD_RELOC_TILEGX_IMM16_X1_HW2
7078 BFD_RELOC_TILEGX_IMM16_X0_HW3
7080 BFD_RELOC_TILEGX_IMM16_X1_HW3
7082 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7084 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7086 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7088 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7090 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7092 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7094 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7096 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7098 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7100 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7102 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7104 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7106 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7108 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7110 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7112 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7114 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7116 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7118 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7120 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7122 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7124 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7126 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7128 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7130 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7132 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7134 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7136 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7138 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7140 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7142 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7144 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7146 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7148 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7150 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7152 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7154 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7156 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7158 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7160 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7162 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7164 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7166 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7168 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7170 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7172 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7174 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7176 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7178 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7180 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7182 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7184 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7186 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7188 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7190 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7192 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7194 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7196 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7198 BFD_RELOC_TILEGX_TLS_DTPMOD64
7200 BFD_RELOC_TILEGX_TLS_DTPOFF64
7202 BFD_RELOC_TILEGX_TLS_TPOFF64
7204 BFD_RELOC_TILEGX_TLS_DTPMOD32
7206 BFD_RELOC_TILEGX_TLS_DTPOFF32
7208 BFD_RELOC_TILEGX_TLS_TPOFF32
7210 BFD_RELOC_TILEGX_TLS_GD_CALL
7212 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7214 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7216 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7218 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7220 BFD_RELOC_TILEGX_TLS_IE_LOAD
7222 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7224 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7226 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7228 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7230 Tilera TILE-Gx Relocations.
7232 BFD_RELOC_EPIPHANY_SIMM8
7234 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7236 BFD_RELOC_EPIPHANY_SIMM24
7238 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7240 BFD_RELOC_EPIPHANY_HIGH
7242 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7244 BFD_RELOC_EPIPHANY_LOW
7246 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7248 BFD_RELOC_EPIPHANY_SIMM11
7250 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7252 BFD_RELOC_EPIPHANY_IMM11
7254 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7256 BFD_RELOC_EPIPHANY_IMM8
7258 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7265 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
7270 bfd_reloc_type_lookup
7271 bfd_reloc_name_lookup
7274 reloc_howto_type *bfd_reloc_type_lookup
7275 (bfd *abfd, bfd_reloc_code_real_type code);
7276 reloc_howto_type *bfd_reloc_name_lookup
7277 (bfd *abfd, const char *reloc_name);
7280 Return a pointer to a howto structure which, when
7281 invoked, will perform the relocation @var{code} on data from the
7287 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7289 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
7293 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
7295 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
7298 static reloc_howto_type bfd_howto_32
=
7299 HOWTO (0, 00, 2, 32, FALSE
, 0, complain_overflow_dont
, 0, "VRT32", FALSE
, 0xffffffff, 0xffffffff, TRUE
);
7303 bfd_default_reloc_type_lookup
7306 reloc_howto_type *bfd_default_reloc_type_lookup
7307 (bfd *abfd, bfd_reloc_code_real_type code);
7310 Provides a default relocation lookup routine for any architecture.
7315 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
7319 case BFD_RELOC_CTOR
:
7320 /* The type of reloc used in a ctor, which will be as wide as the
7321 address - so either a 64, 32, or 16 bitter. */
7322 switch (bfd_arch_bits_per_address (abfd
))
7327 return &bfd_howto_32
;
7341 bfd_get_reloc_code_name
7344 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
7347 Provides a printable name for the supplied relocation code.
7348 Useful mainly for printing error messages.
7352 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
7354 if (code
> BFD_RELOC_UNUSED
)
7356 return bfd_reloc_code_real_names
[code
];
7361 bfd_generic_relax_section
7364 bfd_boolean bfd_generic_relax_section
7367 struct bfd_link_info *,
7371 Provides default handling for relaxing for back ends which
7376 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
7377 asection
*section ATTRIBUTE_UNUSED
,
7378 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
7381 if (link_info
->relocatable
)
7382 (*link_info
->callbacks
->einfo
)
7383 (_("%P%F: --relax and -r may not be used together\n"));
7391 bfd_generic_gc_sections
7394 bfd_boolean bfd_generic_gc_sections
7395 (bfd *, struct bfd_link_info *);
7398 Provides default handling for relaxing for back ends which
7399 don't do section gc -- i.e., does nothing.
7403 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
7404 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
7411 bfd_generic_lookup_section_flags
7414 bfd_boolean bfd_generic_lookup_section_flags
7415 (struct bfd_link_info *, struct flag_info *, asection *);
7418 Provides default handling for section flags lookup
7419 -- i.e., does nothing.
7420 Returns FALSE if the section should be omitted, otherwise TRUE.
7424 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
7425 struct flag_info
*flaginfo
,
7426 asection
*section ATTRIBUTE_UNUSED
)
7428 if (flaginfo
!= NULL
)
7430 (*_bfd_error_handler
) (_("INPUT_SECTION_FLAGS are not supported.\n"));
7438 bfd_generic_merge_sections
7441 bfd_boolean bfd_generic_merge_sections
7442 (bfd *, struct bfd_link_info *);
7445 Provides default handling for SEC_MERGE section merging for back ends
7446 which don't have SEC_MERGE support -- i.e., does nothing.
7450 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
7451 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
7458 bfd_generic_get_relocated_section_contents
7461 bfd_byte *bfd_generic_get_relocated_section_contents
7463 struct bfd_link_info *link_info,
7464 struct bfd_link_order *link_order,
7466 bfd_boolean relocatable,
7470 Provides default handling of relocation effort for back ends
7471 which can't be bothered to do it efficiently.
7476 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
7477 struct bfd_link_info
*link_info
,
7478 struct bfd_link_order
*link_order
,
7480 bfd_boolean relocatable
,
7483 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
7484 asection
*input_section
= link_order
->u
.indirect
.section
;
7486 arelent
**reloc_vector
;
7489 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
7493 /* Read in the section. */
7494 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
7497 if (reloc_size
== 0)
7500 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
7501 if (reloc_vector
== NULL
)
7504 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
7508 if (reloc_count
< 0)
7511 if (reloc_count
> 0)
7514 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
7516 char *error_message
= NULL
;
7518 bfd_reloc_status_type r
;
7520 symbol
= *(*parent
)->sym_ptr_ptr
;
7521 if (symbol
->section
&& discarded_section (symbol
->section
))
7524 static reloc_howto_type none_howto
7525 = HOWTO (0, 0, 0, 0, FALSE
, 0, complain_overflow_dont
, NULL
,
7526 "unused", FALSE
, 0, 0, FALSE
);
7528 p
= data
+ (*parent
)->address
* bfd_octets_per_byte (input_bfd
);
7529 _bfd_clear_contents ((*parent
)->howto
, input_bfd
, input_section
,
7531 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
7532 (*parent
)->addend
= 0;
7533 (*parent
)->howto
= &none_howto
;
7537 r
= bfd_perform_relocation (input_bfd
,
7541 relocatable
? abfd
: NULL
,
7546 asection
*os
= input_section
->output_section
;
7548 /* A partial link, so keep the relocs. */
7549 os
->orelocation
[os
->reloc_count
] = *parent
;
7553 if (r
!= bfd_reloc_ok
)
7557 case bfd_reloc_undefined
:
7558 if (!((*link_info
->callbacks
->undefined_symbol
)
7559 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
7560 input_bfd
, input_section
, (*parent
)->address
,
7564 case bfd_reloc_dangerous
:
7565 BFD_ASSERT (error_message
!= NULL
);
7566 if (!((*link_info
->callbacks
->reloc_dangerous
)
7567 (link_info
, error_message
, input_bfd
, input_section
,
7568 (*parent
)->address
)))
7571 case bfd_reloc_overflow
:
7572 if (!((*link_info
->callbacks
->reloc_overflow
)
7574 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
7575 (*parent
)->howto
->name
, (*parent
)->addend
,
7576 input_bfd
, input_section
, (*parent
)->address
)))
7579 case bfd_reloc_outofrange
:
7581 This error can result when processing some partially
7582 complete binaries. Do not abort, but issue an error
7584 link_info
->callbacks
->einfo
7585 (_("%X%P: %B(%A): relocation \"%R\" goes out of range\n"),
7586 abfd
, input_section
, * parent
);
7598 free (reloc_vector
);
7602 free (reloc_vector
);