binutils/sparc-pinsn.c

   1 /* disassemble sparc instructions for objdump
   2    Copyright (C) 1986, 1987, 1989, 1991 Free Software Foundation, Inc.
   3
   4
   5 This file is part of the binutils.
   6
   7 The binutils are free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 The binutils are distributed in the hope that they will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License
  18 along with the binutils; see the file COPYING.  If not, write to
  19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.  */
  20
  21 #include "bfd.h"
  22 #include "sysdep.h"
  23 #include <stdio.h>
  24 #include "opcode/sparc.h"
  25 #include "objdump.h"
  26 extern int print_address();
  27
  28 static  char *reg_names[] =
  29  { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
  30   "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
  31   "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
  32   "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
  33   "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
  34   "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
  35   "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
  36   "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
  37   "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" };
  38
  39 #define freg_names      (&reg_names[4 * 8])
  40
  41 union sparc_insn
  42   {
  43     unsigned long int code;
  44     struct
  45       {
  46         unsigned int _OP:2;
  47 #define op      ldst._OP
  48         unsigned int _RD:5;
  49 #define rd      ldst._RD
  50         unsigned int op3:6;
  51         unsigned int _RS1:5;
  52 #define rs1     ldst._RS1
  53         unsigned int i:1;
  54         unsigned int _ASI:8;
  55 #define asi     ldst._ASI
  56         unsigned int _RS2:5;
  57 #define rs2     ldst._RS2
  58 #define shcnt   rs2
  59       } ldst;
  60     struct
  61       {
  62         unsigned int _OP:2, _RD:5, op3:6, _RS1:5, i:1;
  63         unsigned int IMM13:13;
  64 #define imm13   IMM13.IMM13
  65       } IMM13;
  66     struct
  67       {
  68         unsigned int _OP:2;
  69         unsigned int a:1;
  70         unsigned int cond:4;
  71         unsigned int op2:3;
  72         unsigned int DISP22:22;
  73 #define disp22  branch.DISP22
  74       } branch;
  75 #ifndef NO_V9
  76     struct
  77       {
  78         unsigned int _OP:2, _RD:5, op3:6, _RS1:5;
  79         unsigned int DISP14:14;
  80 #define disp14  DISP14.DISP14
  81       } DISP14;
  82     struct
  83       {
  84         unsigned int _OP:2;
  85         unsigned int a:1;
  86         unsigned int cond:4;
  87         unsigned int op2:3;
  88         unsigned int p:1;
  89         unsigned int DISP21:21;
  90 #define disp21  branch2.DISP21
  91       } branch2;
  92 #endif /* NO_V9 */
  93
  94 #define imm22   disp22
  95     struct
  96       {
  97         unsigned int _OP:2;
  98         unsigned int _DISP30:30;
  99 #define disp30  call._DISP30
 100       } call;
 101   };
 102
 103 /* Nonzero if INSN is the opcode for a delayed branch.  */
 104 static int
 105 is_delayed_branch (insn)
 106      union sparc_insn insn;
 107 {
 108   unsigned int i;
 109
 110   for (i = 0; i < NUMOPCODES; ++i)
 111     {
 112       const struct sparc_opcode *opcode = &sparc_opcodes[i];
 113       if ((opcode->match & insn.code) == opcode->match
 114           && (opcode->lose & insn.code) == 0
 115           && (opcode->flags&F_DELAYED))
 116         return 1;
 117     }
 118   return 0;
 119 }
 120
 121 static int opcodes_sorted = 0;
 122
 123 /* Print one instruction from MEMADDR on STREAM.  */
 124 int
 125 print_insn_sparc (memaddr, buffer,  stream)
 126      bfd_vma memaddr;
 127     bfd_byte  *buffer;
 128      FILE *stream;
 129
 130 {
 131   union sparc_insn insn;
 132
 133   register unsigned int i;
 134
 135   if (!opcodes_sorted)
 136     {
 137       static int compare_opcodes ();
 138       qsort ((char *) sparc_opcodes, NUMOPCODES,
 139              sizeof (sparc_opcodes[0]), compare_opcodes);
 140       opcodes_sorted = 1;
 141     }
 142
 143 memcpy(&insn,buffer, sizeof (insn));
 144
 145   for (i = 0; i < NUMOPCODES; ++i)
 146     {
 147       const struct sparc_opcode *opcode = &sparc_opcodes[i];
 148       if ((opcode->match & insn.code) == opcode->match
 149           && (opcode->lose & insn.code) == 0)
 150         {
 151           /* Nonzero means that we have found an instruction which has
 152              the effect of adding or or'ing the imm13 field to rs1.  */
 153           int imm_added_to_rs1 = 0;
 154
 155           /* Nonzero means that we have found a plus sign in the args
 156              field of the opcode table.  */
 157           int found_plus = 0;
 158
 159           /* Do we have an 'or' instruction where rs1 is the same
 160              as rsd, and which has the i bit set?  */
 161           if (opcode->match == 0x80102000
 162               && insn.rs1 == insn.rd)
 163             imm_added_to_rs1 = 1;
 164
 165           if (index (opcode->args, 'S') != 0)
 166             /* Reject the special case for `set'.
 167                The real `sethi' will match.  */
 168             continue;
 169           if (insn.rs1 != insn.rd
 170               && index (opcode->args, 'r') != 0)
 171               /* Can't do simple format if source and dest are different.  */
 172               continue;
 173
 174           fputs (opcode->name, stream);
 175
 176           {
 177             register const char *s;
 178
 179             if (opcode->args[0] != ',')
 180               fputs (" ", stream);
 181             for (s = opcode->args; *s != '\0'; ++s)
 182               {
 183                 while (*s == ',')
 184                   {
 185                     fputs (",", stream);
 186                     ++s;
 187
 188                     switch (*s) {
 189                     case 'a':
 190                       fputs ("a", stream);
 191                       ++s;
 192                       continue;
 193 #ifndef NO_V9
 194                     case 'N':
 195                       fputs("pn", stream);
 196                       ++s;
 197                       continue;
 198
 199                     case 'T':
 200                       fputs("pt", stream);
 201                       ++s;
 202                       continue;
 203 #endif                          /* NO_V9 */
 204
 205                     default:
 206                       break;
 207                     }           /* switch on arg */
 208                   }             /* while there are comma started args */
 209
 210                 fputs (" ", stream);
 211
 212                 switch (*s)
 213                   {
 214                   case '+':
 215                     found_plus = 1;
 216
 217                     /* note fall-through */
 218                   default:
 219                     fprintf (stream, "%c", *s);
 220                     break;
 221
 222                   case '#':
 223                     fputs ("0", stream);
 224                     break;
 225
 226 #define reg(n)  fprintf (stream, "%%%s", reg_names[n])
 227                   case '1':
 228                   case 'r':
 229                     reg (insn.rs1);
 230                     break;
 231
 232                   case '2':
 233                     reg (insn.rs2);
 234                     break;
 235
 236                   case 'd':
 237                     reg (insn.rd);
 238                     break;
 239 #undef  reg
 240
 241 #define freg(n) fprintf (stream, "%%%s", freg_names[n])
 242                   case 'e':
 243                   case 'v':     /* double/even */
 244                   case 'V':     /* quad/multiple of 4 */
 245                     freg (insn.rs1);
 246                     break;
 247
 248                   case 'f':
 249                   case 'B':     /* double/even */
 250                   case 'R':     /* quad/multiple of 4 */
 251                     freg (insn.rs2);
 252                     break;
 253
 254 #ifndef NO_V9
 255 /* Somebody who know needs to define rs3.
 256                   case 'j':
 257                   case 'u':     * double/even *
 258                   case 'U':     * quad/multiple of 4 *
 259                     freg (insn.rs3);
 260                     break;
 261 */
 262 #endif                          /* NO_V9 */
 263
 264                   case 'g':
 265                   case 'H':     /* double/even */
 266                   case 'J':     /* quad/multiple of 4 */
 267                     freg (insn.rd);
 268                     break;
 269 #undef  freg
 270
 271 #define creg(n) fprintf (stream, "%%c%u", (unsigned int) (n))
 272                   case 'b':
 273                     creg (insn.rs1);
 274                     break;
 275
 276                   case 'c':
 277                     creg (insn.rs2);
 278                     break;
 279
 280                   case 'D':
 281                     creg (insn.rd);
 282                     break;
 283 #undef  creg
 284
 285                   case 'h':
 286                     fprintf (stream, "%%hi(%#x)",
 287                              (unsigned int) insn.imm22 << 10);
 288                     break;
 289
 290                   case 'i':
 291                     {
 292                       /* We cannot trust the compiler to sign-extend
 293                          when extracting the bitfield, hence the shifts.  */
 294                       int imm = ((int) insn.imm13 << 19) >> 19;
 295
 296                       /* Check to see whether we have a 1+i, and take
 297                          note of that fact.
 298
 299                          Note: because of the way we sort the table,
 300                          we will be matching 1+i rather than i+1,
 301                          so it is OK to assume that i is after +,
 302                          not before it.  */
 303                       if (found_plus)
 304                         imm_added_to_rs1 = 1;
 305
 306                       if (imm <= 9)
 307                         fprintf (stream, "%d", imm);
 308                       else
 309                         fprintf (stream, "%#x", (unsigned) imm);
 310                     }
 311                     break;
 312
 313 #ifndef NO_V9
 314                   case 'k':
 315                     print_address ((bfd_vma)
 316                                    (memaddr
 317                                     + (((int) insn.disp14 << 18) >> 18) * 4),
 318                                    stream);
 319                     break;
 320
 321                   case 'G':
 322                     print_address ((bfd_vma)
 323                                    (memaddr
 324                                     /* We use only 19 of the 21 bits.  */
 325                                     + (((int) insn.disp21 << 13) >> 13) * 4),
 326                                    stream);
 327                     break;
 328
 329                   case 'Y':
 330                     fputs ("%amr", stream);
 331                     break;
 332
 333                   case '6':
 334                   case '7':
 335                   case '8':
 336                   case '9':
 337                     fprintf (stream, "fcc%c", *s - '6' + '0');
 338                     break;
 339
 340                   case 'z':
 341                     fputs ("icc", stream);
 342                     break;
 343
 344                   case 'Z':
 345                     fputs ("xcc", stream);
 346                     break;
 347 #endif                          /* NO_V9 */
 348
 349                   case 'M':
 350                     fprintf(stream, "%%asr%d", insn.rs1);
 351                     break;
 352
 353                   case 'm':
 354                     fprintf(stream, "%%asr%d", insn.rd);
 355                     break;
 356
 357                   case 'L':
 358                     print_address ((bfd_vma) memaddr + insn.disp30 * 4,
 359                                    stream);
 360                     break;
 361
 362                   case 'l':
 363                     if ((insn.code >> 22) == 0)
 364                       /* Special case for `unimp'.  Don't try to turn
 365                          it's operand into a function offset.  */
 366                       fprintf (stream, "%#x",
 367                                (unsigned) (((int) insn.disp22 << 10) >> 10));
 368                     else
 369                       /* We cannot trust the compiler to sign-extend
 370                          when extracting the bitfield, hence the shifts.  */
 371                       print_address ((bfd_vma)
 372                                      (memaddr
 373                                       + (((int) insn.disp22 << 10) >> 10) * 4),
 374                                      stream);
 375                     break;
 376
 377                   case 'A':
 378                     fprintf (stream, "(%d)", (int) insn.asi);
 379                     break;
 380
 381                   case 'C':
 382                     fputs ("%csr", stream);
 383                     break;
 384
 385                   case 'F':
 386                     fputs ("%fsr", stream);
 387                     break;
 388
 389                   case 'p':
 390                     fputs ("%psr", stream);
 391                     break;
 392
 393                   case 'q':
 394                     fputs ("%fq", stream);
 395                     break;
 396
 397                   case 'Q':
 398                     fputs ("%cq", stream);
 399                     break;
 400
 401                   case 't':
 402                     fputs ("%tbr", stream);
 403                     break;
 404
 405                   case 'w':
 406                     fputs ("%wim", stream);
 407                     break;
 408
 409                   case 'y':
 410                     fputs ("%y", stream);
 411                     break;
 412                   }
 413               }
 414           }
 415
 416           /* If we are adding or or'ing something to rs1, then
 417              check to see whether the previous instruction was
 418              a sethi to the same register as in the sethi.
 419              If so, attempt to print the result of the add or
 420              or (in this context add and or do the same thing)
 421              and its symbolic value.  */
 422           if (imm_added_to_rs1)
 423             {
 424               union sparc_insn prev_insn;
 425               int errcode = 0;
 426
 427               memcpy(&prev_insn, buffer -4,  sizeof (prev_insn));
 428
 429               if (errcode == 0)
 430                 {
 431                   /* If it is a delayed branch, we need to look at the
 432                      instruction before the delayed branch.  This handles
 433                      sequences such as
 434
 435                      sethi %o1, %hi(_foo), %o1
 436                      call _printf
 437                      or %o1, %lo(_foo), %o1
 438                      */
 439
 440                   if (is_delayed_branch (prev_insn))
 441                     memcpy(&prev_insn, buffer - 8, sizeof(prev_insn));
 442
 443                 }
 444
 445               /* If there was a problem reading memory, then assume
 446                  the previous instruction was not sethi.  */
 447               if (errcode == 0)
 448                 {
 449                   /* Is it sethi to the same register?  */
 450                   if ((prev_insn.code & 0xc1c00000) == 0x01000000
 451                       && prev_insn.rd == insn.rs1)
 452                     {
 453                       fprintf (stream, "\t! ");
 454                       /* We cannot trust the compiler to sign-extend
 455                          when extracting the bitfield, hence the shifts.  */
 456                       print_address (((int) prev_insn.imm22 << 10)
 457                                      | (insn.imm13 << 19) >> 19, stream);
 458                     }
 459                 }
 460             }
 461
 462           return sizeof (insn);
 463         }
 464     }
 465
 466   fprintf (stream, "%#8x", insn.code);
 467   return sizeof (insn);
 468 }
 469
 470
 471 /* Compare opcodes A and B.  */
 472
 473 static int
 474 compare_opcodes (a, b)
 475      char *a, *b;
 476 {
 477   struct sparc_opcode *op0 = (struct sparc_opcode *) a;
 478   struct sparc_opcode *op1 = (struct sparc_opcode *) b;
 479   unsigned long int match0 = op0->match, match1 = op1->match;
 480   unsigned long int lose0 = op0->lose, lose1 = op1->lose;
 481   register unsigned int i;
 482
 483   /* If a bit is set in both match and lose, there is something
 484      wrong with the opcode table.  */
 485   if (match0 & lose0)
 486     {
 487       fprintf (stderr, "Internal error:  bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
 488                op0->name, match0, lose0);
 489       op0->lose &= ~op0->match;
 490       lose0 = op0->lose;
 491     }
 492
 493   if (match1 & lose1)
 494     {
 495       fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
 496                op1->name, match1, lose1);
 497       op1->lose &= ~op1->match;
 498       lose1 = op1->lose;
 499     }
 500
 501   /* Because the bits that are variable in one opcode are constant in
 502      another, it is important to order the opcodes in the right order.  */
 503   for (i = 0; i < 32; ++i)
 504     {
 505       unsigned long int x = 1 << i;
 506       int x0 = (match0 & x) != 0;
 507       int x1 = (match1 & x) != 0;
 508
 509       if (x0 != x1)
 510         return x1 - x0;
 511     }
 512
 513   for (i = 0; i < 32; ++i)
 514     {
 515       unsigned long int x = 1 << i;
 516       int x0 = (lose0 & x) != 0;
 517       int x1 = (lose1 & x) != 0;
 518
 519       if (x0 != x1)
 520         return x1 - x0;
 521     }
 522
 523   /* They are functionally equal.  So as long as the opcode table is
 524      valid, we can put whichever one first we want, on aesthetic grounds.  */
 525   {
 526     int length_diff = strlen (op0->args) - strlen (op1->args);
 527     if (length_diff != 0)
 528       /* Put the one with fewer arguments first.  */
 529       return length_diff;
 530   }
 531
 532   /* Put 1+i before i+1.  */
 533   {
 534     char *p0 = (char *) index(op0->args, '+');
 535     char *p1 = (char *) index(op1->args, '+');
 536
 537     if (p0 && p1)
 538       {
 539         /* There is a plus in both operands.  Note that a plus
 540            sign cannot be the first character in args,
 541            so the following [-1]'s are valid.  */
 542         if (p0[-1] == 'i' && p1[1] == 'i')
 543           /* op0 is i+1 and op1 is 1+i, so op1 goes first.  */
 544           return 1;
 545         if (p0[1] == 'i' && p1[-1] == 'i')
 546           /* op0 is 1+i and op1 is i+1, so op0 goes first.  */
 547           return -1;
 548       }
 549   }
 550
 551   /* They are, as far as we can tell, identical.
 552      Since qsort may have rearranged the table partially, there is
 553      no way to tell which one was first in the opcode table as
 554      written, so just say there are equal.  */
 555   return 0;
 556 }