* Makefile.in: Bump version to 1.96, and remove -beta
[binutils-gdb.git] / binutils / sparc-pinsn.c
1 /* disassemble sparc instructions for objdump
2 Copyright (C) 1986, 1987, 1989, 1991 Free Software Foundation, Inc.
3
4
5 This file is part of the binutils.
6
7 The binutils are free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
10 any later version.
11
12 The binutils are distributed in the hope that they will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with the binutils; see the file COPYING. If not, write to
19 the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
20
21 /* $Id$ */
22
23 #include "bfd.h"
24 #include "sysdep.h"
25 #include <stdio.h>
26 #include "opcode/sparc.h"
27 #include "objdump.h"
28 extern int print_address();
29
30 static char *reg_names[] =
31 { "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
32 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
33 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
34 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
35 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
36 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
37 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
38 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
39 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr" };
40
41 #define freg_names (&reg_names[4 * 8])
42
43 union sparc_insn
44 {
45 unsigned long int code;
46 struct
47 {
48 unsigned int _OP:2;
49 #define op ldst._OP
50 unsigned int _RD:5;
51 #define rd ldst._RD
52 unsigned int op3:6;
53 unsigned int _RS1:5;
54 #define rs1 ldst._RS1
55 unsigned int i:1;
56 unsigned int _ASI:8;
57 #define asi ldst._ASI
58 unsigned int _RS2:5;
59 #define rs2 ldst._RS2
60 #define shcnt rs2
61 } ldst;
62 struct
63 {
64 unsigned int _OP:2, _RD:5, op3:6, _RS1:5, i:1;
65 unsigned int IMM13:13;
66 #define imm13 IMM13.IMM13
67 } IMM13;
68 struct
69 {
70 unsigned int _OP:2;
71 unsigned int a:1;
72 unsigned int cond:4;
73 unsigned int op2:3;
74 unsigned int DISP22:22;
75 #define disp22 branch.DISP22
76 } branch;
77 #ifndef NO_V9
78 struct
79 {
80 unsigned int _OP:2, _RD:5, op3:6, _RS1:5;
81 unsigned int DISP14:14;
82 #define disp14 DISP14.DISP14
83 } DISP14;
84 struct
85 {
86 unsigned int _OP:2;
87 unsigned int a:1;
88 unsigned int cond:4;
89 unsigned int op2:3;
90 unsigned int p:1;
91 unsigned int DISP21:21;
92 #define disp21 branch2.DISP21
93 } branch2;
94 #endif /* NO_V9 */
95
96 #define imm22 disp22
97 struct
98 {
99 unsigned int _OP:2;
100 unsigned int _DISP30:30;
101 #define disp30 call._DISP30
102 } call;
103 };
104
105 /* Nonzero if INSN is the opcode for a delayed branch. */
106 static int
107 is_delayed_branch (insn)
108 union sparc_insn insn;
109 {
110 unsigned int i;
111
112 for (i = 0; i < NUMOPCODES; ++i)
113 {
114 const struct sparc_opcode *opcode = &sparc_opcodes[i];
115 if ((opcode->match & insn.code) == opcode->match
116 && (opcode->lose & insn.code) == 0
117 && (opcode->flags&F_DELAYED))
118 return 1;
119 }
120 return 0;
121 }
122
123 static int opcodes_sorted = 0;
124
125 /* Print one instruction from MEMADDR on STREAM. */
126 int
127 print_insn_sparc (memaddr, buffer, stream)
128 bfd_vma memaddr;
129 bfd_byte *buffer;
130 FILE *stream;
131
132 {
133 union sparc_insn insn;
134
135 register unsigned int i;
136
137 if (!opcodes_sorted)
138 {
139 static int compare_opcodes ();
140 qsort ((char *) sparc_opcodes, NUMOPCODES,
141 sizeof (sparc_opcodes[0]), compare_opcodes);
142 opcodes_sorted = 1;
143 }
144
145 memcpy(&insn,buffer, sizeof (insn));
146
147 for (i = 0; i < NUMOPCODES; ++i)
148 {
149 const struct sparc_opcode *opcode = &sparc_opcodes[i];
150 if ((opcode->match & insn.code) == opcode->match
151 && (opcode->lose & insn.code) == 0)
152 {
153 /* Nonzero means that we have found an instruction which has
154 the effect of adding or or'ing the imm13 field to rs1. */
155 int imm_added_to_rs1 = 0;
156
157 /* Nonzero means that we have found a plus sign in the args
158 field of the opcode table. */
159 int found_plus = 0;
160
161 /* Do we have an 'or' instruction where rs1 is the same
162 as rsd, and which has the i bit set? */
163 if (opcode->match == 0x80102000
164 && insn.rs1 == insn.rd)
165 imm_added_to_rs1 = 1;
166
167 if (index (opcode->args, 'S') != 0)
168 /* Reject the special case for `set'.
169 The real `sethi' will match. */
170 continue;
171 if (insn.rs1 != insn.rd
172 && index (opcode->args, 'r') != 0)
173 /* Can't do simple format if source and dest are different. */
174 continue;
175
176 fputs (opcode->name, stream);
177
178 {
179 register const char *s;
180
181 if (opcode->args[0] != ',')
182 fputs (" ", stream);
183 for (s = opcode->args; *s != '\0'; ++s)
184 {
185 while (*s == ',')
186 {
187 fputs (",", stream);
188 ++s;
189
190 switch (*s) {
191 case 'a':
192 fputs ("a", stream);
193 ++s;
194 continue;
195 #ifndef NO_V9
196 case 'N':
197 fputs("pn", stream);
198 ++s;
199 continue;
200
201 case 'T':
202 fputs("pt", stream);
203 ++s;
204 continue;
205 #endif /* NO_V9 */
206
207 default:
208 break;
209 } /* switch on arg */
210 } /* while there are comma started args */
211
212 fputs (" ", stream);
213
214 switch (*s)
215 {
216 case '+':
217 found_plus = 1;
218
219 /* note fall-through */
220 default:
221 fprintf (stream, "%c", *s);
222 break;
223
224 case '#':
225 fputs ("0", stream);
226 break;
227
228 #define reg(n) fprintf (stream, "%%%s", reg_names[n])
229 case '1':
230 case 'r':
231 reg (insn.rs1);
232 break;
233
234 case '2':
235 reg (insn.rs2);
236 break;
237
238 case 'd':
239 reg (insn.rd);
240 break;
241 #undef reg
242
243 #define freg(n) fprintf (stream, "%%%s", freg_names[n])
244 case 'e':
245 case 'v': /* double/even */
246 case 'V': /* quad/multiple of 4 */
247 freg (insn.rs1);
248 break;
249
250 case 'f':
251 case 'B': /* double/even */
252 case 'R': /* quad/multiple of 4 */
253 freg (insn.rs2);
254 break;
255
256 #ifndef NO_V9
257 #if 0
258 /* Somebody who know needs to define rs3. */
259 case 'j':
260 case 'u': /* double/even */
261 case 'U': /* quad/multiple of 4 */
262 freg (insn.rs3);
263 break;
264 #endif
265 #endif /* NO_V9 */
266
267 case 'g':
268 case 'H': /* double/even */
269 case 'J': /* quad/multiple of 4 */
270 freg (insn.rd);
271 break;
272 #undef freg
273
274 #define creg(n) fprintf (stream, "%%c%u", (unsigned int) (n))
275 case 'b':
276 creg (insn.rs1);
277 break;
278
279 case 'c':
280 creg (insn.rs2);
281 break;
282
283 case 'D':
284 creg (insn.rd);
285 break;
286 #undef creg
287
288 case 'h':
289 fprintf (stream, "%%hi(%#x)",
290 (unsigned int) insn.imm22 << 10);
291 break;
292
293 case 'i':
294 {
295 /* We cannot trust the compiler to sign-extend
296 when extracting the bitfield, hence the shifts. */
297 int imm = ((int) insn.imm13 << 19) >> 19;
298
299 /* Check to see whether we have a 1+i, and take
300 note of that fact.
301
302 Note: because of the way we sort the table,
303 we will be matching 1+i rather than i+1,
304 so it is OK to assume that i is after +,
305 not before it. */
306 if (found_plus)
307 imm_added_to_rs1 = 1;
308
309 if (imm <= 9)
310 fprintf (stream, "%d", imm);
311 else
312 fprintf (stream, "%#x", (unsigned) imm);
313 }
314 break;
315
316 #ifndef NO_V9
317 case 'k':
318 print_address ((bfd_vma)
319 (memaddr
320 + (((int) insn.disp14 << 18) >> 18) * 4),
321 stream);
322 break;
323
324 case 'G':
325 print_address ((bfd_vma)
326 (memaddr
327 /* We use only 19 of the 21 bits. */
328 + (((int) insn.disp21 << 13) >> 13) * 4),
329 stream);
330 break;
331
332 case 'Y':
333 fputs ("%amr", stream);
334 break;
335
336 case '6':
337 case '7':
338 case '8':
339 case '9':
340 fprintf (stream, "fcc%c", *s - '6' + '0');
341 break;
342
343 case 'z':
344 fputs ("icc", stream);
345 break;
346
347 case 'Z':
348 fputs ("xcc", stream);
349 break;
350 #endif /* NO_V9 */
351
352 case 'M':
353 fprintf(stream, "%%asr%d", insn.rs1);
354 break;
355
356 case 'm':
357 fprintf(stream, "%%asr%d", insn.rd);
358 break;
359
360 case 'L':
361 print_address ((bfd_vma) memaddr + insn.disp30 * 4,
362 stream);
363 break;
364
365 case 'l':
366 if ((insn.code >> 22) == 0)
367 /* Special case for `unimp'. Don't try to turn
368 it's operand into a function offset. */
369 fprintf (stream, "%#x",
370 (unsigned) (((int) insn.disp22 << 10) >> 10));
371 else
372 /* We cannot trust the compiler to sign-extend
373 when extracting the bitfield, hence the shifts. */
374 print_address ((bfd_vma)
375 (memaddr
376 + (((int) insn.disp22 << 10) >> 10) * 4),
377 stream);
378 break;
379
380 case 'A':
381 fprintf (stream, "(%d)", (int) insn.asi);
382 break;
383
384 case 'C':
385 fputs ("%csr", stream);
386 break;
387
388 case 'F':
389 fputs ("%fsr", stream);
390 break;
391
392 case 'p':
393 fputs ("%psr", stream);
394 break;
395
396 case 'q':
397 fputs ("%fq", stream);
398 break;
399
400 case 'Q':
401 fputs ("%cq", stream);
402 break;
403
404 case 't':
405 fputs ("%tbr", stream);
406 break;
407
408 case 'w':
409 fputs ("%wim", stream);
410 break;
411
412 case 'y':
413 fputs ("%y", stream);
414 break;
415 }
416 }
417 }
418
419 /* If we are adding or or'ing something to rs1, then
420 check to see whether the previous instruction was
421 a sethi to the same register as in the sethi.
422 If so, attempt to print the result of the add or
423 or (in this context add and or do the same thing)
424 and its symbolic value. */
425 if (imm_added_to_rs1)
426 {
427 union sparc_insn prev_insn;
428 int errcode = 0;
429
430 memcpy(&prev_insn, buffer -4, sizeof (prev_insn));
431
432 if (errcode == 0)
433 {
434 /* If it is a delayed branch, we need to look at the
435 instruction before the delayed branch. This handles
436 sequences such as
437
438 sethi %o1, %hi(_foo), %o1
439 call _printf
440 or %o1, %lo(_foo), %o1
441 */
442
443 if (is_delayed_branch (prev_insn))
444 memcpy(&prev_insn, buffer - 8, sizeof(prev_insn));
445
446 }
447
448 /* If there was a problem reading memory, then assume
449 the previous instruction was not sethi. */
450 if (errcode == 0)
451 {
452 /* Is it sethi to the same register? */
453 if ((prev_insn.code & 0xc1c00000) == 0x01000000
454 && prev_insn.rd == insn.rs1)
455 {
456 fprintf (stream, "\t! ");
457 /* We cannot trust the compiler to sign-extend
458 when extracting the bitfield, hence the shifts. */
459 print_address (((int) prev_insn.imm22 << 10)
460 | (insn.imm13 << 19) >> 19, stream);
461 }
462 }
463 }
464
465 return sizeof (insn);
466 }
467 }
468
469 fprintf (stream, "%#8x", insn.code);
470 return sizeof (insn);
471 }
472
473
474 /* Compare opcodes A and B. */
475
476 static int
477 compare_opcodes (a, b)
478 char *a, *b;
479 {
480 struct sparc_opcode *op0 = (struct sparc_opcode *) a;
481 struct sparc_opcode *op1 = (struct sparc_opcode *) b;
482 unsigned long int match0 = op0->match, match1 = op1->match;
483 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
484 register unsigned int i;
485
486 /* If a bit is set in both match and lose, there is something
487 wrong with the opcode table. */
488 if (match0 & lose0)
489 {
490 fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
491 op0->name, match0, lose0);
492 op0->lose &= ~op0->match;
493 lose0 = op0->lose;
494 }
495
496 if (match1 & lose1)
497 {
498 fprintf (stderr, "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n",
499 op1->name, match1, lose1);
500 op1->lose &= ~op1->match;
501 lose1 = op1->lose;
502 }
503
504 /* Because the bits that are variable in one opcode are constant in
505 another, it is important to order the opcodes in the right order. */
506 for (i = 0; i < 32; ++i)
507 {
508 unsigned long int x = 1 << i;
509 int x0 = (match0 & x) != 0;
510 int x1 = (match1 & x) != 0;
511
512 if (x0 != x1)
513 return x1 - x0;
514 }
515
516 for (i = 0; i < 32; ++i)
517 {
518 unsigned long int x = 1 << i;
519 int x0 = (lose0 & x) != 0;
520 int x1 = (lose1 & x) != 0;
521
522 if (x0 != x1)
523 return x1 - x0;
524 }
525
526 /* They are functionally equal. So as long as the opcode table is
527 valid, we can put whichever one first we want, on aesthetic grounds. */
528 {
529 int length_diff = strlen (op0->args) - strlen (op1->args);
530 if (length_diff != 0)
531 /* Put the one with fewer arguments first. */
532 return length_diff;
533 }
534
535 /* Put 1+i before i+1. */
536 {
537 char *p0 = (char *) index(op0->args, '+');
538 char *p1 = (char *) index(op1->args, '+');
539
540 if (p0 && p1)
541 {
542 /* There is a plus in both operands. Note that a plus
543 sign cannot be the first character in args,
544 so the following [-1]'s are valid. */
545 if (p0[-1] == 'i' && p1[1] == 'i')
546 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
547 return 1;
548 if (p0[1] == 'i' && p1[-1] == 'i')
549 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
550 return -1;
551 }
552 }
553
554 /* They are, as far as we can tell, identical.
555 Since qsort may have rearranged the table partially, there is
556 no way to tell which one was first in the opcode table as
557 written, so just say there are equal. */
558 return 0;
559 }