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ba29d90907f2a09143387313dc367d4f7062f938
[yosys.git] / blif.cc
1 /*
2 * yosys -- Yosys Open SYnthesis Suite
3 *
4 * Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 */
19
20 // [[CITE]] Berkeley Logic Interchange Format (BLIF)
21 // University of California. Berkeley. July 28, 1992
22 // http://www.ece.cmu.edu/~ee760/760docs/blif.pdf
23
24 #include "kernel/rtlil.h"
25 #include "kernel/register.h"
26 #include "kernel/sigtools.h"
27 #include "kernel/celltypes.h"
28 #include "kernel/log.h"
29 #include <string>
30
31 USING_YOSYS_NAMESPACE
32 PRIVATE_NAMESPACE_BEGIN
33
34 struct BlifDumperConfig
35 {
36 bool icells_mode;
37 bool conn_mode;
38 bool impltf_mode;
39 bool gates_mode;
40 bool cname_mode;
41 bool iname_mode;
42 bool param_mode;
43 bool attr_mode;
44 bool iattr_mode;
45 bool blackbox_mode;
46 bool noalias_mode;
47
48 std::string buf_type, buf_in, buf_out;
49 std::map<RTLIL::IdString, std::pair<RTLIL::IdString, RTLIL::IdString>> unbuf_types;
50 std::string true_type, true_out, false_type, false_out, undef_type, undef_out;
51
52 BlifDumperConfig() : icells_mode(false), conn_mode(false), impltf_mode(false), gates_mode(false),
53 cname_mode(false), iname_mode(false), param_mode(false), attr_mode(false), iattr_mode(false),
54 blackbox_mode(false), noalias_mode(false) { }
55 };
56
57 struct BlifDumper
58 {
59 std::ostream &f;
60 RTLIL::Module *module;
61 RTLIL::Design *design;
62 BlifDumperConfig *config;
63 CellTypes ct;
64
65 SigMap sigmap;
66 dict<SigBit, int> init_bits;
67
68 BlifDumper(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BlifDumperConfig *config) :
69 f(f), module(module), design(design), config(config), ct(design), sigmap(module)
70 {
71 for (Wire *wire : module->wires())
72 if (wire->attributes.count(ID::init)) {
73 SigSpec initsig = sigmap(wire);
74 Const initval = wire->attributes.at(ID::init);
75 for (int i = 0; i < GetSize(initsig) && i < GetSize(initval); i++)
76 switch (initval[i]) {
77 case State::S0:
78 init_bits[initsig[i]] = 0;
79 break;
80 case State::S1:
81 init_bits[initsig[i]] = 1;
82 break;
83 default:
84 break;
85 }
86 }
87 }
88
89 pool<SigBit> cstr_bits_seen;
90
91 const std::string str(RTLIL::IdString id)
92 {
93 std::string str = RTLIL::unescape_id(id);
94 for (size_t i = 0; i < str.size(); i++)
95 if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
96 str[i] = '?';
97 return str;
98 }
99
100 const std::string str(RTLIL::SigBit sig)
101 {
102 cstr_bits_seen.insert(sig);
103
104 if (sig.wire == NULL) {
105 if (sig == RTLIL::State::S0) return config->false_type == "-" || config->false_type == "+" ? config->false_out.c_str() : "$false";
106 if (sig == RTLIL::State::S1) return config->true_type == "-" || config->true_type == "+" ? config->true_out.c_str() : "$true";
107 return config->undef_type == "-" || config->undef_type == "+" ? config->undef_out.c_str() : "$undef";
108 }
109
110 std::string str = RTLIL::unescape_id(sig.wire->name);
111 for (size_t i = 0; i < str.size(); i++)
112 if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
113 str[i] = '?';
114
115 if (sig.wire->width != 1)
116 str += stringf("[%d]", sig.wire->upto ? sig.wire->start_offset+sig.wire->width-sig.offset-1 : sig.wire->start_offset+sig.offset);
117
118 return str;
119 }
120
121 const std::string str_init(RTLIL::SigBit sig)
122 {
123 sigmap.apply(sig);
124
125 if (init_bits.count(sig) == 0)
126 return " 2";
127
128 string str = stringf(" %d", init_bits.at(sig));
129
130 return str;
131 }
132
133 const char *subckt_or_gate(std::string cell_type)
134 {
135 if (!config->gates_mode)
136 return "subckt";
137 if (design->module(RTLIL::escape_id(cell_type)) == nullptr)
138 return "gate";
139 if (design->module(RTLIL::escape_id(cell_type))->get_blackbox_attribute())
140 return "gate";
141 return "subckt";
142 }
143
144 void dump_params(const char *command, dict<IdString, Const> &params)
145 {
146 for (auto &param : params) {
147 f << stringf("%s %s ", command, log_id(param.first));
148 if (param.second.flags & RTLIL::CONST_FLAG_STRING) {
149 std::string str = param.second.decode_string();
150 f << stringf("\"");
151 for (char ch : str)
152 if (ch == '"' || ch == '\\')
153 f << stringf("\\%c", ch);
154 else if (ch < 32 || ch >= 127)
155 f << stringf("\\%03o", ch);
156 else
157 f << stringf("%c", ch);
158 f << stringf("\"\n");
159 } else
160 f << stringf("%s\n", param.second.as_string().c_str());
161 }
162 }
163
164 void dump()
165 {
166 f << stringf("\n");
167 f << stringf(".model %s\n", str(module->name).c_str());
168
169 std::map<int, RTLIL::Wire*> inputs, outputs;
170
171 for (auto wire : module->wires()) {
172 if (wire->port_input)
173 inputs[wire->port_id] = wire;
174 if (wire->port_output)
175 outputs[wire->port_id] = wire;
176 }
177
178 f << stringf(".inputs");
179 for (auto &it : inputs) {
180 RTLIL::Wire *wire = it.second;
181 for (int i = 0; i < wire->width; i++)
182 f << stringf(" %s", str(RTLIL::SigSpec(wire, i)).c_str());
183 }
184 f << stringf("\n");
185
186 f << stringf(".outputs");
187 for (auto &it : outputs) {
188 RTLIL::Wire *wire = it.second;
189 for (int i = 0; i < wire->width; i++)
190 f << stringf(" %s", str(RTLIL::SigSpec(wire, i)).c_str());
191 }
192 f << stringf("\n");
193
194 if (module->get_blackbox_attribute()) {
195 f << stringf(".blackbox\n");
196 f << stringf(".end\n");
197 return;
198 }
199
200 if (!config->impltf_mode) {
201 if (!config->false_type.empty()) {
202 if (config->false_type == "+")
203 f << stringf(".names %s\n", config->false_out.c_str());
204 else if (config->false_type != "-")
205 f << stringf(".%s %s %s=$false\n", subckt_or_gate(config->false_type),
206 config->false_type.c_str(), config->false_out.c_str());
207 } else
208 f << stringf(".names $false\n");
209 if (!config->true_type.empty()) {
210 if (config->true_type == "+")
211 f << stringf(".names %s\n1\n", config->true_out.c_str());
212 else if (config->true_type != "-")
213 f << stringf(".%s %s %s=$true\n", subckt_or_gate(config->true_type),
214 config->true_type.c_str(), config->true_out.c_str());
215 } else
216 f << stringf(".names $true\n1\n");
217 if (!config->undef_type.empty()) {
218 if (config->undef_type == "+")
219 f << stringf(".names %s\n", config->undef_out.c_str());
220 else if (config->undef_type != "-")
221 f << stringf(".%s %s %s=$undef\n", subckt_or_gate(config->undef_type),
222 config->undef_type.c_str(), config->undef_out.c_str());
223 } else
224 f << stringf(".names $undef\n");
225 }
226
227 for (auto cell : module->cells())
228 {
229 if (config->unbuf_types.count(cell->type)) {
230 auto portnames = config->unbuf_types.at(cell->type);
231 f << stringf(".names %s %s\n1 1\n",
232 str(cell->getPort(portnames.first)).c_str(), str(cell->getPort(portnames.second)).c_str());
233 continue;
234 }
235
236 if (!config->icells_mode && cell->type == ID($_NOT_)) {
237 f << stringf(".names %s %s\n0 1\n",
238 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::Y)).c_str());
239 goto internal_cell;
240 }
241
242 if (!config->icells_mode && cell->type == ID($_AND_)) {
243 f << stringf(".names %s %s %s\n11 1\n",
244 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
245 goto internal_cell;
246 }
247
248 if (!config->icells_mode && cell->type == ID($_OR_)) {
249 f << stringf(".names %s %s %s\n1- 1\n-1 1\n",
250 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
251 goto internal_cell;
252 }
253
254 if (!config->icells_mode && cell->type == ID($_XOR_)) {
255 f << stringf(".names %s %s %s\n10 1\n01 1\n",
256 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
257 goto internal_cell;
258 }
259
260 if (!config->icells_mode && cell->type == ID($_NAND_)) {
261 f << stringf(".names %s %s %s\n0- 1\n-0 1\n",
262 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
263 goto internal_cell;
264 }
265
266 if (!config->icells_mode && cell->type == ID($_NOR_)) {
267 f << stringf(".names %s %s %s\n00 1\n",
268 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
269 goto internal_cell;
270 }
271
272 if (!config->icells_mode && cell->type == ID($_XNOR_)) {
273 f << stringf(".names %s %s %s\n11 1\n00 1\n",
274 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
275 goto internal_cell;
276 }
277
278 if (!config->icells_mode && cell->type == ID($_ANDNOT_)) {
279 f << stringf(".names %s %s %s\n10 1\n",
280 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
281 goto internal_cell;
282 }
283
284 if (!config->icells_mode && cell->type == ID($_ORNOT_)) {
285 f << stringf(".names %s %s %s\n1- 1\n-0 1\n",
286 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::Y)).c_str());
287 goto internal_cell;
288 }
289
290 if (!config->icells_mode && cell->type == ID($_AOI3_)) {
291 f << stringf(".names %s %s %s %s\n-00 1\n0-0 1\n",
292 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::Y)).c_str());
293 goto internal_cell;
294 }
295
296 if (!config->icells_mode && cell->type == ID($_OAI3_)) {
297 f << stringf(".names %s %s %s %s\n00- 1\n--0 1\n",
298 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(), str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::Y)).c_str());
299 goto internal_cell;
300 }
301
302 if (!config->icells_mode && cell->type == ID($_AOI4_)) {
303 f << stringf(".names %s %s %s %s %s\n-0-0 1\n-00- 1\n0--0 1\n0-0- 1\n",
304 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
305 str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Y)).c_str());
306 goto internal_cell;
307 }
308
309 if (!config->icells_mode && cell->type == ID($_OAI4_)) {
310 f << stringf(".names %s %s %s %s %s\n00-- 1\n--00 1\n",
311 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
312 str(cell->getPort(ID::C)).c_str(), str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Y)).c_str());
313 goto internal_cell;
314 }
315
316 if (!config->icells_mode && cell->type == ID($_MUX_)) {
317 f << stringf(".names %s %s %s %s\n1-0 1\n-11 1\n",
318 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
319 str(cell->getPort(ID::S)).c_str(), str(cell->getPort(ID::Y)).c_str());
320 goto internal_cell;
321 }
322
323 if (!config->icells_mode && cell->type == ID($_NMUX_)) {
324 f << stringf(".names %s %s %s %s\n0-0 1\n-01 1\n",
325 str(cell->getPort(ID::A)).c_str(), str(cell->getPort(ID::B)).c_str(),
326 str(cell->getPort(ID::S)).c_str(), str(cell->getPort(ID::Y)).c_str());
327 goto internal_cell;
328 }
329
330 if (!config->icells_mode && cell->type == ID($_FF_)) {
331 f << stringf(".latch %s %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(),
332 str_init(cell->getPort(ID::Q)).c_str());
333 goto internal_cell;
334 }
335
336 if (!config->icells_mode && cell->type == ID($_DFF_N_)) {
337 f << stringf(".latch %s %s fe %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(),
338 str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
339 goto internal_cell;
340 }
341
342 if (!config->icells_mode && cell->type == ID($_DFF_P_)) {
343 f << stringf(".latch %s %s re %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(),
344 str(cell->getPort(ID::C)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
345 goto internal_cell;
346 }
347
348 if (!config->icells_mode && cell->type == ID($_DLATCH_N_)) {
349 f << stringf(".latch %s %s al %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(),
350 str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
351 goto internal_cell;
352 }
353
354 if (!config->icells_mode && cell->type == ID($_DLATCH_P_)) {
355 f << stringf(".latch %s %s ah %s%s\n", str(cell->getPort(ID::D)).c_str(), str(cell->getPort(ID::Q)).c_str(),
356 str(cell->getPort(ID::E)).c_str(), str_init(cell->getPort(ID::Q)).c_str());
357 goto internal_cell;
358 }
359
360 if (!config->icells_mode && cell->type == ID($lut)) {
361 f << stringf(".names");
362 auto &inputs = cell->getPort(ID::A);
363 auto width = cell->parameters.at(ID::WIDTH).as_int();
364 log_assert(inputs.size() == width);
365 for (int i = width-1; i >= 0; i--)
366 f << stringf(" %s", str(inputs.extract(i, 1)).c_str());
367 auto &output = cell->getPort(ID::Y);
368 log_assert(output.size() == 1);
369 f << stringf(" %s", str(output).c_str());
370 f << stringf("\n");
371 RTLIL::SigSpec mask = cell->parameters.at(ID::LUT);
372 for (int i = 0; i < (1 << width); i++)
373 if (mask[i] == State::S1) {
374 for (int j = width-1; j >= 0; j--) {
375 f << ((i>>j)&1 ? '1' : '0');
376 }
377 f << " 1\n";
378 }
379 goto internal_cell;
380 }
381
382 if (!config->icells_mode && cell->type == ID($sop)) {
383 f << stringf(".names");
384 auto &inputs = cell->getPort(ID::A);
385 auto width = cell->parameters.at(ID::WIDTH).as_int();
386 auto depth = cell->parameters.at(ID::DEPTH).as_int();
387 vector<State> table = cell->parameters.at(ID::TABLE).bits;
388 while (GetSize(table) < 2*width*depth)
389 table.push_back(State::S0);
390 log_assert(inputs.size() == width);
391 for (int i = 0; i < width; i++)
392 f << stringf(" %s", str(inputs.extract(i, 1)).c_str());
393 auto &output = cell->getPort(ID::Y);
394 log_assert(output.size() == 1);
395 f << stringf(" %s", str(output).c_str());
396 f << stringf("\n");
397 for (int i = 0; i < depth; i++) {
398 for (int j = 0; j < width; j++) {
399 bool pat0 = table.at(2*width*i + 2*j + 0) == State::S1;
400 bool pat1 = table.at(2*width*i + 2*j + 1) == State::S1;
401 if (pat0 && !pat1) f << "0";
402 else if (!pat0 && pat1) f << "1";
403 else f << "-";
404 }
405 f << " 1\n";
406 }
407 goto internal_cell;
408 }
409
410 f << stringf(".%s %s", subckt_or_gate(cell->type.str()), str(cell->type).c_str());
411 for (auto &conn : cell->connections())
412 {
413 if (conn.second.size() == 1) {
414 f << stringf(" %s=%s", str(conn.first).c_str(), str(conn.second[0]).c_str());
415 continue;
416 }
417
418 Module *m = design->module(cell->type);
419 Wire *w = m ? m->wire(conn.first) : nullptr;
420
421 if (w == nullptr) {
422 for (int i = 0; i < GetSize(conn.second); i++)
423 f << stringf(" %s[%d]=%s", str(conn.first).c_str(), i, str(conn.second[i]).c_str());
424 } else {
425 for (int i = 0; i < std::min(GetSize(conn.second), GetSize(w)); i++) {
426 SigBit sig(w, i);
427 f << stringf(" %s[%d]=%s", str(conn.first).c_str(), sig.wire->upto ?
428 sig.wire->start_offset+sig.wire->width-sig.offset-1 :
429 sig.wire->start_offset+sig.offset, str(conn.second[i]).c_str());
430 }
431 }
432 }
433 f << stringf("\n");
434
435 if (config->cname_mode)
436 f << stringf(".cname %s\n", str(cell->name).c_str());
437 if (config->attr_mode)
438 dump_params(".attr", cell->attributes);
439 if (config->param_mode)
440 dump_params(".param", cell->parameters);
441
442 if (0) {
443 internal_cell:
444 if (config->iname_mode)
445 f << stringf(".cname %s\n", str(cell->name).c_str());
446 if (config->iattr_mode)
447 dump_params(".attr", cell->attributes);
448 }
449 }
450
451 for (auto &conn : module->connections())
452 for (int i = 0; i < conn.first.size(); i++)
453 {
454 SigBit lhs_bit = conn.first[i];
455 SigBit rhs_bit = conn.second[i];
456
457 if (config->noalias_mode && cstr_bits_seen.count(lhs_bit) == 0)
458 continue;
459
460 if (config->conn_mode)
461 f << stringf(".conn %s %s\n", str(rhs_bit).c_str(), str(lhs_bit).c_str());
462 else if (!config->buf_type.empty())
463 f << stringf(".%s %s %s=%s %s=%s\n", subckt_or_gate(config->buf_type), config->buf_type.c_str(),
464 config->buf_in.c_str(), str(rhs_bit).c_str(), config->buf_out.c_str(), str(lhs_bit).c_str());
465 else
466 f << stringf(".names %s %s\n1 1\n", str(rhs_bit).c_str(), str(lhs_bit).c_str());
467 }
468
469 f << stringf(".end\n");
470 }
471
472 static void dump(std::ostream &f, RTLIL::Module *module, RTLIL::Design *design, BlifDumperConfig &config)
473 {
474 BlifDumper dumper(f, module, design, &config);
475 dumper.dump();
476 }
477 };
478
479 struct BlifBackend : public Backend {
480 BlifBackend() : Backend("blif", "write design to BLIF file") { }
481 void help() override
482 {
483 // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
484 log("\n");
485 log(" write_blif [options] [filename]\n");
486 log("\n");
487 log("Write the current design to an BLIF file.\n");
488 log("\n");
489 log(" -top top_module\n");
490 log(" set the specified module as design top module\n");
491 log("\n");
492 log(" -buf <cell-type> <in-port> <out-port>\n");
493 log(" use cells of type <cell-type> with the specified port names for buffers\n");
494 log("\n");
495 log(" -unbuf <cell-type> <in-port> <out-port>\n");
496 log(" replace buffer cells with the specified name and port names with\n");
497 log(" a .names statement that models a buffer\n");
498 log("\n");
499 log(" -true <cell-type> <out-port>\n");
500 log(" -false <cell-type> <out-port>\n");
501 log(" -undef <cell-type> <out-port>\n");
502 log(" use the specified cell types to drive nets that are constant 1, 0, or\n");
503 log(" undefined. when '-' is used as <cell-type>, then <out-port> specifies\n");
504 log(" the wire name to be used for the constant signal and no cell driving\n");
505 log(" that wire is generated. when '+' is used as <cell-type>, then <out-port>\n");
506 log(" specifies the wire name to be used for the constant signal and a .names\n");
507 log(" statement is generated to drive the wire.\n");
508 log("\n");
509 log(" -noalias\n");
510 log(" if a net name is aliasing another net name, then by default a net\n");
511 log(" without fanout is created that is driven by the other net. This option\n");
512 log(" suppresses the generation of this nets without fanout.\n");
513 log("\n");
514 log("The following options can be useful when the generated file is not going to be\n");
515 log("read by a BLIF parser but a custom tool. It is recommended to not name the output\n");
516 log("file *.blif when any of this options is used.\n");
517 log("\n");
518 log(" -icells\n");
519 log(" do not translate Yosys's internal gates to generic BLIF logic\n");
520 log(" functions. Instead create .subckt or .gate lines for all cells.\n");
521 log("\n");
522 log(" -gates\n");
523 log(" print .gate instead of .subckt lines for all cells that are not\n");
524 log(" instantiations of other modules from this design.\n");
525 log("\n");
526 log(" -conn\n");
527 log(" do not generate buffers for connected wires. instead use the\n");
528 log(" non-standard .conn statement.\n");
529 log("\n");
530 log(" -attr\n");
531 log(" use the non-standard .attr statement to write cell attributes\n");
532 log("\n");
533 log(" -param\n");
534 log(" use the non-standard .param statement to write cell parameters\n");
535 log("\n");
536 log(" -cname\n");
537 log(" use the non-standard .cname statement to write cell names\n");
538 log("\n");
539 log(" -iname, -iattr\n");
540 log(" enable -cname and -attr functionality for .names statements\n");
541 log(" (the .cname and .attr statements will be included in the BLIF\n");
542 log(" output after the truth table for the .names statement)\n");
543 log("\n");
544 log(" -blackbox\n");
545 log(" write blackbox cells with .blackbox statement.\n");
546 log("\n");
547 log(" -impltf\n");
548 log(" do not write definitions for the $true, $false and $undef wires.\n");
549 log("\n");
550 }
551 void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) override
552 {
553 std::string top_module_name;
554 std::string buf_type, buf_in, buf_out;
555 std::string true_type, true_out;
556 std::string false_type, false_out;
557 BlifDumperConfig config;
558
559 log_header(design, "Executing BLIF backend.\n");
560
561 size_t argidx;
562 for (argidx = 1; argidx < args.size(); argidx++)
563 {
564 if (args[argidx] == "-top" && argidx+1 < args.size()) {
565 top_module_name = args[++argidx];
566 continue;
567 }
568 if (args[argidx] == "-buf" && argidx+3 < args.size()) {
569 config.buf_type = args[++argidx];
570 config.buf_in = args[++argidx];
571 config.buf_out = args[++argidx];
572 continue;
573 }
574 if (args[argidx] == "-unbuf" && argidx+3 < args.size()) {
575 RTLIL::IdString unbuf_type = RTLIL::escape_id(args[++argidx]);
576 RTLIL::IdString unbuf_in = RTLIL::escape_id(args[++argidx]);
577 RTLIL::IdString unbuf_out = RTLIL::escape_id(args[++argidx]);
578 config.unbuf_types[unbuf_type] = std::pair<RTLIL::IdString, RTLIL::IdString>(unbuf_in, unbuf_out);
579 continue;
580 }
581 if (args[argidx] == "-true" && argidx+2 < args.size()) {
582 config.true_type = args[++argidx];
583 config.true_out = args[++argidx];
584 continue;
585 }
586 if (args[argidx] == "-false" && argidx+2 < args.size()) {
587 config.false_type = args[++argidx];
588 config.false_out = args[++argidx];
589 continue;
590 }
591 if (args[argidx] == "-undef" && argidx+2 < args.size()) {
592 config.undef_type = args[++argidx];
593 config.undef_out = args[++argidx];
594 continue;
595 }
596 if (args[argidx] == "-icells") {
597 config.icells_mode = true;
598 continue;
599 }
600 if (args[argidx] == "-gates") {
601 config.gates_mode = true;
602 continue;
603 }
604 if (args[argidx] == "-conn") {
605 config.conn_mode = true;
606 continue;
607 }
608 if (args[argidx] == "-cname") {
609 config.cname_mode = true;
610 continue;
611 }
612 if (args[argidx] == "-param") {
613 config.param_mode = true;
614 continue;
615 }
616 if (args[argidx] == "-attr") {
617 config.attr_mode = true;
618 continue;
619 }
620 if (args[argidx] == "-iname") {
621 config.iname_mode = true;
622 continue;
623 }
624 if (args[argidx] == "-iattr") {
625 config.iattr_mode = true;
626 continue;
627 }
628 if (args[argidx] == "-blackbox") {
629 config.blackbox_mode = true;
630 continue;
631 }
632 if (args[argidx] == "-impltf") {
633 config.impltf_mode = true;
634 continue;
635 }
636 if (args[argidx] == "-noalias") {
637 config.noalias_mode = true;
638 continue;
639 }
640 break;
641 }
642 extra_args(f, filename, args, argidx);
643
644 if (top_module_name.empty())
645 for (auto module : design->modules())
646 if (module->get_bool_attribute(ID::top))
647 top_module_name = module->name.str();
648
649 *f << stringf("# Generated by %s\n", yosys_version_str);
650
651 std::vector<RTLIL::Module*> mod_list;
652
653 design->sort();
654 for (auto module : design->modules())
655 {
656 if (module->get_blackbox_attribute() && !config.blackbox_mode)
657 continue;
658
659 if (module->processes.size() != 0)
660 log_error("Found unmapped processes in module %s: unmapped processes are not supported in BLIF backend!\n", log_id(module->name));
661 if (module->memories.size() != 0)
662 log_error("Found unmapped memories in module %s: unmapped memories are not supported in BLIF backend!\n", log_id(module->name));
663
664 if (module->name == RTLIL::escape_id(top_module_name)) {
665 BlifDumper::dump(*f, module, design, config);
666 top_module_name.clear();
667 continue;
668 }
669
670 mod_list.push_back(module);
671 }
672
673 if (!top_module_name.empty())
674 log_error("Can't find top module `%s'!\n", top_module_name.c_str());
675
676 for (auto module : mod_list)
677 BlifDumper::dump(*f, module, design, config);
678 }
679 } BlifBackend;
680
681 PRIVATE_NAMESPACE_END