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arch-arm: Decode SEVL instruction for A32 and T32 IS
[gem5.git] / build_opts / ARM_MESI_Three_Level
1 # Copyright (c) 2019 ARM Limited
2 # All rights reserved.
3
4 TARGET_ISA = 'arm'
5 CPU_MODELS = 'TimingSimpleCPU, O3CPU'
6 PROTOCOL = 'MESI_Three_Level'