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misc: merge branch 'release-staging-v19.0.0.0' into develop
[gem5.git] / build_opts / RISCV
1 TARGET_ISA = 'riscv'
2 CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,MinorCPU,O3CPU'
3 PROTOCOL = 'MI_example'