cache_ram.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4 use ieee.math_real.all;
   5
   6 entity cache_ram is
   7     generic(
   8         ROW_BITS : integer := 16;
   9         WIDTH    : integer := 64;
  10         TRACE    : boolean := false;
  11         ADD_BUF  : boolean := false
  12         );
  13
  14     port(
  15         clk     : in  std_logic;
  16         rd_en   : in  std_logic;
  17         rd_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
  18         rd_data : out std_logic_vector(WIDTH - 1 downto 0);
  19         wr_en   : in  std_logic;
  20         wr_sel  : in  std_logic_vector(WIDTH/8 - 1 downto 0);
  21         wr_addr : in  std_logic_vector(ROW_BITS - 1 downto 0);
  22         wr_data : in  std_logic_vector(WIDTH - 1 downto 0)
  23         );
  24
  25 end cache_ram;
  26
  27 architecture rtl of cache_ram is
  28     constant SIZE : integer := 2**ROW_BITS;
  29
  30     type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
  31     signal ram : ram_type;
  32     attribute ram_style : string;
  33     attribute ram_style of ram : signal is "block";
  34     attribute ram_decomp : string;
  35     attribute ram_decomp of ram : signal is "power";
  36
  37     signal rd_data0 : std_logic_vector(WIDTH - 1 downto 0);
  38
  39 begin
  40     process(clk)
  41         variable lbit : integer range 0 to WIDTH - 1;
  42         variable mbit : integer range 0 to WIDTH - 1;
  43         variable widx : integer range 0 to SIZE - 1;
  44     begin
  45         if rising_edge(clk) then
  46             if wr_en = '1' then
  47                 if TRACE then
  48                     report "write a:" & to_hstring(wr_addr) &
  49                         " sel:" & to_hstring(wr_sel) &
  50                         " dat:" & to_hstring(wr_data);
  51                 end if;
  52                 for i in 0 to WIDTH/8-1 loop
  53                     lbit := i * 8;
  54                     mbit := lbit + 7;
  55                     widx := to_integer(unsigned(wr_addr));
  56                     if wr_sel(i) = '1' then
  57                         ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
  58                     end if;
  59                 end loop;
  60             end if;
  61             if rd_en = '1' then
  62                 rd_data0 <= ram(to_integer(unsigned(rd_addr)));
  63                 if TRACE then
  64                     report "read a:" & to_hstring(rd_addr) &
  65                         " dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
  66                 end if;
  67             end if;
  68         end if;
  69     end process;
  70
  71     buf: if ADD_BUF generate
  72     begin
  73         process(clk)
  74         begin
  75             if rising_edge(clk) then
  76                 rd_data <= rd_data0;
  77             end if;
  78         end process;
  79     end generate;
  80
  81     nobuf: if not ADD_BUF generate
  82     begin
  83         rd_data <= rd_data0;
  84     end generate;
  85
  86 end;