2 use ieee.std_logic_1164.all;
3 use ieee.numeric_std.all;
4 use ieee.math_real.all;
8 ROW_BITS : integer := 16;
10 TRACE : boolean := false;
11 ADD_BUF : boolean := false
17 rd_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
18 rd_data : out std_logic_vector(WIDTH - 1 downto 0);
20 wr_sel : in std_logic_vector(WIDTH/8 - 1 downto 0);
21 wr_addr : in std_logic_vector(ROW_BITS - 1 downto 0);
22 wr_data : in std_logic_vector(WIDTH - 1 downto 0)
27 architecture rtl of cache_ram is
28 constant SIZE : integer := 2**ROW_BITS;
30 type ram_type is array (0 to SIZE - 1) of std_logic_vector(WIDTH - 1 downto 0);
31 signal ram : ram_type;
32 attribute ram_style : string;
33 attribute ram_style of ram : signal is "block";
34 attribute ram_decomp : string;
35 attribute ram_decomp of ram : signal is "power";
37 signal rd_data0 : std_logic_vector(WIDTH - 1 downto 0);
41 variable lbit : integer range 0 to WIDTH - 1;
42 variable mbit : integer range 0 to WIDTH - 1;
43 variable widx : integer range 0 to SIZE - 1;
45 if rising_edge(clk) then
48 report "write a:" & to_hstring(wr_addr) &
49 " sel:" & to_hstring(wr_sel) &
50 " dat:" & to_hstring(wr_data);
52 for i in 0 to WIDTH/8-1 loop
55 widx := to_integer(unsigned(wr_addr));
56 if wr_sel(i) = '1' then
57 ram(widx)(mbit downto lbit) <= wr_data(mbit downto lbit);
62 rd_data0 <= ram(to_integer(unsigned(rd_addr)));
64 report "read a:" & to_hstring(rd_addr) &
65 " dat:" & to_hstring(ram(to_integer(unsigned(rd_addr))));
71 buf: if ADD_BUF generate
75 if rising_edge(clk) then
81 nobuf: if not ADD_BUF generate