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  26 Subject: Re: [libre-riscv-dev] daily kan-ban update 18may2020
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  54
  55 Luke Kenneth Casson Leighton schreef op ma 18-05-2020 om 12:45 [+0100]:
  56 > * and had a fascinating conversation thanks to yehowshua and jeremy(also =
  57 welcome!), which resulted in this(https://libre-soc.org/3d_gpu/architecture=
  58 /tomasulo_transformation/).
  59
  60 If I understand this correct the big architectural difference between exten=
  61 ded scoreboarding and Tomasulo is that in the former the register content i=
  62 s stored in a central register file and for the latter it is distributed ov=
  63 er several 'reservation stations'. In order to scale to for example multi-i=
  64 ssue you need to go to higher order nRmW register files for scoreboarding a=
  65 nd for Tomasulo you increase the number of reservation stations together wi=
  66 th a more complex tracker of the register tagging/aliasing.
  67 So some 2 cents from me.
  68 =46rom physical implementation point of view the central high order nRmW regi=
  69 ster file and scoreboard does worry me. Higher order nRmW register files wi=
  70 ll become power and area hungry compared to multiple lower order reservatio=
  71 n stations.
  72 I have seen numbers of a few tens of functional units in your design. I thi=
  73 nk it will become also a nightmare to connect and route all the input and o=
  74 utputs of all the functional units to the central register file and scorebo=
  75 ard. So at first sight, from physical implementation point for smaller node=
  76 s, the Tomasulo algorithm seems more scalable than extended scoreboarding. =
  77 I indicated before that in smaller nodes power consumption and delay is mai=
  78 nly determined by the length of the interconnects and not by the input load=
  79  of the logic gates itself; in 180nm it will be more fifty/fifty. As Jeremy=
  80  indicated this is next to the power consumption in the register files and =
  81 cache which scales with the total bit count of the block and the nRmW order=
  82  of the block.
  83 Also the travialness of a big fan-in NOR or NAND gate may be deceptive, the=
  84 se gates are not feasible and will be synthesized to trees of NAND/NOR gate=
  85 s. In that respect a high fan-in NOR/NAND can have similar time/power consu=
  86 mption than a seemingly more complex case of if statement. In zero order, f=
  87 or single output block, delay and power is determined by the number of inpu=
  88 ts independent of the complexity of the RTL/HDL code. In first order one ha=
  89 s to account that NAND/NOR logic is more efficient than XOR/XNOR logic but =
  90 for bigger trees this difference is less pronounced as XOR/XNOR trees will =
  91 be synthesized to more efficient trees using AOI (and-or-invert) cells.
  92
  93 greets,
  94 Staf.
  95
  96
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