1 # See LICENSE for license details.
14 # export to bootloader
15 export ROMCONF
=$(BUILD_DIR
)/$(CONFIG_PROJECT
).
$(CONFIG
).rom.conf
17 # export to fpga-shells
18 export FPGA_TOP_SYSTEM
=$(MODEL
)
19 export FPGA_BUILD_DIR
=$(BUILD_DIR
)/$(FPGA_TOP_SYSTEM
)
20 export fpga_common_script_dir
=$(FPGA_DIR
)/common
/tcl
21 export fpga_board_script_dir
=$(FPGA_DIR
)/$(BOARD
)/tcl
29 base_dir
:= $(patsubst %/,%,$(dir $(abspath
$(lastword
$(MAKEFILE_LIST
)))))
30 export rocketchip_dir
:= $(base_dir
)/rocket-chip
31 SBT ?
= java
-jar
$(rocketchip_dir
)/sbt-launch.jar
33 # Build firrtl.jar and put it where chisel3 can find it.
34 FIRRTL_JAR ?
= $(rocketchip_dir
)/firrtl
/utils
/bin
/firrtl.jar
35 FIRRTL ?
= java
-Xmx2G
-Xss8M
-XX
:MaxPermSize
=256M
-cp
$(FIRRTL_JAR
) firrtl.Driver
37 $(FIRRTL_JAR
): $(shell find
$(rocketchip_dir
)/firrtl
/src
/main
/scala
-iname
"*.scala")
38 $(MAKE
) -C
$(rocketchip_dir
)/firrtl SBT
="$(SBT)" root_dir
=$(rocketchip_dir
)/firrtl build-scala
40 mkdir
-p
$(rocketchip_dir
)/lib
41 cp
-p
$(FIRRTL_JAR
) rocket-chip
/lib
42 mkdir
-p
$(rocketchip_dir
)/chisel3
/lib
43 cp
-p
$(FIRRTL_JAR
) $(rocketchip_dir
)/chisel3
/lib
46 firrtl
:= $(BUILD_DIR
)/$(CONFIG_PROJECT
).
$(CONFIG
).fir
47 $(firrtl
): $(shell find
$(base_dir
)/src
/main
/scala
-name
'*.scala') $(FIRRTL_JAR
)
49 $(SBT
) "run-main freechips.rocketchip.system.Generator $(BUILD_DIR) $(PROJECT) $(MODEL) $(CONFIG_PROJECT) $(CONFIG)"
55 verilog
:= $(BUILD_DIR
)/$(CONFIG_PROJECT
).
$(CONFIG
).v
56 $(verilog
): $(firrtl
) $(FIRRTL_JAR
)
57 $(FIRRTL
) -i
$(firrtl
) -o
$@
-X verilog
58 ifneq ($(PATCHVERILOG
),"")
65 romgen
:= $(BUILD_DIR
)/$(CONFIG_PROJECT
).
$(CONFIG
).rom.v
67 ifneq ($(BOOTROM_DIR
),"")
68 $(MAKE
) -C
$(BOOTROM_DIR
) romgen
69 mv
$(BUILD_DIR
)/rom.v
$@
75 f
:= $(BUILD_DIR
)/$(CONFIG_PROJECT
).
$(CONFIG
).vsrcs.F
79 bit
:= $(BUILD_DIR
)/obj
/$(MODEL
).bit
80 $(bit
): $(romgen
) $(f
)
81 cd
$(BUILD_DIR
); vivado \
82 -nojournal
-mode batch \
83 -source
$(fpga_common_script_dir
)/vivado.tcl \
85 -top-module
"$(MODEL)" \
87 -ip-vivado-tcls
"$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
92 mcs
:= $(BUILD_DIR
)/obj
/$(MODEL
).mcs
94 cd
$(BUILD_DIR
); vivado
-nojournal
-mode batch
-source
$(fpga_common_script_dir
)/write_cfgmem.tcl
-tclargs
$(BOARD
) $@
$<
102 ifneq ($(BOOTROM_DIR
),"")
103 $(MAKE
) -C
$(BOOTROM_DIR
) clean
105 $(MAKE
) -C
$(FPGA_DIR
) clean