2 use ieee.std_logic_1164.all;
5 use work.decode_types.all;
9 lr: std_ulogic_vector(63 downto 0);
10 ctr: std_ulogic_vector(63 downto 0);
11 tb: std_ulogic_vector(63 downto 0);
15 type Fetch1ToIcacheType is record
17 stop_mark: std_ulogic;
18 nia: std_ulogic_vector(63 downto 0);
21 type IcacheToFetch2Type is record
23 stop_mark: std_ulogic;
24 nia: std_ulogic_vector(63 downto 0);
25 insn: std_ulogic_vector(31 downto 0);
28 type Fetch2ToDecode1Type is record
30 stop_mark : std_ulogic;
31 nia: std_ulogic_vector(63 downto 0);
32 insn: std_ulogic_vector(31 downto 0);
34 constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', others => (others => '0'));
36 type Decode1ToDecode2Type is record
38 stop_mark : std_ulogic;
39 nia: std_ulogic_vector(63 downto 0);
40 insn: std_ulogic_vector(31 downto 0);
43 constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
45 type Decode2ToExecute1Type is record
47 insn_type: insn_type_t;
48 nia: std_ulogic_vector(63 downto 0);
49 write_reg: std_ulogic_vector(4 downto 0);
50 read_reg1: std_ulogic_vector(4 downto 0);
51 read_reg2: std_ulogic_vector(4 downto 0);
52 read_data1: std_ulogic_vector(63 downto 0);
53 read_data2: std_ulogic_vector(63 downto 0);
54 read_data3: std_ulogic_vector(63 downto 0);
55 cr: std_ulogic_vector(31 downto 0);
59 input_carry: carry_in_t;
60 output_carry: std_ulogic;
62 output_cr: std_ulogic;
64 is_signed: std_ulogic;
65 insn: std_ulogic_vector(31 downto 0);
67 constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
68 (valid => '0', insn_type => OP_ILLEGAL, lr => '0', rc => '0', invert_a => '0',
69 input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
70 is_32bit => '0', is_signed => '0', others => (others => '0'));
72 type Decode2ToMultiplyType is record
74 insn_type: insn_type_t;
75 write_reg: std_ulogic_vector(4 downto 0);
76 data1: std_ulogic_vector(64 downto 0);
77 data2: std_ulogic_vector(64 downto 0);
80 constant Decode2ToMultiplyInit : Decode2ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', others => (others => '0'));
82 type Decode2ToDividerType is record
84 write_reg: std_ulogic_vector(4 downto 0);
85 dividend: std_ulogic_vector(63 downto 0);
86 divisor: std_ulogic_vector(63 downto 0);
87 is_signed: std_ulogic;
89 is_extended: std_ulogic;
90 is_modulus: std_ulogic;
93 constant Decode2ToDividerInit: Decode2ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0', is_extended => '0', is_modulus => '0', rc => '0', others => (others => '0'));
95 type Decode2ToRegisterFileType is record
96 read1_enable : std_ulogic;
97 read1_reg : std_ulogic_vector(4 downto 0);
98 read2_enable : std_ulogic;
99 read2_reg : std_ulogic_vector(4 downto 0);
100 read3_enable : std_ulogic;
101 read3_reg : std_ulogic_vector(4 downto 0);
104 type RegisterFileToDecode2Type is record
105 read1_data : std_ulogic_vector(63 downto 0);
106 read2_data : std_ulogic_vector(63 downto 0);
107 read3_data : std_ulogic_vector(63 downto 0);
110 type Decode2ToCrFileType is record
114 type CrFileToDecode2Type is record
115 read_cr_data : std_ulogic_vector(31 downto 0);
118 type Execute1ToFetch1Type is record
119 redirect: std_ulogic;
120 redirect_nia: std_ulogic_vector(63 downto 0);
122 constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
124 type Decode2ToLoadstore1Type is record
126 load : std_ulogic; -- is this a load or store
127 addr1 : std_ulogic_vector(63 downto 0);
128 addr2 : std_ulogic_vector(63 downto 0);
129 data : std_ulogic_vector(63 downto 0); -- data to write, unused for read
130 write_reg : std_ulogic_vector(4 downto 0); -- read data goes to this register
131 length : std_ulogic_vector(3 downto 0);
132 byte_reverse : std_ulogic;
133 sign_extend : std_ulogic; -- do we need to sign extend?
134 update : std_ulogic; -- is this an update instruction?
135 update_reg : std_ulogic_vector(4 downto 0); -- if so, the register to update
137 constant Decode2ToLoadstore1Init : Decode2ToLoadstore1Type := (valid => '0', load => '0', byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
139 type Loadstore1ToLoadstore2Type is record
142 addr : std_ulogic_vector(63 downto 0);
143 data : std_ulogic_vector(63 downto 0);
144 write_reg : std_ulogic_vector(4 downto 0);
145 length : std_ulogic_vector(3 downto 0);
146 byte_reverse : std_ulogic;
147 sign_extend : std_ulogic;
149 update_reg : std_ulogic_vector(4 downto 0);
152 type Loadstore2ToWritebackType is record
154 write_enable: std_ulogic;
155 write_reg : std_ulogic_vector(4 downto 0);
156 write_data : std_ulogic_vector(63 downto 0);
158 constant Loadstore2ToWritebackInit : Loadstore2ToWritebackType := (valid => '0', write_enable => '0', others => (others => '0'));
160 type Execute1ToExecute2Type is record
162 write_enable : std_ulogic;
163 write_reg: std_ulogic_vector(4 downto 0);
164 write_data: std_ulogic_vector(63 downto 0);
165 write_cr_enable : std_ulogic;
166 write_cr_mask : std_ulogic_vector(7 downto 0);
167 write_cr_data : std_ulogic_vector(31 downto 0);
170 constant Execute1ToExecute2Init : Execute1ToExecute2Type := (valid => '0', write_enable => '0', write_cr_enable => '0', rc => '0', others => (others => '0'));
172 type Execute2ToWritebackType is record
174 write_enable : std_ulogic;
175 write_reg: std_ulogic_vector(4 downto 0);
176 write_data: std_ulogic_vector(63 downto 0);
177 write_cr_enable : std_ulogic;
178 write_cr_mask : std_ulogic_vector(7 downto 0);
179 write_cr_data : std_ulogic_vector(31 downto 0);
181 constant Execute2ToWritebackInit : Execute2ToWritebackType := (valid => '0', write_enable => '0', write_cr_enable => '0', others => (others => '0'));
183 type MultiplyToWritebackType is record
186 write_reg_enable : std_ulogic;
187 write_reg_nr: std_ulogic_vector(4 downto 0);
188 write_reg_data: std_ulogic_vector(63 downto 0);
189 write_cr_enable: std_ulogic;
190 write_cr_mask: std_ulogic_vector(7 downto 0);
191 write_cr_data: std_ulogic_vector(31 downto 0);
193 constant MultiplyToWritebackInit : MultiplyToWritebackType := (valid => '0', write_reg_enable => '0', write_cr_enable => '0', others => (others => '0'));
195 type DividerToWritebackType is record
198 write_reg_enable : std_ulogic;
199 write_reg_nr: std_ulogic_vector(4 downto 0);
200 write_reg_data: std_ulogic_vector(63 downto 0);
201 write_cr_enable: std_ulogic;
202 write_cr_mask: std_ulogic_vector(7 downto 0);
203 write_cr_data: std_ulogic_vector(31 downto 0);
205 constant DividerToWritebackInit : DividerToWritebackType := (valid => '0', write_reg_enable => '0', write_cr_enable => '0', others => (others => '0'));
207 type WritebackToRegisterFileType is record
208 write_reg : std_ulogic_vector(4 downto 0);
209 write_data : std_ulogic_vector(63 downto 0);
210 write_enable : std_ulogic;
212 constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
214 type WritebackToCrFileType is record
215 write_cr_enable : std_ulogic;
216 write_cr_mask : std_ulogic_vector(7 downto 0);
217 write_cr_data : std_ulogic_vector(31 downto 0);
219 constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', others => (others => '0'));
222 package body common is