common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.decode_types.all;
   6
   7 package common is
   8         type ctrl_t is record
   9                 lr: std_ulogic_vector(63 downto 0);
  10                 ctr: std_ulogic_vector(63 downto 0);
  11                 tb: std_ulogic_vector(63 downto 0);
  12                 carry: std_ulogic;
  13         end record;
  14
  15         type Fetch1ToFetch2Type is record
  16                 valid: std_ulogic;
  17                 nia: std_ulogic_vector(63 downto 0);
  18         end record;
  19
  20         type Fetch2ToDecode1Type is record
  21                 valid: std_ulogic;
  22                 nia: std_ulogic_vector(63 downto 0);
  23                 insn: std_ulogic_vector(31 downto 0);
  24         end record;
  25         constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', others => (others => '0'));
  26
  27         type Decode1ToDecode2Type is record
  28                 valid: std_ulogic;
  29                 nia: std_ulogic_vector(63 downto 0);
  30                 insn: std_ulogic_vector(31 downto 0);
  31                 decode: decode_rom_t;
  32         end record;
  33         constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', decode => decode_rom_init, others => (others => '0'));
  34
  35         type Decode2ToExecute1Type is record
  36                 valid: std_ulogic;
  37                 insn_type: insn_type_t;
  38                 nia: std_ulogic_vector(63 downto 0);
  39                 write_reg: std_ulogic_vector(4 downto 0);
  40                 read_reg1: std_ulogic_vector(4 downto 0);
  41                 read_reg2: std_ulogic_vector(4 downto 0);
  42                 read_data1: std_ulogic_vector(63 downto 0);
  43                 read_data2: std_ulogic_vector(63 downto 0);
  44                 const1: std_ulogic_vector(7 downto 0);
  45                 const2: std_ulogic_vector(5 downto 0);
  46                 const3: std_ulogic_vector(4 downto 0);
  47                 cr: std_ulogic_vector(31 downto 0);
  48                 lr: std_ulogic;
  49                 rc: std_ulogic;
  50                 input_carry: std_ulogic;
  51                 output_carry: std_ulogic;
  52                 input_cr: std_ulogic;
  53                 output_cr: std_ulogic;
  54         end record;
  55         constant Decode2ToExecute1Init : Decode2ToExecute1Type := (valid => '0', insn_type => OP_ILLEGAL, lr => '0', rc => '0', input_carry => '0', output_carry => '0', input_cr => '0', output_cr => '0', others => (others => '0'));
  56
  57         type Decode2ToMultiplyType is record
  58                 valid: std_ulogic;
  59                 insn_type: insn_type_t;
  60                 nia: std_ulogic_vector(63 downto 0);
  61                 write_reg: std_ulogic_vector(4 downto 0);
  62                 data1: std_ulogic_vector(64 downto 0);
  63                 data2: std_ulogic_vector(64 downto 0);
  64                 rc: std_ulogic;
  65         end record;
  66         constant Decode2ToMultiplyInit : Decode2ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', others => (others => '0'));
  67
  68         type Decode2ToRegisterFileType is record
  69                 read1_enable : std_ulogic;
  70                 read1_reg : std_ulogic_vector(4 downto 0);
  71                 read2_enable : std_ulogic;
  72                 read2_reg : std_ulogic_vector(4 downto 0);
  73                 read3_enable : std_ulogic;
  74                 read3_reg : std_ulogic_vector(4 downto 0);
  75         end record;
  76
  77         type RegisterFileToDecode2Type is record
  78                 read1_data : std_ulogic_vector(63 downto 0);
  79                 read2_data : std_ulogic_vector(63 downto 0);
  80                 read3_data : std_ulogic_vector(63 downto 0);
  81         end record;
  82
  83         type Decode2ToCrFileType is record
  84                 read : std_ulogic;
  85         end record;
  86
  87         type CrFileToDecode2Type is record
  88                 read_cr_data   : std_ulogic_vector(31 downto 0);
  89         end record;
  90
  91         type Execute1ToFetch1Type is record
  92                 redirect: std_ulogic;
  93                 redirect_nia: std_ulogic_vector(63 downto 0);
  94         end record;
  95         constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
  96
  97         type Decode2ToLoadstore1Type is record
  98                 valid : std_ulogic;
  99                 nia: std_ulogic_vector(63 downto 0);
 100                 load : std_ulogic;                              -- is this a load or store
 101                 addr1 : std_ulogic_vector(63 downto 0);
 102                 addr2 : std_ulogic_vector(63 downto 0);
 103                 data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 104                 write_reg : std_ulogic_vector(4 downto 0);      -- read data goes to this register
 105                 length : std_ulogic_vector(3 downto 0);
 106                 byte_reverse : std_ulogic;
 107                 sign_extend : std_ulogic;                       -- do we need to sign extend?
 108                 update : std_ulogic;                            -- is this an update instruction?
 109                 update_reg : std_ulogic_vector(4 downto 0);     -- if so, the register to update
 110         end record;
 111         constant Decode2ToLoadstore1Init : Decode2ToLoadstore1Type := (valid => '0', load => '0', byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
 112
 113         type Loadstore1ToLoadstore2Type is record
 114                 valid : std_ulogic;
 115                 load : std_ulogic;
 116                 addr : std_ulogic_vector(63 downto 0);
 117                 data : std_ulogic_vector(63 downto 0);
 118                 write_reg : std_ulogic_vector(4 downto 0);
 119                 length : std_ulogic_vector(3 downto 0);
 120                 byte_reverse : std_ulogic;
 121                 sign_extend : std_ulogic;
 122                 update : std_ulogic;
 123                 update_reg : std_ulogic_vector(4 downto 0);
 124         end record;
 125
 126         type Loadstore2ToWritebackType is record
 127                 valid : std_ulogic;
 128                 write_enable: std_ulogic;
 129                 write_reg : std_ulogic_vector(4 downto 0);
 130                 write_data : std_ulogic_vector(63 downto 0);
 131                 write_enable2: std_ulogic;
 132                 write_reg2 : std_ulogic_vector(4 downto 0);
 133                 write_data2 : std_ulogic_vector(63 downto 0);
 134         end record;
 135         constant Loadstore2ToWritebackInit : Loadstore2ToWritebackType := (valid => '0', write_enable => '0', write_enable2 => '0', others => (others => '0'));
 136
 137         type Execute1ToExecute2Type is record
 138                 valid: std_ulogic;
 139                 write_enable : std_ulogic;
 140                 write_reg: std_ulogic_vector(4 downto 0);
 141                 write_data: std_ulogic_vector(63 downto 0);
 142                 write_cr_enable : std_ulogic;
 143                 write_cr_mask : std_ulogic_vector(7 downto 0);
 144                 write_cr_data : std_ulogic_vector(31 downto 0);
 145                 rc : std_ulogic;
 146         end record;
 147         constant Execute1ToExecute2Init : Execute1ToExecute2Type := (valid => '0', write_enable => '0', write_cr_enable => '0', rc => '0', others => (others => '0'));
 148
 149         type Execute2ToWritebackType is record
 150                 valid: std_ulogic;
 151                 write_enable : std_ulogic;
 152                 write_reg: std_ulogic_vector(4 downto 0);
 153                 write_data: std_ulogic_vector(63 downto 0);
 154                 write_cr_enable : std_ulogic;
 155                 write_cr_mask : std_ulogic_vector(7 downto 0);
 156                 write_cr_data : std_ulogic_vector(31 downto 0);
 157         end record;
 158         constant Execute2ToWritebackInit : Execute2ToWritebackType := (valid => '0', write_enable => '0', write_cr_enable => '0', others => (others => '0'));
 159
 160         type MultiplyToWritebackType is record
 161                 valid: std_ulogic;
 162
 163                 write_reg_enable : std_ulogic;
 164                 write_reg_nr: std_ulogic_vector(4 downto 0);
 165                 write_reg_data: std_ulogic_vector(63 downto 0);
 166                 write_cr_enable: std_ulogic;
 167                 write_cr_mask: std_ulogic_vector(7 downto 0);
 168                 write_cr_data: std_ulogic_vector(31 downto 0);
 169         end record;
 170         constant MultiplyToWritebackInit : MultiplyToWritebackType := (valid => '0', write_reg_enable => '0', write_cr_enable => '0', others => (others => '0'));
 171
 172         type WritebackToRegisterFileType is record
 173                 write_reg : std_ulogic_vector(4 downto 0);
 174                 write_data : std_ulogic_vector(63 downto 0);
 175                 write_enable : std_ulogic;
 176                 write_reg2 : std_ulogic_vector(4 downto 0);
 177                 write_data2 : std_ulogic_vector(63 downto 0);
 178                 write_enable2 : std_ulogic;
 179         end record;
 180         constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_enable2 => '0', others => (others => '0'));
 181
 182         type WritebackToCrFileType is record
 183                 write_cr_enable : std_ulogic;
 184                 write_cr_mask : std_ulogic_vector(7 downto 0);
 185                 write_cr_data : std_ulogic_vector(31 downto 0);
 186         end record;
 187         constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', others => (others => '0'));
 188
 189         -- Would prefer not to expose this outside the register file, but ghdl
 190         -- doesn't support external names
 191         type regfile is array(0 to 32) of std_ulogic_vector(63 downto 0);
 192 end common;
 193
 194 package body common is
 195 end common;