common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- MSR bit numbers
  11     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  12     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  13     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  14     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  15     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  16     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  17     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  18
  19     -- SPR numbers
  20     subtype spr_num_t is integer range 0 to 1023;
  21
  22     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  23
  24     constant SPR_XER    : spr_num_t := 1;
  25     constant SPR_LR     : spr_num_t := 8;
  26     constant SPR_CTR    : spr_num_t := 9;
  27     constant SPR_DSISR  : spr_num_t := 18;
  28     constant SPR_DAR    : spr_num_t := 19;
  29     constant SPR_TB     : spr_num_t := 268;
  30     constant SPR_DEC    : spr_num_t := 22;
  31     constant SPR_SRR0   : spr_num_t := 26;
  32     constant SPR_SRR1   : spr_num_t := 27;
  33     constant SPR_HSRR0  : spr_num_t := 314;
  34     constant SPR_HSRR1  : spr_num_t := 315;
  35     constant SPR_SPRG0  : spr_num_t := 272;
  36     constant SPR_SPRG1  : spr_num_t := 273;
  37     constant SPR_SPRG2  : spr_num_t := 274;
  38     constant SPR_SPRG3  : spr_num_t := 275;
  39     constant SPR_SPRG3U : spr_num_t := 259;
  40     constant SPR_HSPRG0 : spr_num_t := 304;
  41     constant SPR_HSPRG1 : spr_num_t := 305;
  42     constant SPR_PID    : spr_num_t := 48;
  43     constant SPR_PRTBL  : spr_num_t := 720;
  44
  45     -- GPR indices in the register file (GPR only)
  46     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  47
  48     -- Extended GPR indice (can hold an SPR)
  49     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  50
  51     -- Some SPRs are stored in the register file, they use the magic
  52     -- GPR numbers above 31.
  53     --
  54     -- The function fast_spr_num() returns the corresponding fast
  55     -- pseudo-GPR number for a given SPR number. The result MSB
  56     -- indicates if this is indeed a fast SPR. If clear, then
  57     -- the SPR is not stored in the GPR file.
  58     --
  59     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  60
  61     -- Indices conversion functions
  62     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  63     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  64     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  65     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  66
  67     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  68     -- in the CR file as a kind of CR extension (with a separate write
  69     -- control). The rest is stored as a fast SPR.
  70     type xer_common_t is record
  71         ca : std_ulogic;
  72         ca32 : std_ulogic;
  73         ov : std_ulogic;
  74         ov32 : std_ulogic;
  75         so : std_ulogic;
  76     end record;
  77     constant xerc_init : xer_common_t := (others => '0');
  78
  79     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  80
  81     -- This needs to die...
  82     type ctrl_t is record
  83         tb: std_ulogic_vector(63 downto 0);
  84         dec: std_ulogic_vector(63 downto 0);
  85         msr: std_ulogic_vector(63 downto 0);
  86         irq_state : irq_state_t;
  87         irq_nia: std_ulogic_vector(63 downto 0);
  88         srr1: std_ulogic_vector(63 downto 0);
  89     end record;
  90
  91     type Fetch1ToIcacheType is record
  92         req: std_ulogic;
  93         virt_mode : std_ulogic;
  94         priv_mode : std_ulogic;
  95         stop_mark: std_ulogic;
  96         nia: std_ulogic_vector(63 downto 0);
  97     end record;
  98
  99     type IcacheToDecode1Type is record
 100         valid: std_ulogic;
 101         stop_mark: std_ulogic;
 102         fetch_failed: std_ulogic;
 103         nia: std_ulogic_vector(63 downto 0);
 104         insn: std_ulogic_vector(31 downto 0);
 105     end record;
 106
 107     type Decode1ToDecode2Type is record
 108         valid: std_ulogic;
 109         stop_mark : std_ulogic;
 110         nia: std_ulogic_vector(63 downto 0);
 111         insn: std_ulogic_vector(31 downto 0);
 112         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 113         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 114         decode: decode_rom_t;
 115     end record;
 116     constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'), ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init);
 117
 118     type Decode2ToExecute1Type is record
 119         valid: std_ulogic;
 120         unit : unit_t;
 121         insn_type: insn_type_t;
 122         nia: std_ulogic_vector(63 downto 0);
 123         write_reg: gspr_index_t;
 124         read_reg1: gspr_index_t;
 125         read_reg2: gspr_index_t;
 126         read_data1: std_ulogic_vector(63 downto 0);
 127         read_data2: std_ulogic_vector(63 downto 0);
 128         read_data3: std_ulogic_vector(63 downto 0);
 129         bypass_data1: std_ulogic;
 130         bypass_data2: std_ulogic;
 131         bypass_data3: std_ulogic;
 132         cr: std_ulogic_vector(31 downto 0);
 133         xerc: xer_common_t;
 134         lr: std_ulogic;
 135         rc: std_ulogic;
 136         oe: std_ulogic;
 137         invert_a: std_ulogic;
 138         invert_out: std_ulogic;
 139         input_carry: carry_in_t;
 140         output_carry: std_ulogic;
 141         input_cr: std_ulogic;
 142         output_cr: std_ulogic;
 143         is_32bit: std_ulogic;
 144         is_signed: std_ulogic;
 145         insn: std_ulogic_vector(31 downto 0);
 146         data_len: std_ulogic_vector(3 downto 0);
 147         byte_reverse : std_ulogic;
 148         sign_extend : std_ulogic;                       -- do we need to sign extend?
 149         update : std_ulogic;                            -- is this an update instruction?
 150         reserve : std_ulogic;                           -- set for larx/stcx
 151     end record;
 152     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 153         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 154          lr => '0', rc => '0', oe => '0', invert_a => '0',
 155          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 156          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0',
 157          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
 158
 159     type Execute1ToMultiplyType is record
 160         valid: std_ulogic;
 161         data1: std_ulogic_vector(63 downto 0);
 162         data2: std_ulogic_vector(63 downto 0);
 163         is_32bit: std_ulogic;
 164         neg_result: std_ulogic;
 165     end record;
 166     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0',
 167                                                                  is_32bit => '0', neg_result => '0',
 168                                                                  others => (others => '0'));
 169
 170     type Execute1ToDividerType is record
 171         valid: std_ulogic;
 172         dividend: std_ulogic_vector(63 downto 0);
 173         divisor: std_ulogic_vector(63 downto 0);
 174         is_signed: std_ulogic;
 175         is_32bit: std_ulogic;
 176         is_extended: std_ulogic;
 177         is_modulus: std_ulogic;
 178         neg_result: std_ulogic;
 179     end record;
 180     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 181                                                               is_extended => '0', is_modulus => '0',
 182                                                               neg_result => '0', others => (others => '0'));
 183
 184     type Decode2ToRegisterFileType is record
 185         read1_enable : std_ulogic;
 186         read1_reg : gspr_index_t;
 187         read2_enable : std_ulogic;
 188         read2_reg : gspr_index_t;
 189         read3_enable : std_ulogic;
 190         read3_reg : gpr_index_t;
 191     end record;
 192
 193     type RegisterFileToDecode2Type is record
 194         read1_data : std_ulogic_vector(63 downto 0);
 195         read2_data : std_ulogic_vector(63 downto 0);
 196         read3_data : std_ulogic_vector(63 downto 0);
 197     end record;
 198
 199     type Decode2ToCrFileType is record
 200         read : std_ulogic;
 201     end record;
 202
 203     type CrFileToDecode2Type is record
 204         read_cr_data   : std_ulogic_vector(31 downto 0);
 205         read_xerc_data : xer_common_t;
 206     end record;
 207
 208     type Execute1ToFetch1Type is record
 209         redirect: std_ulogic;
 210         virt_mode: std_ulogic;
 211         priv_mode: std_ulogic;
 212         redirect_nia: std_ulogic_vector(63 downto 0);
 213     end record;
 214     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 215                                                                  priv_mode => '0', others => (others => '0'));
 216
 217     type Execute1ToLoadstore1Type is record
 218         valid : std_ulogic;
 219         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 220         nia : std_ulogic_vector(63 downto 0);
 221         insn : std_ulogic_vector(31 downto 0);
 222         addr1 : std_ulogic_vector(63 downto 0);
 223         addr2 : std_ulogic_vector(63 downto 0);
 224         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 225         write_reg : gpr_index_t;
 226         length : std_ulogic_vector(3 downto 0);
 227         ci : std_ulogic;                                -- cache-inhibited load/store
 228         byte_reverse : std_ulogic;
 229         sign_extend : std_ulogic;                       -- do we need to sign extend?
 230         update : std_ulogic;                            -- is this an update instruction?
 231         update_reg : gpr_index_t;                       -- if so, the register to update
 232         xerc : xer_common_t;
 233         reserve : std_ulogic;                           -- set for larx/stcx.
 234         rc : std_ulogic;                                -- set for stcx.
 235         virt_mode : std_ulogic;                         -- do translation through TLB
 236         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 237     end record;
 238     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 239                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 240                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 241                                                                      nia => (others => '0'), insn => (others => '0'),
 242                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
 243                                                                      others => (others => '0'));
 244
 245     type Loadstore1ToExecute1Type is record
 246         exception : std_ulogic;
 247         invalid : std_ulogic;
 248         perm_error : std_ulogic;
 249         rc_error : std_ulogic;
 250         badtree : std_ulogic;
 251         segment_fault : std_ulogic;
 252         instr_fault : std_ulogic;
 253     end record;
 254
 255     type Loadstore1ToDcacheType is record
 256         valid : std_ulogic;
 257         load : std_ulogic;                              -- is this a load
 258         dcbz : std_ulogic;
 259         nc : std_ulogic;
 260         reserve : std_ulogic;
 261         virt_mode : std_ulogic;
 262         priv_mode : std_ulogic;
 263         addr : std_ulogic_vector(63 downto 0);
 264         data : std_ulogic_vector(63 downto 0);
 265         byte_sel : std_ulogic_vector(7 downto 0);
 266     end record;
 267
 268     type DcacheToLoadstore1Type is record
 269         valid : std_ulogic;
 270         data : std_ulogic_vector(63 downto 0);
 271         store_done : std_ulogic;
 272         error : std_ulogic;
 273         cache_paradox : std_ulogic;
 274     end record;
 275
 276     type Loadstore1ToMmuType is record
 277         valid : std_ulogic;
 278         tlbie : std_ulogic;
 279         slbia : std_ulogic;
 280         mtspr : std_ulogic;
 281         iside : std_ulogic;
 282         load  : std_ulogic;
 283         priv  : std_ulogic;
 284         sprn  : std_ulogic_vector(9 downto 0);
 285         addr  : std_ulogic_vector(63 downto 0);
 286         rs    : std_ulogic_vector(63 downto 0);
 287     end record;
 288
 289     type MmuToLoadstore1Type is record
 290         done       : std_ulogic;
 291         invalid    : std_ulogic;
 292         badtree    : std_ulogic;
 293         segerr     : std_ulogic;
 294         perm_error : std_ulogic;
 295         rc_error   : std_ulogic;
 296         sprval     : std_ulogic_vector(63 downto 0);
 297     end record;
 298
 299     type MmuToDcacheType is record
 300         valid : std_ulogic;
 301         tlbie : std_ulogic;
 302         doall : std_ulogic;
 303         tlbld : std_ulogic;
 304         addr  : std_ulogic_vector(63 downto 0);
 305         pte   : std_ulogic_vector(63 downto 0);
 306     end record;
 307
 308     type DcacheToMmuType is record
 309         stall : std_ulogic;
 310         done  : std_ulogic;
 311         err   : std_ulogic;
 312         data  : std_ulogic_vector(63 downto 0);
 313     end record;
 314
 315     type MmuToIcacheType is record
 316         tlbld : std_ulogic;
 317         tlbie : std_ulogic;
 318         doall : std_ulogic;
 319         addr  : std_ulogic_vector(63 downto 0);
 320         pte   : std_ulogic_vector(63 downto 0);
 321     end record;
 322
 323     type Loadstore1ToWritebackType is record
 324         valid : std_ulogic;
 325         write_enable: std_ulogic;
 326         write_reg : gpr_index_t;
 327         write_data : std_ulogic_vector(63 downto 0);
 328         xerc : xer_common_t;
 329         rc : std_ulogic;
 330         store_done : std_ulogic;
 331     end record;
 332     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 333                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 334
 335     type Execute1ToWritebackType is record
 336         valid: std_ulogic;
 337         rc : std_ulogic;
 338         write_enable : std_ulogic;
 339         write_reg: gspr_index_t;
 340         write_data: std_ulogic_vector(63 downto 0);
 341         write_cr_enable : std_ulogic;
 342         write_cr_mask : std_ulogic_vector(7 downto 0);
 343         write_cr_data : std_ulogic_vector(31 downto 0);
 344         write_xerc_enable : std_ulogic;
 345         xerc : xer_common_t;
 346         exc_write_enable : std_ulogic;
 347         exc_write_reg : gspr_index_t;
 348         exc_write_data : std_ulogic_vector(63 downto 0);
 349     end record;
 350     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 351                                                                    write_cr_enable => '0', exc_write_enable => '0',
 352                                                                    write_xerc_enable => '0', xerc => xerc_init,
 353                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 354                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 355                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 356
 357     type MultiplyToExecute1Type is record
 358         valid: std_ulogic;
 359         result: std_ulogic_vector(127 downto 0);
 360         overflow : std_ulogic;
 361     end record;
 362     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 363                                                                  others => (others => '0'));
 364
 365     type DividerToExecute1Type is record
 366         valid: std_ulogic;
 367         write_reg_data: std_ulogic_vector(63 downto 0);
 368         overflow : std_ulogic;
 369     end record;
 370     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 371                                                                others => (others => '0'));
 372
 373     type WritebackToRegisterFileType is record
 374         write_reg : gspr_index_t;
 375         write_data : std_ulogic_vector(63 downto 0);
 376         write_enable : std_ulogic;
 377     end record;
 378     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 379
 380     type WritebackToCrFileType is record
 381         write_cr_enable : std_ulogic;
 382         write_cr_mask : std_ulogic_vector(7 downto 0);
 383         write_cr_data : std_ulogic_vector(31 downto 0);
 384         write_xerc_enable : std_ulogic;
 385         write_xerc_data : xer_common_t;
 386     end record;
 387     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 388                                                                write_xerc_data => xerc_init,
 389                                                                write_cr_mask => (others => '0'),
 390                                                                write_cr_data => (others => '0'));
 391
 392 end common;
 393
 394 package body common is
 395     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 396     begin
 397         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 398     end;
 399     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 400        variable n : integer range 0 to 31;
 401        -- tmp variable introduced as workaround for VCS compilation
 402        -- simulation was failing with subtype constraint mismatch error
 403        -- see GitHub PR #173
 404        variable tmp : std_ulogic_vector(4 downto 0);
 405     begin
 406        case spr is
 407        when SPR_LR =>
 408            n := 0;
 409        when SPR_CTR =>
 410            n:= 1;
 411        when SPR_SRR0 =>
 412            n := 2;
 413        when SPR_SRR1 =>
 414            n := 3;
 415        when SPR_HSRR0 =>
 416            n := 4;
 417        when SPR_HSRR1 =>
 418            n := 5;
 419        when SPR_SPRG0 =>
 420            n := 6;
 421        when SPR_SPRG1 =>
 422            n := 7;
 423        when SPR_SPRG2 =>
 424            n := 8;
 425        when SPR_SPRG3 | SPR_SPRG3U =>
 426            n := 9;
 427        when SPR_HSPRG0 =>
 428            n := 10;
 429        when SPR_HSPRG1 =>
 430            n := 11;
 431        when SPR_XER =>
 432            n := 12;
 433        when others =>
 434            n := 0;
 435            return "000000";
 436        end case;
 437        tmp := std_ulogic_vector(to_unsigned(n, 5));
 438        return "1" & tmp;
 439     end;
 440
 441     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 442     begin
 443         return i(4 downto 0);
 444     end;
 445
 446     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 447     begin
 448         return "0" & i;
 449     end;
 450
 451     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 452     begin
 453         if s(5) = '1' then
 454             return s;
 455         else
 456             return gpr_to_gspr(g);
 457         end if;
 458     end;
 459
 460     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 461     begin
 462         return s(5);
 463     end;
 464 end common;