common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9     -- Processor Version Number
  10     constant PVR_MICROWATT  : std_ulogic_vector(31 downto 0) := x"00630000";
  11
  12     -- MSR bit numbers
  13     constant MSR_SF  : integer := (63 - 0);     -- Sixty-Four bit mode
  14     constant MSR_EE  : integer := (63 - 48);    -- External interrupt Enable
  15     constant MSR_PR  : integer := (63 - 49);    -- PRoblem state
  16     constant MSR_IR  : integer := (63 - 58);    -- Instruction Relocation
  17     constant MSR_DR  : integer := (63 - 59);    -- Data Relocation
  18     constant MSR_RI  : integer := (63 - 62);    -- Recoverable Interrupt
  19     constant MSR_LE  : integer := (63 - 63);    -- Little Endian
  20
  21     -- SPR numbers
  22     subtype spr_num_t is integer range 0 to 1023;
  23
  24     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  25
  26     constant SPR_XER    : spr_num_t := 1;
  27     constant SPR_LR     : spr_num_t := 8;
  28     constant SPR_CTR    : spr_num_t := 9;
  29     constant SPR_TAR    : spr_num_t := 815;
  30     constant SPR_DSISR  : spr_num_t := 18;
  31     constant SPR_DAR    : spr_num_t := 19;
  32     constant SPR_TB     : spr_num_t := 268;
  33     constant SPR_TBU    : spr_num_t := 269;
  34     constant SPR_DEC    : spr_num_t := 22;
  35     constant SPR_SRR0   : spr_num_t := 26;
  36     constant SPR_SRR1   : spr_num_t := 27;
  37     constant SPR_CFAR   : spr_num_t := 28;
  38     constant SPR_HSRR0  : spr_num_t := 314;
  39     constant SPR_HSRR1  : spr_num_t := 315;
  40     constant SPR_SPRG0  : spr_num_t := 272;
  41     constant SPR_SPRG1  : spr_num_t := 273;
  42     constant SPR_SPRG2  : spr_num_t := 274;
  43     constant SPR_SPRG3  : spr_num_t := 275;
  44     constant SPR_SPRG3U : spr_num_t := 259;
  45     constant SPR_HSPRG0 : spr_num_t := 304;
  46     constant SPR_HSPRG1 : spr_num_t := 305;
  47     constant SPR_PID    : spr_num_t := 48;
  48     constant SPR_PRTBL  : spr_num_t := 720;
  49     constant SPR_PVR    : spr_num_t := 287;
  50
  51     -- GPR indices in the register file (GPR only)
  52     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  53
  54     -- Extended GPR indice (can hold an SPR)
  55     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  56
  57     -- Some SPRs are stored in the register file, they use the magic
  58     -- GPR numbers above 31.
  59     --
  60     -- The function fast_spr_num() returns the corresponding fast
  61     -- pseudo-GPR number for a given SPR number. The result MSB
  62     -- indicates if this is indeed a fast SPR. If clear, then
  63     -- the SPR is not stored in the GPR file.
  64     --
  65     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  66
  67     -- Indices conversion functions
  68     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  69     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  70     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  71     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  72
  73     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  74     -- in the CR file as a kind of CR extension (with a separate write
  75     -- control). The rest is stored as a fast SPR.
  76     type xer_common_t is record
  77         ca : std_ulogic;
  78         ca32 : std_ulogic;
  79         ov : std_ulogic;
  80         ov32 : std_ulogic;
  81         so : std_ulogic;
  82     end record;
  83     constant xerc_init : xer_common_t := (others => '0');
  84
  85     type irq_state_t is (WRITE_SRR0, WRITE_SRR1);
  86
  87     -- For now, fixed 16 sources, make this either a parametric
  88     -- package of some sort or an unconstrainted array.
  89     type ics_to_icp_t is record
  90         -- Level interrupts only, ICS just keeps prsenting the
  91         -- highest priority interrupt. Once handling edge, something
  92         -- smarter involving handshake & reject support will be needed
  93         src : std_ulogic_vector(3 downto 0);
  94         pri : std_ulogic_vector(7 downto 0);
  95     end record;
  96
  97     -- This needs to die...
  98     type ctrl_t is record
  99         tb: std_ulogic_vector(63 downto 0);
 100         dec: std_ulogic_vector(63 downto 0);
 101         msr: std_ulogic_vector(63 downto 0);
 102         cfar: std_ulogic_vector(63 downto 0);
 103         irq_state : irq_state_t;
 104         srr1: std_ulogic_vector(63 downto 0);
 105     end record;
 106
 107     type Fetch1ToIcacheType is record
 108         req: std_ulogic;
 109         virt_mode : std_ulogic;
 110         priv_mode : std_ulogic;
 111         stop_mark: std_ulogic;
 112         sequential: std_ulogic;
 113         nia: std_ulogic_vector(63 downto 0);
 114     end record;
 115
 116     type IcacheToDecode1Type is record
 117         valid: std_ulogic;
 118         stop_mark: std_ulogic;
 119         fetch_failed: std_ulogic;
 120         nia: std_ulogic_vector(63 downto 0);
 121         insn: std_ulogic_vector(31 downto 0);
 122     end record;
 123
 124     type Decode1ToDecode2Type is record
 125         valid: std_ulogic;
 126         stop_mark : std_ulogic;
 127         nia: std_ulogic_vector(63 downto 0);
 128         insn: std_ulogic_vector(31 downto 0);
 129         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
 130         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
 131         decode: decode_rom_t;
 132         br_pred: std_ulogic; -- Branch was predicted to be taken
 133     end record;
 134     constant Decode1ToDecode2Init : Decode1ToDecode2Type :=
 135         (valid => '0', stop_mark => '0', nia => (others => '0'), insn => (others => '0'),
 136          ispr1 => (others => '0'), ispr2 => (others => '0'), decode => decode_rom_init, br_pred => '0');
 137
 138     type Decode1ToFetch1Type is record
 139         redirect     : std_ulogic;
 140         redirect_nia : std_ulogic_vector(63 downto 0);
 141     end record;
 142
 143     type Decode2ToExecute1Type is record
 144         valid: std_ulogic;
 145         unit : unit_t;
 146         insn_type: insn_type_t;
 147         nia: std_ulogic_vector(63 downto 0);
 148         write_reg: gspr_index_t;
 149         read_reg1: gspr_index_t;
 150         read_reg2: gspr_index_t;
 151         read_data1: std_ulogic_vector(63 downto 0);
 152         read_data2: std_ulogic_vector(63 downto 0);
 153         read_data3: std_ulogic_vector(63 downto 0);
 154         bypass_data1: std_ulogic;
 155         bypass_data2: std_ulogic;
 156         bypass_data3: std_ulogic;
 157         cr: std_ulogic_vector(31 downto 0);
 158         bypass_cr : std_ulogic;
 159         xerc: xer_common_t;
 160         lr: std_ulogic;
 161         rc: std_ulogic;
 162         oe: std_ulogic;
 163         invert_a: std_ulogic;
 164         invert_out: std_ulogic;
 165         input_carry: carry_in_t;
 166         output_carry: std_ulogic;
 167         input_cr: std_ulogic;
 168         output_cr: std_ulogic;
 169         is_32bit: std_ulogic;
 170         is_signed: std_ulogic;
 171         insn: std_ulogic_vector(31 downto 0);
 172         data_len: std_ulogic_vector(3 downto 0);
 173         byte_reverse : std_ulogic;
 174         sign_extend : std_ulogic;                       -- do we need to sign extend?
 175         update : std_ulogic;                            -- is this an update instruction?
 176         reserve : std_ulogic;                           -- set for larx/stcx
 177         br_pred : std_ulogic;
 178     end record;
 179     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 180         (valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 181          bypass_cr => '0', lr => '0', rc => '0', oe => '0', invert_a => '0',
 182          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 183          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
 184          byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
 185
 186     type MultiplyInputType is record
 187         valid: std_ulogic;
 188         data1: std_ulogic_vector(63 downto 0);
 189         data2: std_ulogic_vector(63 downto 0);
 190         addend: std_ulogic_vector(127 downto 0);
 191         is_32bit: std_ulogic;
 192         not_result: std_ulogic;
 193     end record;
 194     constant MultiplyInputInit : MultiplyInputType := (valid => '0',
 195                                                        is_32bit => '0', not_result => '0',
 196                                                        others => (others => '0'));
 197
 198     type MultiplyOutputType is record
 199         valid: std_ulogic;
 200         result: std_ulogic_vector(127 downto 0);
 201         overflow : std_ulogic;
 202     end record;
 203     constant MultiplyOutputInit : MultiplyOutputType := (valid => '0', overflow => '0',
 204                                                          others => (others => '0'));
 205
 206     type Execute1ToDividerType is record
 207         valid: std_ulogic;
 208         dividend: std_ulogic_vector(63 downto 0);
 209         divisor: std_ulogic_vector(63 downto 0);
 210         is_signed: std_ulogic;
 211         is_32bit: std_ulogic;
 212         is_extended: std_ulogic;
 213         is_modulus: std_ulogic;
 214         neg_result: std_ulogic;
 215     end record;
 216     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 217                                                               is_extended => '0', is_modulus => '0',
 218                                                               neg_result => '0', others => (others => '0'));
 219
 220     type Decode2ToRegisterFileType is record
 221         read1_enable : std_ulogic;
 222         read1_reg : gspr_index_t;
 223         read2_enable : std_ulogic;
 224         read2_reg : gspr_index_t;
 225         read3_enable : std_ulogic;
 226         read3_reg : gpr_index_t;
 227     end record;
 228
 229     type RegisterFileToDecode2Type is record
 230         read1_data : std_ulogic_vector(63 downto 0);
 231         read2_data : std_ulogic_vector(63 downto 0);
 232         read3_data : std_ulogic_vector(63 downto 0);
 233     end record;
 234
 235     type Decode2ToCrFileType is record
 236         read : std_ulogic;
 237     end record;
 238
 239     type CrFileToDecode2Type is record
 240         read_cr_data   : std_ulogic_vector(31 downto 0);
 241         read_xerc_data : xer_common_t;
 242     end record;
 243
 244     type Execute1ToFetch1Type is record
 245         redirect: std_ulogic;
 246         virt_mode: std_ulogic;
 247         priv_mode: std_ulogic;
 248         redirect_nia: std_ulogic_vector(63 downto 0);
 249     end record;
 250     constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
 251                                                              priv_mode => '0', others => (others => '0'));
 252
 253     type Execute1ToLoadstore1Type is record
 254         valid : std_ulogic;
 255         op : insn_type_t;                               -- what ld/st or m[tf]spr or TLB op to do
 256         nia : std_ulogic_vector(63 downto 0);
 257         insn : std_ulogic_vector(31 downto 0);
 258         addr1 : std_ulogic_vector(63 downto 0);
 259         addr2 : std_ulogic_vector(63 downto 0);
 260         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 261         write_reg : gpr_index_t;
 262         length : std_ulogic_vector(3 downto 0);
 263         ci : std_ulogic;                                -- cache-inhibited load/store
 264         byte_reverse : std_ulogic;
 265         sign_extend : std_ulogic;                       -- do we need to sign extend?
 266         update : std_ulogic;                            -- is this an update instruction?
 267         update_reg : gpr_index_t;                       -- if so, the register to update
 268         xerc : xer_common_t;
 269         reserve : std_ulogic;                           -- set for larx/stcx.
 270         rc : std_ulogic;                                -- set for stcx.
 271         virt_mode : std_ulogic;                         -- do translation through TLB
 272         priv_mode : std_ulogic;                         -- privileged mode (MSR[PR] = 0)
 273     end record;
 274     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
 275                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 276                                                                      reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
 277                                                                      nia => (others => '0'), insn => (others => '0'),
 278                                                                      addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
 279                                                                      others => (others => '0'));
 280
 281     type Loadstore1ToExecute1Type is record
 282         busy : std_ulogic;
 283         exception : std_ulogic;
 284         invalid : std_ulogic;
 285         perm_error : std_ulogic;
 286         rc_error : std_ulogic;
 287         badtree : std_ulogic;
 288         segment_fault : std_ulogic;
 289         instr_fault : std_ulogic;
 290     end record;
 291
 292     type Loadstore1ToDcacheType is record
 293         valid : std_ulogic;
 294         load : std_ulogic;                              -- is this a load
 295         dcbz : std_ulogic;
 296         nc : std_ulogic;
 297         reserve : std_ulogic;
 298         virt_mode : std_ulogic;
 299         priv_mode : std_ulogic;
 300         addr : std_ulogic_vector(63 downto 0);
 301         data : std_ulogic_vector(63 downto 0);
 302         byte_sel : std_ulogic_vector(7 downto 0);
 303     end record;
 304
 305     type DcacheToLoadstore1Type is record
 306         valid : std_ulogic;
 307         data : std_ulogic_vector(63 downto 0);
 308         store_done : std_ulogic;
 309         error : std_ulogic;
 310         cache_paradox : std_ulogic;
 311     end record;
 312
 313     type Loadstore1ToMmuType is record
 314         valid : std_ulogic;
 315         tlbie : std_ulogic;
 316         slbia : std_ulogic;
 317         mtspr : std_ulogic;
 318         iside : std_ulogic;
 319         load  : std_ulogic;
 320         priv  : std_ulogic;
 321         sprn  : std_ulogic_vector(9 downto 0);
 322         addr  : std_ulogic_vector(63 downto 0);
 323         rs    : std_ulogic_vector(63 downto 0);
 324     end record;
 325
 326     type MmuToLoadstore1Type is record
 327         done       : std_ulogic;
 328         err        : std_ulogic;
 329         invalid    : std_ulogic;
 330         badtree    : std_ulogic;
 331         segerr     : std_ulogic;
 332         perm_error : std_ulogic;
 333         rc_error   : std_ulogic;
 334         sprval     : std_ulogic_vector(63 downto 0);
 335     end record;
 336
 337     type MmuToDcacheType is record
 338         valid : std_ulogic;
 339         tlbie : std_ulogic;
 340         doall : std_ulogic;
 341         tlbld : std_ulogic;
 342         addr  : std_ulogic_vector(63 downto 0);
 343         pte   : std_ulogic_vector(63 downto 0);
 344     end record;
 345
 346     type DcacheToMmuType is record
 347         stall : std_ulogic;
 348         done  : std_ulogic;
 349         err   : std_ulogic;
 350         data  : std_ulogic_vector(63 downto 0);
 351     end record;
 352
 353     type MmuToIcacheType is record
 354         tlbld : std_ulogic;
 355         tlbie : std_ulogic;
 356         doall : std_ulogic;
 357         addr  : std_ulogic_vector(63 downto 0);
 358         pte   : std_ulogic_vector(63 downto 0);
 359     end record;
 360
 361     type Loadstore1ToWritebackType is record
 362         valid : std_ulogic;
 363         write_enable: std_ulogic;
 364         write_reg : gpr_index_t;
 365         write_data : std_ulogic_vector(63 downto 0);
 366         xerc : xer_common_t;
 367         rc : std_ulogic;
 368         store_done : std_ulogic;
 369     end record;
 370     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 371                                                                        rc => '0', store_done => '0', write_data => (others => '0'), others => (others => '0'));
 372
 373     type Execute1ToWritebackType is record
 374         valid: std_ulogic;
 375         rc : std_ulogic;
 376         write_enable : std_ulogic;
 377         write_reg: gspr_index_t;
 378         write_data: std_ulogic_vector(63 downto 0);
 379         write_cr_enable : std_ulogic;
 380         write_cr_mask : std_ulogic_vector(7 downto 0);
 381         write_cr_data : std_ulogic_vector(31 downto 0);
 382         write_xerc_enable : std_ulogic;
 383         xerc : xer_common_t;
 384         exc_write_enable : std_ulogic;
 385         exc_write_reg : gspr_index_t;
 386         exc_write_data : std_ulogic_vector(63 downto 0);
 387     end record;
 388     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 389                                                                    write_cr_enable => '0', exc_write_enable => '0',
 390                                                                    write_xerc_enable => '0', xerc => xerc_init,
 391                                    write_data => (others => '0'), write_cr_mask => (others => '0'),
 392                                    write_cr_data => (others => '0'), write_reg => (others => '0'),
 393                                    exc_write_reg => (others => '0'), exc_write_data => (others => '0'));
 394
 395     type DividerToExecute1Type is record
 396         valid: std_ulogic;
 397         write_reg_data: std_ulogic_vector(63 downto 0);
 398         overflow : std_ulogic;
 399     end record;
 400     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 401                                                                others => (others => '0'));
 402
 403     type WritebackToRegisterFileType is record
 404         write_reg : gspr_index_t;
 405         write_data : std_ulogic_vector(63 downto 0);
 406         write_enable : std_ulogic;
 407     end record;
 408     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_data => (others => '0'), others => (others => '0'));
 409
 410     type WritebackToCrFileType is record
 411         write_cr_enable : std_ulogic;
 412         write_cr_mask : std_ulogic_vector(7 downto 0);
 413         write_cr_data : std_ulogic_vector(31 downto 0);
 414         write_xerc_enable : std_ulogic;
 415         write_xerc_data : xer_common_t;
 416     end record;
 417     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 418                                                                write_xerc_data => xerc_init,
 419                                                                write_cr_mask => (others => '0'),
 420                                                                write_cr_data => (others => '0'));
 421
 422 end common;
 423
 424 package body common is
 425     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 426     begin
 427         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 428     end;
 429     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 430        variable n : integer range 0 to 31;
 431        -- tmp variable introduced as workaround for VCS compilation
 432        -- simulation was failing with subtype constraint mismatch error
 433        -- see GitHub PR #173
 434        variable tmp : std_ulogic_vector(4 downto 0);
 435     begin
 436        case spr is
 437        when SPR_LR =>
 438            n := 0;
 439        when SPR_CTR =>
 440            n:= 1;
 441        when SPR_SRR0 =>
 442            n := 2;
 443        when SPR_SRR1 =>
 444            n := 3;
 445        when SPR_HSRR0 =>
 446            n := 4;
 447        when SPR_HSRR1 =>
 448            n := 5;
 449        when SPR_SPRG0 =>
 450            n := 6;
 451        when SPR_SPRG1 =>
 452            n := 7;
 453        when SPR_SPRG2 =>
 454            n := 8;
 455        when SPR_SPRG3 | SPR_SPRG3U =>
 456            n := 9;
 457        when SPR_HSPRG0 =>
 458            n := 10;
 459        when SPR_HSPRG1 =>
 460            n := 11;
 461        when SPR_XER =>
 462            n := 12;
 463        when SPR_TAR =>
 464            n := 13;
 465        when others =>
 466            n := 0;
 467            return "000000";
 468        end case;
 469        tmp := std_ulogic_vector(to_unsigned(n, 5));
 470        return "1" & tmp;
 471     end;
 472
 473     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 474     begin
 475         return i(4 downto 0);
 476     end;
 477
 478     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 479     begin
 480         return "0" & i;
 481     end;
 482
 483     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 484     begin
 485         if s(5) = '1' then
 486             return s;
 487         else
 488             return gpr_to_gspr(g);
 489         end if;
 490     end;
 491
 492     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 493     begin
 494         return s(5);
 495     end;
 496 end common;