common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.decode_types.all;
   6
   7 package common is
   8         type ctrl_t is record
   9                 lr: std_ulogic_vector(63 downto 0);
  10                 ctr: std_ulogic_vector(63 downto 0);
  11                 tb: std_ulogic_vector(63 downto 0);
  12                 carry: std_ulogic;
  13         end record;
  14
  15         type Fetch1ToIcacheType is record
  16                 req: std_ulogic;
  17                 stop_mark: std_ulogic;
  18                 nia: std_ulogic_vector(63 downto 0);
  19         end record;
  20
  21         type IcacheToFetch2Type is record
  22                 valid: std_ulogic;
  23                 stop_mark: std_ulogic;
  24                 nia: std_ulogic_vector(63 downto 0);
  25                 insn: std_ulogic_vector(31 downto 0);
  26         end record;
  27
  28         type Fetch2ToDecode1Type is record
  29                 valid: std_ulogic;
  30                 stop_mark : std_ulogic;
  31                 nia: std_ulogic_vector(63 downto 0);
  32                 insn: std_ulogic_vector(31 downto 0);
  33         end record;
  34         constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', others => (others => '0'));
  35
  36         type Decode1ToDecode2Type is record
  37                 valid: std_ulogic;
  38                 stop_mark : std_ulogic;
  39                 nia: std_ulogic_vector(63 downto 0);
  40                 insn: std_ulogic_vector(31 downto 0);
  41                 decode: decode_rom_t;
  42         end record;
  43         constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
  44
  45         type Decode2ToExecute1Type is record
  46                 valid: std_ulogic;
  47                 insn_type: insn_type_t;
  48                 nia: std_ulogic_vector(63 downto 0);
  49                 write_reg: std_ulogic_vector(4 downto 0);
  50                 read_reg1: std_ulogic_vector(4 downto 0);
  51                 read_reg2: std_ulogic_vector(4 downto 0);
  52                 read_data1: std_ulogic_vector(63 downto 0);
  53                 read_data2: std_ulogic_vector(63 downto 0);
  54                 read_data3: std_ulogic_vector(63 downto 0);
  55                 cr: std_ulogic_vector(31 downto 0);
  56                 lr: std_ulogic;
  57                 rc: std_ulogic;
  58                 invert_a: std_ulogic;
  59                 input_carry: carry_in_t;
  60                 output_carry: std_ulogic;
  61                 input_cr: std_ulogic;
  62                 output_cr: std_ulogic;
  63                 is_32bit: std_ulogic;
  64                 is_signed: std_ulogic;
  65                 insn: std_ulogic_vector(31 downto 0);
  66         end record;
  67         constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
  68                 (valid => '0', insn_type => OP_ILLEGAL, lr => '0', rc => '0', invert_a => '0',
  69                  input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
  70                  is_32bit => '0', is_signed => '0', others => (others => '0'));
  71
  72         type Decode2ToMultiplyType is record
  73                 valid: std_ulogic;
  74                 insn_type: insn_type_t;
  75                 write_reg: std_ulogic_vector(4 downto 0);
  76                 data1: std_ulogic_vector(64 downto 0);
  77                 data2: std_ulogic_vector(64 downto 0);
  78                 rc: std_ulogic;
  79         end record;
  80         constant Decode2ToMultiplyInit : Decode2ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', others => (others => '0'));
  81
  82         type Decode2ToDividerType is record
  83                 valid: std_ulogic;
  84                 write_reg: std_ulogic_vector(4 downto 0);
  85                 dividend: std_ulogic_vector(63 downto 0);
  86                 divisor: std_ulogic_vector(63 downto 0);
  87                 is_signed: std_ulogic;
  88                 is_32bit: std_ulogic;
  89                 is_extended: std_ulogic;
  90                 is_modulus: std_ulogic;
  91                 rc: std_ulogic;
  92         end record;
  93         constant Decode2ToDividerInit: Decode2ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0', is_extended => '0', is_modulus => '0', rc => '0', others => (others => '0'));
  94
  95         type Decode2ToRegisterFileType is record
  96                 read1_enable : std_ulogic;
  97                 read1_reg : std_ulogic_vector(4 downto 0);
  98                 read2_enable : std_ulogic;
  99                 read2_reg : std_ulogic_vector(4 downto 0);
 100                 read3_enable : std_ulogic;
 101                 read3_reg : std_ulogic_vector(4 downto 0);
 102         end record;
 103
 104         type RegisterFileToDecode2Type is record
 105                 read1_data : std_ulogic_vector(63 downto 0);
 106                 read2_data : std_ulogic_vector(63 downto 0);
 107                 read3_data : std_ulogic_vector(63 downto 0);
 108         end record;
 109
 110         type Decode2ToCrFileType is record
 111                 read : std_ulogic;
 112         end record;
 113
 114         type CrFileToDecode2Type is record
 115                 read_cr_data   : std_ulogic_vector(31 downto 0);
 116         end record;
 117
 118         type Execute1ToFetch1Type is record
 119                 redirect: std_ulogic;
 120                 redirect_nia: std_ulogic_vector(63 downto 0);
 121         end record;
 122         constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
 123
 124         type Decode2ToLoadstore1Type is record
 125                 valid : std_ulogic;
 126                 load : std_ulogic;                              -- is this a load or store
 127                 addr1 : std_ulogic_vector(63 downto 0);
 128                 addr2 : std_ulogic_vector(63 downto 0);
 129                 data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 130                 write_reg : std_ulogic_vector(4 downto 0);      -- read data goes to this register
 131                 length : std_ulogic_vector(3 downto 0);
 132                 byte_reverse : std_ulogic;
 133                 sign_extend : std_ulogic;                       -- do we need to sign extend?
 134                 update : std_ulogic;                            -- is this an update instruction?
 135                 update_reg : std_ulogic_vector(4 downto 0);     -- if so, the register to update
 136         end record;
 137         constant Decode2ToLoadstore1Init : Decode2ToLoadstore1Type := (valid => '0', load => '0', byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
 138
 139         type Loadstore1ToLoadstore2Type is record
 140                 valid : std_ulogic;
 141                 load : std_ulogic;
 142                 addr : std_ulogic_vector(63 downto 0);
 143                 data : std_ulogic_vector(63 downto 0);
 144                 write_reg : std_ulogic_vector(4 downto 0);
 145                 length : std_ulogic_vector(3 downto 0);
 146                 byte_reverse : std_ulogic;
 147                 sign_extend : std_ulogic;
 148                 update : std_ulogic;
 149                 update_reg : std_ulogic_vector(4 downto 0);
 150         end record;
 151
 152         type Loadstore2ToWritebackType is record
 153                 valid : std_ulogic;
 154                 write_enable: std_ulogic;
 155                 write_reg : std_ulogic_vector(4 downto 0);
 156                 write_data : std_ulogic_vector(63 downto 0);
 157         end record;
 158         constant Loadstore2ToWritebackInit : Loadstore2ToWritebackType := (valid => '0', write_enable => '0', others => (others => '0'));
 159
 160         type Execute1ToExecute2Type is record
 161                 valid: std_ulogic;
 162                 write_enable : std_ulogic;
 163                 write_reg: std_ulogic_vector(4 downto 0);
 164                 write_data: std_ulogic_vector(63 downto 0);
 165                 write_cr_enable : std_ulogic;
 166                 write_cr_mask : std_ulogic_vector(7 downto 0);
 167                 write_cr_data : std_ulogic_vector(31 downto 0);
 168                 rc : std_ulogic;
 169         end record;
 170         constant Execute1ToExecute2Init : Execute1ToExecute2Type := (valid => '0', write_enable => '0', write_cr_enable => '0', rc => '0', others => (others => '0'));
 171
 172         type Execute2ToWritebackType is record
 173                 valid: std_ulogic;
 174                 write_enable : std_ulogic;
 175                 write_reg: std_ulogic_vector(4 downto 0);
 176                 write_data: std_ulogic_vector(63 downto 0);
 177                 write_cr_enable : std_ulogic;
 178                 write_cr_mask : std_ulogic_vector(7 downto 0);
 179                 write_cr_data : std_ulogic_vector(31 downto 0);
 180         end record;
 181         constant Execute2ToWritebackInit : Execute2ToWritebackType := (valid => '0', write_enable => '0', write_cr_enable => '0', others => (others => '0'));
 182
 183         type MultiplyToWritebackType is record
 184                 valid: std_ulogic;
 185
 186                 write_reg_enable : std_ulogic;
 187                 write_reg_nr: std_ulogic_vector(4 downto 0);
 188                 write_reg_data: std_ulogic_vector(63 downto 0);
 189                 write_cr_enable: std_ulogic;
 190                 write_cr_mask: std_ulogic_vector(7 downto 0);
 191                 write_cr_data: std_ulogic_vector(31 downto 0);
 192         end record;
 193         constant MultiplyToWritebackInit : MultiplyToWritebackType := (valid => '0', write_reg_enable => '0', write_cr_enable => '0', others => (others => '0'));
 194
 195         type DividerToWritebackType is record
 196                 valid: std_ulogic;
 197
 198                 write_reg_enable : std_ulogic;
 199                 write_reg_nr: std_ulogic_vector(4 downto 0);
 200                 write_reg_data: std_ulogic_vector(63 downto 0);
 201                 write_cr_enable: std_ulogic;
 202                 write_cr_mask: std_ulogic_vector(7 downto 0);
 203                 write_cr_data: std_ulogic_vector(31 downto 0);
 204         end record;
 205         constant DividerToWritebackInit : DividerToWritebackType := (valid => '0', write_reg_enable => '0', write_cr_enable => '0', others => (others => '0'));
 206
 207         type WritebackToRegisterFileType is record
 208                 write_reg : std_ulogic_vector(4 downto 0);
 209                 write_data : std_ulogic_vector(63 downto 0);
 210                 write_enable : std_ulogic;
 211         end record;
 212         constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
 213
 214         type WritebackToCrFileType is record
 215                 write_cr_enable : std_ulogic;
 216                 write_cr_mask : std_ulogic_vector(7 downto 0);
 217                 write_cr_data : std_ulogic_vector(31 downto 0);
 218         end record;
 219         constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', others => (others => '0'));
 220 end common;
 221
 222 package body common is
 223 end common;