common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3 use ieee.numeric_std.all;
   4
   5 library work;
   6 use work.decode_types.all;
   7
   8 package common is
   9
  10     -- SPR numbers
  11     subtype spr_num_t is integer range 0 to 1023;
  12
  13     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t;
  14
  15     constant SPR_XER    : spr_num_t := 1;
  16     constant SPR_LR     : spr_num_t := 8;
  17     constant SPR_CTR    : spr_num_t := 9;
  18     constant SPR_TB     : spr_num_t := 268;
  19     constant SPR_SRR0   : spr_num_t := 26;
  20     constant SPR_SRR1   : spr_num_t := 27;
  21     constant SPR_HSRR0  : spr_num_t := 314;
  22     constant SPR_HSRR1  : spr_num_t := 315;
  23     constant SPR_SPRG0  : spr_num_t := 272;
  24     constant SPR_SPRG1  : spr_num_t := 273;
  25     constant SPR_SPRG2  : spr_num_t := 274;
  26     constant SPR_SPRG3  : spr_num_t := 275;
  27     constant SPR_SPRG3U : spr_num_t := 259;
  28     constant SPR_HSPRG0 : spr_num_t := 304;
  29     constant SPR_HSPRG1 : spr_num_t := 305;
  30
  31     -- GPR indices in the register file (GPR only)
  32     subtype gpr_index_t is std_ulogic_vector(4 downto 0);
  33
  34     -- Extended GPR indice (can hold an SPR)
  35     subtype gspr_index_t is std_ulogic_vector(5 downto 0);
  36
  37     -- Some SPRs are stored in the register file, they use the magic
  38     -- GPR numbers above 31.
  39     --
  40     -- The function fast_spr_num() returns the corresponding fast
  41     -- pseudo-GPR number for a given SPR number. The result MSB
  42     -- indicates if this is indeed a fast SPR. If clear, then
  43     -- the SPR is not stored in the GPR file.
  44     --
  45     function fast_spr_num(spr: spr_num_t) return gspr_index_t;
  46
  47     -- Indices conversion functions
  48     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t;
  49     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t;
  50     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t;
  51     function is_fast_spr(s: gspr_index_t) return std_ulogic;
  52
  53     -- The XER is split: the common bits (CA, OV, SO, OV32 and CA32) are
  54     -- in the CR file as a kind of CR extension (with a separate write
  55     -- control). The rest is stored as a fast SPR.
  56     type xer_common_t is record
  57         ca : std_ulogic;
  58         ca32 : std_ulogic;
  59         ov : std_ulogic;
  60         ov32 : std_ulogic;
  61         so : std_ulogic;
  62     end record;
  63     constant xerc_init : xer_common_t := (others => '0');
  64
  65     -- This needs to die...
  66     type ctrl_t is record
  67         tb: std_ulogic_vector(63 downto 0);
  68     end record;
  69
  70     type Fetch1ToIcacheType is record
  71         req: std_ulogic;
  72         stop_mark: std_ulogic;
  73         nia: std_ulogic_vector(63 downto 0);
  74     end record;
  75
  76     type IcacheToFetch2Type is record
  77         valid: std_ulogic;
  78         stop_mark: std_ulogic;
  79         nia: std_ulogic_vector(63 downto 0);
  80         insn: std_ulogic_vector(31 downto 0);
  81     end record;
  82
  83     type Fetch2ToDecode1Type is record
  84         valid: std_ulogic;
  85         stop_mark : std_ulogic;
  86         nia: std_ulogic_vector(63 downto 0);
  87         insn: std_ulogic_vector(31 downto 0);
  88     end record;
  89     constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', stop_mark => '0', others => (others => '0'));
  90
  91     type Decode1ToDecode2Type is record
  92         valid: std_ulogic;
  93         stop_mark : std_ulogic;
  94         nia: std_ulogic_vector(63 downto 0);
  95         insn: std_ulogic_vector(31 downto 0);
  96         ispr1: gspr_index_t; -- (G)SPR used for branch condition (CTR) or mfspr
  97         ispr2: gspr_index_t; -- (G)SPR used for branch target (CTR, LR, TAR)
  98         decode: decode_rom_t;
  99     end record;
 100     constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', stop_mark => '0', decode => decode_rom_init, others => (others => '0'));
 101
 102     type Decode2ToExecute1Type is record
 103         valid: std_ulogic;
 104         insn_type: insn_type_t;
 105         nia: std_ulogic_vector(63 downto 0);
 106         write_reg: gspr_index_t;
 107         read_reg1: gspr_index_t;
 108         read_reg2: gspr_index_t;
 109         read_data1: std_ulogic_vector(63 downto 0);
 110         read_data2: std_ulogic_vector(63 downto 0);
 111         read_data3: std_ulogic_vector(63 downto 0);
 112         bypass_data1: std_ulogic;
 113         bypass_data2: std_ulogic;
 114         bypass_data3: std_ulogic;
 115         cr: std_ulogic_vector(31 downto 0);
 116         xerc: xer_common_t;
 117         lr: std_ulogic;
 118         rc: std_ulogic;
 119         oe: std_ulogic;
 120         invert_a: std_ulogic;
 121         invert_out: std_ulogic;
 122         input_carry: carry_in_t;
 123         output_carry: std_ulogic;
 124         input_cr: std_ulogic;
 125         output_cr: std_ulogic;
 126         is_32bit: std_ulogic;
 127         is_signed: std_ulogic;
 128         insn: std_ulogic_vector(31 downto 0);
 129         data_len: std_ulogic_vector(3 downto 0);
 130         byte_reverse : std_ulogic;
 131         sign_extend : std_ulogic;                       -- do we need to sign extend?
 132         update : std_ulogic;                            -- is this an update instruction?
 133         reserve : std_ulogic;                           -- set for larx/stcx
 134     end record;
 135     constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
 136         (valid => '0', insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
 137          lr => '0', rc => '0', oe => '0', invert_a => '0',
 138          invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
 139          is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0',
 140          byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
 141
 142     type Execute1ToMultiplyType is record
 143         valid: std_ulogic;
 144         insn_type: insn_type_t;
 145         data1: std_ulogic_vector(64 downto 0);
 146         data2: std_ulogic_vector(64 downto 0);
 147         is_32bit: std_ulogic;
 148     end record;
 149     constant Execute1ToMultiplyInit : Execute1ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL,
 150                                                                  is_32bit => '0',
 151                                                                  others => (others => '0'));
 152
 153     type Execute1ToDividerType is record
 154         valid: std_ulogic;
 155         dividend: std_ulogic_vector(63 downto 0);
 156         divisor: std_ulogic_vector(63 downto 0);
 157         is_signed: std_ulogic;
 158         is_32bit: std_ulogic;
 159         is_extended: std_ulogic;
 160         is_modulus: std_ulogic;
 161         neg_result: std_ulogic;
 162     end record;
 163     constant Execute1ToDividerInit: Execute1ToDividerType := (valid => '0', is_signed => '0', is_32bit => '0',
 164                                                               is_extended => '0', is_modulus => '0',
 165                                                               neg_result => '0', others => (others => '0'));
 166
 167     type Decode2ToRegisterFileType is record
 168         read1_enable : std_ulogic;
 169         read1_reg : gspr_index_t;
 170         read2_enable : std_ulogic;
 171         read2_reg : gspr_index_t;
 172         read3_enable : std_ulogic;
 173         read3_reg : gpr_index_t;
 174     end record;
 175
 176     type RegisterFileToDecode2Type is record
 177         read1_data : std_ulogic_vector(63 downto 0);
 178         read2_data : std_ulogic_vector(63 downto 0);
 179         read3_data : std_ulogic_vector(63 downto 0);
 180     end record;
 181
 182     type Decode2ToCrFileType is record
 183         read : std_ulogic;
 184     end record;
 185
 186     type CrFileToDecode2Type is record
 187         read_cr_data   : std_ulogic_vector(31 downto 0);
 188         read_xerc_data : xer_common_t;
 189     end record;
 190
 191     type Execute1ToFetch1Type is record
 192         redirect: std_ulogic;
 193         redirect_nia: std_ulogic_vector(63 downto 0);
 194     end record;
 195     constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
 196
 197     type Execute1ToLoadstore1Type is record
 198         valid : std_ulogic;
 199         load : std_ulogic;                              -- is this a load or store
 200         addr1 : std_ulogic_vector(63 downto 0);
 201         addr2 : std_ulogic_vector(63 downto 0);
 202         data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 203         write_reg : gpr_index_t;
 204         length : std_ulogic_vector(3 downto 0);
 205         ci : std_ulogic;                                -- cache-inhibited load/store
 206         byte_reverse : std_ulogic;
 207         sign_extend : std_ulogic;                       -- do we need to sign extend?
 208         update : std_ulogic;                            -- is this an update instruction?
 209         update_reg : gpr_index_t;                       -- if so, the register to update
 210         xerc : xer_common_t;
 211         reserve : std_ulogic;                           -- set for larx/stcx.
 212         rc : std_ulogic;                                -- set for stcx.
 213     end record;
 214     constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', load => '0', ci => '0', byte_reverse => '0',
 215                                                                      sign_extend => '0', update => '0', xerc => xerc_init,
 216                                                                      reserve => '0', rc => '0', others => (others => '0'));
 217
 218     type Loadstore1ToDcacheType is record
 219         valid : std_ulogic;
 220         load : std_ulogic;
 221         nc : std_ulogic;
 222         reserve : std_ulogic;
 223         addr : std_ulogic_vector(63 downto 0);
 224         data : std_ulogic_vector(63 downto 0);
 225         byte_sel : std_ulogic_vector(7 downto 0);
 226     end record;
 227
 228     type DcacheToLoadstore1Type is record
 229         valid : std_ulogic;
 230         data : std_ulogic_vector(63 downto 0);
 231         store_done : std_ulogic;
 232         error : std_ulogic;
 233     end record;
 234
 235     type Loadstore1ToWritebackType is record
 236         valid : std_ulogic;
 237         write_enable: std_ulogic;
 238         write_reg : gpr_index_t;
 239         write_data : std_ulogic_vector(63 downto 0);
 240         xerc : xer_common_t;
 241         rc : std_ulogic;
 242         store_done : std_ulogic;
 243     end record;
 244     constant Loadstore1ToWritebackInit : Loadstore1ToWritebackType := (valid => '0', write_enable => '0', xerc => xerc_init,
 245                                                                        rc => '0', store_done => '0', others => (others => '0'));
 246
 247     type Execute1ToWritebackType is record
 248         valid: std_ulogic;
 249         rc : std_ulogic;
 250         write_enable : std_ulogic;
 251         write_reg: gspr_index_t;
 252         write_data: std_ulogic_vector(63 downto 0);
 253         write_cr_enable : std_ulogic;
 254         write_cr_mask : std_ulogic_vector(7 downto 0);
 255         write_cr_data : std_ulogic_vector(31 downto 0);
 256         write_xerc_enable : std_ulogic;
 257         xerc : xer_common_t;
 258     end record;
 259     constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
 260                                                                    write_cr_enable => '0',
 261                                                                    write_xerc_enable => '0', xerc => xerc_init,
 262                                                                    others => (others => '0'));
 263
 264     type MultiplyToExecute1Type is record
 265         valid: std_ulogic;
 266         write_reg_data: std_ulogic_vector(63 downto 0);
 267         overflow : std_ulogic;
 268     end record;
 269     constant MultiplyToExecute1Init : MultiplyToExecute1Type := (valid => '0', overflow => '0',
 270                                                                  others => (others => '0'));
 271
 272     type DividerToExecute1Type is record
 273         valid: std_ulogic;
 274         write_reg_data: std_ulogic_vector(63 downto 0);
 275         overflow : std_ulogic;
 276     end record;
 277     constant DividerToExecute1Init : DividerToExecute1Type := (valid => '0', overflow => '0',
 278                                                                others => (others => '0'));
 279
 280     type WritebackToRegisterFileType is record
 281         write_reg : gspr_index_t;
 282         write_data : std_ulogic_vector(63 downto 0);
 283         write_enable : std_ulogic;
 284     end record;
 285     constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', others => (others => '0'));
 286
 287     type WritebackToCrFileType is record
 288         write_cr_enable : std_ulogic;
 289         write_cr_mask : std_ulogic_vector(7 downto 0);
 290         write_cr_data : std_ulogic_vector(31 downto 0);
 291         write_xerc_enable : std_ulogic;
 292         write_xerc_data : xer_common_t;
 293     end record;
 294     constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', write_xerc_enable => '0',
 295                                                                write_xerc_data => xerc_init,
 296                                                                others => (others => '0'));
 297 end common;
 298
 299 package body common is
 300     function decode_spr_num(insn: std_ulogic_vector(31 downto 0)) return spr_num_t is
 301     begin
 302         return to_integer(unsigned(insn(15 downto 11) & insn(20 downto 16)));
 303     end;
 304     function fast_spr_num(spr: spr_num_t) return gspr_index_t is
 305        variable n : integer range 0 to 31;
 306     begin
 307        case spr is
 308        when SPR_LR =>
 309            n := 0;
 310        when SPR_CTR =>
 311            n:= 1;
 312        when SPR_SRR0 =>
 313            n := 2;
 314        when SPR_SRR1 =>
 315            n := 3;
 316        when SPR_HSRR0 =>
 317            n := 4;
 318        when SPR_HSRR1 =>
 319            n := 5;
 320        when SPR_SPRG0 =>
 321            n := 6;
 322        when SPR_SPRG1 =>
 323            n := 7;
 324        when SPR_SPRG2 =>
 325            n := 8;
 326        when SPR_SPRG3 | SPR_SPRG3U =>
 327            n := 9;
 328        when SPR_HSPRG0 =>
 329            n := 10;
 330        when SPR_HSPRG1 =>
 331            n := 11;
 332        when SPR_XER =>
 333            n := 12;
 334        when others =>
 335            n := 0;
 336            return "000000";
 337        end case;
 338        return "1" & std_ulogic_vector(to_unsigned(n, 5));
 339     end;
 340
 341     function gspr_to_gpr(i: gspr_index_t) return gpr_index_t is
 342     begin
 343         return i(4 downto 0);
 344     end;
 345
 346     function gpr_to_gspr(i: gpr_index_t) return gspr_index_t is
 347     begin
 348         return "0" & i;
 349     end;
 350
 351     function gpr_or_spr_to_gspr(g: gpr_index_t; s: gspr_index_t) return gspr_index_t is
 352     begin
 353         if s(5) = '1' then
 354             return s;
 355         else
 356             return gpr_to_gspr(g);
 357         end if;
 358     end;
 359
 360     function is_fast_spr(s: gspr_index_t) return std_ulogic is
 361     begin
 362         return s(5);
 363     end;
 364 end common;