common.vhdl

   1 library ieee;
   2 use ieee.std_logic_1164.all;
   3
   4 library work;
   5 use work.decode_types.all;
   6
   7 package common is
   8         type ctrl_t is record
   9                 lr: std_ulogic_vector(63 downto 0);
  10                 ctr: std_ulogic_vector(63 downto 0);
  11                 tb: std_ulogic_vector(63 downto 0);
  12                 carry: std_ulogic;
  13         end record;
  14
  15         type Fetch1ToFetch2Type is record
  16                 valid: std_ulogic;
  17                 nia: std_ulogic_vector(63 downto 0);
  18         end record;
  19
  20         type Fetch2ToDecode1Type is record
  21                 valid: std_ulogic;
  22                 nia: std_ulogic_vector(63 downto 0);
  23                 insn: std_ulogic_vector(31 downto 0);
  24         end record;
  25         constant Fetch2ToDecode1Init : Fetch2ToDecode1Type := (valid => '0', others => (others => '0'));
  26
  27         type Decode1ToDecode2Type is record
  28                 valid: std_ulogic;
  29                 nia: std_ulogic_vector(63 downto 0);
  30                 insn: std_ulogic_vector(31 downto 0);
  31                 decode: decode_rom_t;
  32         end record;
  33         constant Decode1ToDecode2Init : Decode1ToDecode2Type := (valid => '0', decode => decode_rom_init, others => (others => '0'));
  34
  35         type Decode2ToExecute1Type is record
  36                 valid: std_ulogic;
  37                 insn_type: insn_type_t;
  38                 nia: std_ulogic_vector(63 downto 0);
  39                 write_reg: std_ulogic_vector(4 downto 0);
  40                 read_reg1: std_ulogic_vector(4 downto 0);
  41                 read_reg2: std_ulogic_vector(4 downto 0);
  42                 read_data1: std_ulogic_vector(63 downto 0);
  43                 read_data2: std_ulogic_vector(63 downto 0);
  44                 const1: std_ulogic_vector(7 downto 0);
  45                 const2: std_ulogic_vector(5 downto 0);
  46                 const3: std_ulogic_vector(4 downto 0);
  47                 cr: std_ulogic_vector(31 downto 0);
  48                 lr: std_ulogic;
  49                 rc: std_ulogic;
  50                 input_carry: std_ulogic;
  51                 output_carry: std_ulogic;
  52                 input_cr: std_ulogic;
  53                 output_cr: std_ulogic;
  54                 input_cr_data: std_ulogic_vector(31 downto 0);
  55         end record;
  56         constant Decode2ToExecute1Init : Decode2ToExecute1Type := (valid => '0', insn_type => OP_ILLEGAL, lr => '0', rc => '0', input_carry => '0', output_carry => '0', input_cr => '0', output_cr => '0', others => (others => '0'));
  57
  58         type Decode2ToMultiplyType is record
  59                 valid: std_ulogic;
  60                 insn_type: insn_type_t;
  61                 nia: std_ulogic_vector(63 downto 0);
  62                 write_reg: std_ulogic_vector(4 downto 0);
  63                 data1: std_ulogic_vector(64 downto 0);
  64                 data2: std_ulogic_vector(64 downto 0);
  65                 rc: std_ulogic;
  66         end record;
  67         constant Decode2ToMultiplyInit : Decode2ToMultiplyType := (valid => '0', insn_type => OP_ILLEGAL, rc => '0', others => (others => '0'));
  68
  69         type Decode2ToRegisterFileType is record
  70                 read1_reg : std_ulogic_vector(4 downto 0);
  71                 read2_reg : std_ulogic_vector(4 downto 0);
  72                 read3_reg : std_ulogic_vector(4 downto 0);
  73         end record;
  74
  75         type RegisterFileToDecode2Type is record
  76                 read1_data : std_ulogic_vector(63 downto 0);
  77                 read2_data : std_ulogic_vector(63 downto 0);
  78                 read3_data : std_ulogic_vector(63 downto 0);
  79         end record;
  80
  81         type Decode2ToCrFileType is record
  82                 read : std_ulogic;
  83         end record;
  84
  85         type CrFileToDecode2Type is record
  86                 read_cr_data   : std_ulogic_vector(31 downto 0);
  87         end record;
  88
  89         type Execute1ToFetch1Type is record
  90                 redirect: std_ulogic;
  91                 redirect_nia: std_ulogic_vector(63 downto 0);
  92         end record;
  93         constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', others => (others => '0'));
  94
  95         type Decode2ToLoadstore1Type is record
  96                 valid : std_ulogic;
  97                 nia: std_ulogic_vector(63 downto 0);
  98                 load : std_ulogic;                              -- is this a load or store
  99                 addr1 : std_ulogic_vector(63 downto 0);
 100                 addr2 : std_ulogic_vector(63 downto 0);
 101                 data : std_ulogic_vector(63 downto 0);          -- data to write, unused for read
 102                 write_reg : std_ulogic_vector(4 downto 0);      -- read data goes to this register
 103                 length : std_ulogic_vector(3 downto 0);
 104                 byte_reverse : std_ulogic;
 105                 sign_extend : std_ulogic;                       -- do we need to sign extend?
 106                 update : std_ulogic;                            -- is this an update instruction?
 107                 update_reg : std_ulogic_vector(4 downto 0);     -- if so, the register to update
 108         end record;
 109         constant Decode2ToLoadstore1Init : Decode2ToLoadstore1Type := (valid => '0', load => '0', byte_reverse => '0', sign_extend => '0', update => '0', others => (others => '0'));
 110
 111         type Loadstore1ToLoadstore2Type is record
 112                 valid : std_ulogic;
 113                 load : std_ulogic;
 114                 addr : std_ulogic_vector(63 downto 0);
 115                 data : std_ulogic_vector(63 downto 0);
 116                 write_reg : std_ulogic_vector(4 downto 0);
 117                 length : std_ulogic_vector(3 downto 0);
 118                 byte_reverse : std_ulogic;
 119                 sign_extend : std_ulogic;
 120                 update : std_ulogic;
 121                 update_reg : std_ulogic_vector(4 downto 0);
 122         end record;
 123
 124         type Loadstore2ToWritebackType is record
 125                 valid : std_ulogic;
 126                 write_enable: std_ulogic;
 127                 write_reg : std_ulogic_vector(4 downto 0);
 128                 write_data : std_ulogic_vector(63 downto 0);
 129                 write_enable2: std_ulogic;
 130                 write_reg2 : std_ulogic_vector(4 downto 0);
 131                 write_data2 : std_ulogic_vector(63 downto 0);
 132         end record;
 133         constant Loadstore2ToWritebackInit : Loadstore2ToWritebackType := (valid => '0', write_enable => '0', write_enable2 => '0', others => (others => '0'));
 134
 135         type Execute1ToExecute2Type is record
 136                 valid: std_ulogic;
 137                 write_enable : std_ulogic;
 138                 write_reg: std_ulogic_vector(4 downto 0);
 139                 write_data: std_ulogic_vector(63 downto 0);
 140                 write_cr_enable : std_ulogic;
 141                 write_cr_mask : std_ulogic_vector(7 downto 0);
 142                 write_cr_data : std_ulogic_vector(31 downto 0);
 143                 rc : std_ulogic;
 144         end record;
 145         constant Execute1ToExecute2Init : Execute1ToExecute2Type := (valid => '0', write_enable => '0', write_cr_enable => '0', rc => '0', others => (others => '0'));
 146
 147         type Execute2ToWritebackType is record
 148                 valid: std_ulogic;
 149                 write_enable : std_ulogic;
 150                 write_reg: std_ulogic_vector(4 downto 0);
 151                 write_data: std_ulogic_vector(63 downto 0);
 152                 write_cr_enable : std_ulogic;
 153                 write_cr_mask : std_ulogic_vector(7 downto 0);
 154                 write_cr_data : std_ulogic_vector(31 downto 0);
 155         end record;
 156         constant Execute2ToWritebackInit : Execute2ToWritebackType := (valid => '0', write_enable => '0', write_cr_enable => '0', others => (others => '0'));
 157
 158         type MultiplyToWritebackType is record
 159                 valid: std_ulogic;
 160
 161                 write_reg_enable : std_ulogic;
 162                 write_reg_nr: std_ulogic_vector(4 downto 0);
 163                 write_reg_data: std_ulogic_vector(63 downto 0);
 164                 write_cr_enable: std_ulogic;
 165                 write_cr_mask: std_ulogic_vector(7 downto 0);
 166                 write_cr_data: std_ulogic_vector(31 downto 0);
 167         end record;
 168         constant MultiplyToWritebackInit : MultiplyToWritebackType := (valid => '0', write_reg_enable => '0', write_cr_enable => '0', others => (others => '0'));
 169
 170         type WritebackToRegisterFileType is record
 171                 write_reg : std_ulogic_vector(4 downto 0);
 172                 write_data : std_ulogic_vector(63 downto 0);
 173                 write_enable : std_ulogic;
 174                 write_reg2 : std_ulogic_vector(4 downto 0);
 175                 write_data2 : std_ulogic_vector(63 downto 0);
 176                 write_enable2 : std_ulogic;
 177         end record;
 178         constant WritebackToRegisterFileInit : WritebackToRegisterFileType := (write_enable => '0', write_enable2 => '0', others => (others => '0'));
 179
 180         type WritebackToCrFileType is record
 181                 write_cr_enable : std_ulogic;
 182                 write_cr_mask : std_ulogic_vector(7 downto 0);
 183                 write_cr_data : std_ulogic_vector(31 downto 0);
 184         end record;
 185         constant WritebackToCrFileInit : WritebackToCrFileType := (write_cr_enable => '0', others => (others => '0'));
 186
 187         -- Would prefer not to expose this outside the register file, but ghdl
 188         -- doesn't support external names
 189         type regfile is array(0 to 32) of std_ulogic_vector(63 downto 0);
 190 end common;
 191
 192 package body common is
 193 end common;