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[libreriscv.git] / conferences / fosdem2022.mdwn
1 # FOSDEM 2022
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3 # OpenHardware Dev Room
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5 TODO:
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7 * write to openhardware dev room mailing list (private archives)
8 - DONE 13nov2022. no response. assume dead list
9 - therefore take responsibility for writing proposal
10 * write proposal
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12 ## OHW Devroom Proposal
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14 <https://submission.fosdem.org/submission/devroom>
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16 Title: **Libre/Open Hardware CAD, Modelling and VLSI Dev Room**
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18 Elaborate description (including possible topics)
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20 - Open Hardware projects
21 - VLSI (ASIC Design)
22 * Open EDA and VLSI tools and toolflow
23 * Libre/Open VLSI Cell Libraries
24 * VLSI Simulation and Verification
25 - Circuit Design
26 * Printed circuit board design tools
27 * Circuit simulation
28 - 3d modeling and analysis
29 * Solid modeling tools
30 * Meshing, modeling and transforming physical representations
31 * Finite element analysis
32 - 3d printing
33 * 3d slicing tools
34 * Motor control
35 - Machine design and integration
36 * ECAD/MCAD integration
37 * Thermal analysis
38 * Wire modeling
39 - Physical Model Data storage
40 * Data representation and optimization
41 * Version control in hardware data storage
42 * Collaborative and team-based hardware design techniques
43 * Building information Modelling
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45 Why does it fit FOSDEM
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47 There has been a lot of changes happening in the last few years regarding chiptechnology. From RISC-V to attempts to create libre/free processes to make your own chips. Various countries have been catching up and helping and building up their semiconducter industries, some even pushing libre/free toolchains.
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49 Meanwhile others push the boundaries to liberate former closed source toolchains for FPGAs. While an often neglected topic, a lot of work happens by various fantastic players all around the world. We hope to bring some attention to this areas which we basicly all too often take as a given when using computers.
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51 Preferred slot: Full Day