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[libreriscv.git] / conferences / fosdem2022.mdwn
1 # FOSDEM 2022
2
3 # Libre/Open VLSI and FPGA Hardware, Simulation and Verification Dev Room
4
5 TODO:
6
7 * write to openhardware dev room mailing list (private archives)
8 - 13nov2022. no response. assume dead list DONE
9 - therefore take responsibility for writing proposal DONE
10 * write proposal DONE 14nov2022
11 * submit proposal DONE 14no42022
12 * CfP TODO
13 * Talk to devroom managers ONGOING
14 * contact interested people
15 - https://www.crowdsupply.com/great-scott-gadgets/luna (ktemkin)
16 - danielgrosse https://twitter.com/daniel_grosse
17 - Ganesen Narayanasamy, IBM India, Education Course
18 - openwifi <https://github.com/open-sdr/openwifi/issues/99>
19 - libresilicon (actual DIY Foundry equipment)
20 - opentapeoutdev
21 - openlane / openroad
22 - Staf (Chips4Makers)
23 - efabless
24 - libre-soc
25 - LIP6 / CNRS (coriolis2)
26 - apertus <https://www.apertus.org/axiom-ecosystem>
27 - NLnet (to help with outreach)
28 - Crowdsupply (ditto)
29 - KiCAD and other EDA tools
30 - LibreEDA developer (tkramer)
31 - Pine64 <https://wiki.pine64.org/wiki/PineNote>
32 - Bunnie, xobs (https://www.bunniestudios.com/)
33 - Tim Ansell/clifford wolf symbiflow et al https://symbiflow.github.io
34 - Libera.Chat channels:
35 - yosys DONE 29nov2021
36 - opentapeoutdev DONE 29nov2021
37 - symbiflow DONE 29nov2021
38 - openpower DONE 29nov2021
39 - Twitter channels
40 - <https://twitter.com/lkcl/status/1465290569681457157>
41 @Daniel_Grosse @GanesanBlue
42 @TLLim888
43
44 @thepine64
45
46 @Chips4Makers
47
48 @bunniestudios
49
50 @librecores
51
52 @efabless
53
54 ## OHW Devroom Proposal
55
56 <https://submission.fosdem.org/submission/devroom>
57
58 Title: **Libre/Open Hardware, CAD, Modelling and VLSI Dev Room**
59
60 Changed Title: **Libre/Open VLSI and FPGA Hardware, Simulation and Verification Dev Room**
61
62 **Updated** Elaborate description (including possible topics)
63
64 - Open Hardware projects
65 - VLSI ASIC Design and Manufacture
66 * Libre/Open DIY Foundries (nanoscale 3D printing)
67 * Libre/Open VLSI tools and toolflow
68 * Libre/Open VLSI Cell Libraries
69 * VLSI Simulation and Verification
70 - FPGAs
71 * Libre/Open FPGA designs
72 * FPGA toolchains and Reverse-Engineering
73 * FPGA workflow
74 - VLSI RTL and HDL
75 * Advanced and innovative alternative HDL tools
76 * Formal Correctness Proofs
77 * Testing methodologies
78 * Hardware Trust (and how to break it)
79 - Circuit Design (EDA)
80 * Printed circuit board design tools
81 * Analog/Digital Circuit simulation
82 - Software Engineering as applied to Hardware
83 * Continuous Integration for VLSI
84 * Automated tool development (RTL to GDS-II)
85 * Automated testing
86
87 Why does it fit FOSDEM
88
89 There has been a lot of progress happening in the last few years regarding
90 libre/free chip technology. From RISC-V and OpenPOWER to attempts to create
91 libre/free processes to make your own chips. Various countries have been
92 catching up and helping and building up their semiconductorr industries,
93 some even pushing libre/free toolchains. E.g. EU sponsors various projects
94 to work in this field to create open toolchains.
95
96 Meanwhile others push the boundaries to liberate former closed source toolchains for FPGAs. While an often neglected topic, a lot of work happens by various fantastic players all around the world. We hope to bring some attention to these areas which we basicly all too often take as a given when
97 using computers or electronics.
98 We therefore hope to give Open Hardware and their respective toolchains a
99 small platform, all the way from silicon to PCB.
100
101 Note to organisers: we don't mind merging with another devroom (then
102 helping out), as long as the words "Libre/Open Hardware" are included in
103 the devroom title, and the VLSI and FPGA topics are included. NLnet
104 now sponsors dozens of hardware projects alone, and the google skywater
105 130nm project with e-fabless has produced a massive new innovative
106 community that simply did not exist last year. We are also happy for
107 other (smaller) devrooms to merge with this one.
108
109 Preferred slot: Full Day
110
111 # Call for Papers<a name="cfp" />
112
113 This is a new devroom dedicated to Libre/Open VLSI, aka "Nanoscale 3D
114 Printing".
115
116 ### What is FOSDEM?
117
118 ~~Stolen~~/Borrowed from the website:
119
120 _**FOSDEM is a free event for software developers to meet, share ideas and collaborate.**
121 Every year, thousands of developers of free and open source software from all over the world gather at the event in Brussels.
122 ...
123 FOSDEM 2022 will take place on Saturday 5 and Sunday 6 February 2022. It will be an online event._
124
125 ### Important stuff:
126 - FOSDEM is free to attend. There is no registration.
127 - [FOSDEM website](https://fosdem.org/)
128 - [FOSDEM code of conduct](https://fosdem.org/2022/practical/conduct/)
129 - [FOSDEM Schedule](https://fosdem.org/2022/schedule/)
130
131 ### Desirable topics:
132
133 This devroom welcomes anything related to the topic of nanoscale
134 3D printing - more commonly known as "VLSI ASIC design". If you
135 are making an ASIC, or designing one, or using FPGAs, or developing
136 an FPGA Board, or developing tools and techniques that make VLSI ASIC
137 design easier, we'd love to hear from you. Here's a list of topics:
138
139 - Open Hardware projects
140 - VLSI ASIC Design and Manufacture
141 * Libre/Open DIY Foundries (nanoscale 3D printing)
142 * Libre/Open VLSI tools and toolflow
143 * Libre/Open VLSI Cell Libraries
144 * VLSI Simulation and Verification
145 - VLSI Tools in use or in development
146 * Silicon-proven (QFlow, coriolis2, OpenLANE)
147 * Under development (LibreEDA, other)
148 * Advances in Algorithmics in Place and Route and Layout
149 - FPGAs
150 * Libre/Open FPGA designs
151 * FPGA toolchains and Reverse-Engineering
152 * FPGA workflow
153 - VLSI RTL and HDL
154 * Advanced and innovative alternative HDL tools
155 * Formal Correctness Proofs
156 * Testing methodologies
157 * Hardware Trust (and how to break it)
158 - Circuit Design (EDA)
159 * Printed circuit board design tools
160 * Analog/Digital Circuit simulation
161 - Software Engineering as applied to Hardware
162 * Continuous Integration for VLSI
163 * Automated tool development (RTL to GDS-II)
164 * Automated testing
165
166 ### Topic overlap
167
168 There is quite a lot of overlap this year with:
169
170 * [CAD devroom]( https://fosdem.org/2022/schedule/track/open_source_computer_aided_modeling_and_design/),
171 * [Emulator devroom](https://fosdem.org/2022/schedule/track/emulator_development/)
172 * [Retro room](https://fosdem.org/2022/schedule/track/retrocomputing/)
173
174 It is entirely up to you as a speaker which devroom you choose: the
175 main reason for a new VLSI devroom this year is because it is a rapidly
176 expanding area formerly entirely NDA'd.
177
178 ### How to submit your proposal
179
180 To submit a talk, please visit the [FOSDEM 2022 Pentabarf website](https://penta.fosdem.org/submission/FOSDEM22) (the mystery of whether pentabarf means barfing in 5 directions or in 5 colors has not been solved yet).
181
182 Create an **event** and click on **Show all** in the top right corner to display the full form.
183
184 ### What should be in your submission
185
186 - name
187 - short bio
188 - contact info
189 - title (funny titles are ~~required~~/appreciated)
190 - abstract (what you're going talk about)
191 - duration
192
193 ### Important Dates
194
195 - **December 28th: submission deadline**
196 - FAQ - is the submission deadline final?
197 - Technically speaking, you can submit talks till pentabarf
198 closes, which should be somewhere in January
199 - However, talks submitted before the 29th get a higher precedence
200 - ASAP: announcement selected talks
201 - January: speakers are contacted to upload pre-record sessions
202 - February 6th: FOSDEM! (with live Q&A during recorded talks)
203
204 ### Contact us
205
206 - [Luke Leighton](mailto:lkcl@lkcl.net)
207 - [Christophe PFaab](mailto:pfaab@uni-bremen.de)
208 - "lkcl" or "mwfc" on #fosdem Libera.Chat IRC