1 \documentclass[slidestop
]{beamer
}
2 \usepackage{beamerthemesplit
}
10 \title{Data-Dependent-Fail-First
}
11 \author{Luke Kenneth Casson Leighton and Shriya Sharma
}
18 \huge{The Libre-SOC Hybrid
3D CPU
}\\
20 \Large{Data-Dependent-Fail-First
}\\
25 \large{Sponsored by NLnet's PET Programme
}\\
32 \frame{\frametitle{Why another SoC?
}
35 \item Intel Management Engine, Apple QA issues, Spectre
\vspace{6pt
}
36 \item Endless proprietary drivers, "simplest" solution: \\
37 License proprietary hard macros (with proprietary firmware)\\
38 Adversely affects product development cost\\
39 due to opaque driver bugs (Samsung S3C6410 / S5P100)
41 \item Alternative: Intel and Valve-Steam collaboration\\
42 "Most productive business meeting ever!"\\
43 https://tinyurl.com/valve-steam-intel
45 \item Because for
30 years I Always Wanted To Design A CPU
47 \item Ultimately it is a strategic
\textit{business
} objective to
48 develop entirely Libre hardware, firmware and drivers.
54 \frame{\frametitle{How can you help?
}
59 \item Start here! https://libre-soc.org \\
60 Mailing lists https://lists.libre-soc.org \\
61 IRC Freenode libre-soc \\
62 etc. etc. (it's a Libre project, go figure) \\
64 \item Can I get paid? Yes! NLnet funded\\
65 See https://libre-soc.org/nlnet/\#faq \\
67 \item Also profit-sharing in any commercial ventures \\
69 \item How many opportunities to develop Libre SoCs exist,\\
70 and actually get paid for it?
72 \item I'm not a developer, how can I help?\\
73 - Plenty of research needed, artwork, website \\
74 - Help find customers and OEMs willing to commit (LOI)
80 \frame{\frametitle{What goes into a typical SoC?
}
83 \item 15 to
20mm BGA package:
2.5 to
5 watt power consumption\\
84 heat sink normally not required (simplifies overall design)
86 \item Fully-integrated peripherals (not Northbridge/Southbridge)\\
87 USB, HDMI, RGB/TTL, SD/MMC, I2C, UART, SPI, GPIO etc. etc.
89 \item Built-in GPU (shared memory bus,
3rd party licensed)
\vspace{3pt
}
90 \item Built-in VPU (likewise, proprietary)
\vspace{3pt
}
91 \item Target price between \$
2.50 and \$
30 depending on market\\
92 Radically different from IBM POWER9 Core (
200 Watt)
94 \item We're doing the same, just with a hybrid architecture.\\
101 %%\frame{\frametitle{Simple SBC-style SoC}
104 %%\includegraphics[width=0.9\textwidth]{shakti_libre_soc.jpg}
112 \begin{frame
}[fragile
]
113 \frametitle{Simple-V CMPI in a nutshell
}
116 function op
\_cmpi(BA, RA, SI) # cmpi not vector-cmpi!
117 (assuming you know power-isa)
119 for (i =
0; i < VL; i++)
120 CR
[BA+id
] <= compare(ireg
[RA+ira
], SI);
121 if (reg
\_is\_vectorised[BA
] ) \
{ id +=
1; \
}
122 if (reg
\_is\_vectorised[RA
]) \
{ ira +=
1; \
}
126 \item Above is oversimplified: predication etc. left out
127 \item Scalar-scalar and scalar-vector and vector-vector now all in one
128 \item OoO may choose to push CMPIs into instr. queue (v. busy!)
132 \frame{\frametitle{Load/Store Fault-First
}
135 \item Problem: vector load and store can cause a page fault
136 \item Solution: a protocol that allows optional load/store
137 \item instruction
\textit{requests
} a number of elements
138 \item instruction
\textit{informs
} the number actually loaded
139 \item first load/store is not optional
143 \begin{frame
}[fragile
]
144 \frametitle{Data-Dependent Fail-First
}
147 function op
\_cmpi(BA, RA, SI) # cmpi not vector-cmpi!
149 for (i =
0; i < VL; i++)
150 CR
[BA+id
] <= compare(ireg
[RA+ira
], SI);
151 if (reg
\_is\_vectorised[BA
] ) \
{ id +=
1; \
}
152 if (reg
\_is\_vectorised[RA
]) \
{ ira +=
1; \
}
156 \item Above is oversimplified: predication etc. left out
157 \item Scalar-scalar and scalar-vector and vector-vector now all in one
158 \item OoO may choose to push CMPIs into instr. queue (v. busy!)
163 \frame{\frametitle{Additional Simple-V features
}
166 \item "fail-on-first" (POWER9 VSX strncpy segfaults on boundary!)
167 \item "Twin Predication" (covers VSPLAT, VGATHER, VSCATTER, VINDEX etc.)
168 \item SVP64: extensive "tag" (Vector context) augmentation
169 \item "Context propagation": a VLIW-like context. Allows contexts
170 to be repeatedly applied.
171 Effectively a "hardware compression algorithm" for ISAs.
172 \item Ultimate goal: cut down I-Cache usage, cuts down on power
173 \item Typical GPU has its own I-Cache and small shaders.\\
174 \textit{We are a Hybrid CPU/GPU: I-Cache is not separate!
}
175 \item Needs to go through OpenPOWER Foundation `approval'
179 \frame{\frametitle{maxloc
}
185 \frame{\frametitle{Pospopcount.c
}
187 Positional popcount adds up the totals of each bit set to
1 in each bit-position, of an array of input values.
189 \lstinputlisting[language=
{}]{pospopcount.c
}
192 \frame{\frametitle{Pospopcount.s
}
195 \lstinputlisting[language=
{}]{pospopcount.s
}
200 \frame{\frametitle{strncpy
}
207 \frame{\frametitle{strncpy assembler
}
209 \lstinputlisting[language=
{}]{strncpy.s
}
213 \frame{\frametitle{linked-list walking
}
218 \frame{\frametitle{Summary
}
221 \item Goal is to create a mass-volume low-power embedded SoC suitable
222 for use in netbooks, chromebooks, tablets, smartphones, IoT SBCs.
223 \item No way we could implement a project of this magnitude without
224 nmigen (being able to use python OO to HDL)
225 \item Collaboration with OpenPOWER Foundation and Members absolutely
226 essential. No short-cuts. Standards to be developed and ratified
227 so that everyone benefits.
228 \item Riding the wave of huge stability of OpenPOWER ecosystem
229 \item Greatly simplified open
3D and Video drivers reduces product
230 development costs for customers
231 \item It also happens to be fascinating, deeply rewarding technically
232 challenging, and funded by NLnet
240 {\Huge The end
\vspace{12pt
}\\
241 Thank you
\vspace{12pt
}\\
242 Questions?
\vspace{12pt
}
247 \item Discussion: http://lists.libre-soc.org
248 \item Freenode IRC \#libre-soc
249 \item http://libre-soc.org/
250 \item http://nlnet.nl/PET
251 \item https://libre-soc.org/nlnet/\#faq