1 \documentclass[slidestop
]{beamer
}
2 \usepackage{beamerthemesplit
}
10 \title{Data-Dependent-Fail-First
}
11 \author{Luke Kenneth Casson Leighton and Shriya Sharma
}
18 \huge{The Libre-SOC Hybrid
3D CPU
}\\
20 \Large{Data-Dependent-Fail-First
}\\
25 \large{Sponsored by NLnet's PET Programme
}\\
32 \frame{\frametitle{Why another SoC?
}
35 \item Intel Management Engine, Apple QA issues, Spectre
\vspace{6pt
}
36 \item Endless proprietary drivers, "simplest" solution: \\
37 License proprietary hard macros (with proprietary firmware)\\
38 Adversely affects product development cost\\
39 due to opaque driver bugs (Samsung S3C6410 / S5P100)
41 \item Alternative: Intel and Valve-Steam collaboration\\
42 "Most productive business meeting ever!"\\
43 https://tinyurl.com/valve-steam-intel
45 \item Because for
30 years I Always Wanted To Design A CPU
47 \item Ultimately it is a strategic
\textit{business
} objective to
48 develop entirely Libre hardware, firmware and drivers.
54 \frame{\frametitle{How can you help?
}
59 \item Start here! https://libre-soc.org \\
60 Mailing lists https://lists.libre-soc.org \\
61 IRC Freenode libre-soc \\
62 etc. etc. (it's a Libre project, go figure) \\
64 \item Can I get paid? Yes! NLnet funded\\
65 See https://libre-soc.org/nlnet/\#faq \\
67 \item Also profit-sharing in any commercial ventures \\
69 \item How many opportunities to develop Libre SoCs exist,\\
70 and actually get paid for it?
72 \item I'm not a developer, how can I help?\\
73 - Plenty of research needed, artwork, website \\
74 - Help find customers and OEMs willing to commit (LOI)
80 \frame{\frametitle{What goes into a typical SoC?
}
83 \item 15 to
20mm BGA package:
2.5 to
5 watt power consumption\\
84 heat sink normally not required (simplifies overall design)
86 \item Fully-integrated peripherals (not Northbridge/Southbridge)\\
87 USB, HDMI, RGB/TTL, SD/MMC, I2C, UART, SPI, GPIO etc. etc.
89 \item Built-in GPU (shared memory bus,
3rd party licensed)
\vspace{3pt
}
90 \item Built-in VPU (likewise, proprietary)
\vspace{3pt
}
91 \item Target price between \$
2.50 and \$
30 depending on market\\
92 Radically different from IBM POWER9 Core (
200 Watt)
94 \item We're doing the same, just with a hybrid architecture.\\
101 \begin{frame
}[fragile
]
102 \frametitle{Simple-V CMPI in a nutshell
}
105 function op
\_cmpi(BA, RA, SI) # cmpi not vector-cmpi!
106 (assuming you know power-isa)
108 for (i =
0; i < VL; i++)
109 CR
[BA+id
] <= compare(ireg
[RA+ira
], SI);
110 if (reg
\_is\_vectorised[BA
] ) \
{ id +=
1; \
}
111 if (reg
\_is\_vectorised[RA
]) \
{ ira +=
1; \
}
115 \item Above is oversimplified: predication etc. left out
116 \item Scalar-scalar and scalar-vector and vector-vector now all in one
117 \item OoO may choose to push CMPIs into instr. queue (v. busy!)
122 \frame{\frametitle{Load/Store Fault-First
}
125 \item Problem: vector load and store can cause a page fault
126 \item Solution: a protocol that allows optional load/store
127 \item instruction
\textit{requests
} a number of elements
128 \item instruction
\textit{informs
} the number actually loaded
129 \item first element load/store is not optional (cannot fail)
130 \item ARM SVE: https://arxiv.org/pdf/
1803.06185.pdf
131 \item more: wikipedia Vector processor page: Fault/Fail First
133 \item Load/Store is Memory to/from Register, what about
134 Register to Register?
135 \item Register-to-register: "Data-Dependent Fail-First."
136 \item Z80 LDIR: Mem-Register, CPIR: Register-Register
140 \begin{frame
}[fragile
]
141 \frametitle{Data-Dependent-Fail-First in a nutshell
}
144 function op
\_cmpi(BA, RA, SI) # cmpi not vector-cmpi!
146 for (i =
0; i < VL; i++)
147 CR
[BA+id
] <= compare(ireg
[RA+ira
], SI);
148 if (reg
\_is\_vectorised[BA
] ) \
{ id +=
1; \
}
149 if (reg
\_is\_vectorised[RA
]) \
{ ira +=
1; \
}
150 if test (CR
[BA+id
]) == FAIL: \
{ VL = i +
1; break \
}
154 \item Parallelism still perfectly possible
155 ("hold" writing results until sequential post-analysis
156 carried out. Best done with OoO)
157 \item VL truncation can be inclusive or exclusive
158 (include or exclude a NULL pointer or a
159 string-end character, or overflow result)
160 \item \textit{Truncation can be to zero Vector Length
}
164 \frame{\frametitle{Power ISA v3.1 vstribr
}
166 \lstinputlisting[language=
{}]{vstribr.txt
}
169 \item ironically this hard-coded instruction is
170 identical to general-purpose Simple-V DD-FFirst...
175 \frame{\frametitle{maxloc
}
181 \frame{\frametitle{Pospopcount
}
184 \item Positional popcount adds up the totals of each bit set to
1 in each bit-position, of an array of input values.
185 \item Notoriously difficult to do in SIMD assembler: typically
550 lines
189 \lstinputlisting[language=
{}]{pospopcount.c
}
193 \frame{\frametitle{Pospopcount
}
196 \includegraphics[width=
0.6\textwidth]{pospopcount.png
}
199 \item The challenge is to perform an appropriate transpose of the data (the CPU can only work on registers, horizontally),
200 in blocks that suit the processor and the ISA capacity.
206 \frame{\frametitle{Pospopcount
}
209 \includegraphics[width=
0.6\textwidth]{array_popcnt.png
}
214 \item The draft gbbd instruction implements the transpose (shown above),
215 preparing the data to use the standard popcount instruction.
222 \frame{\frametitle{Pospopcount.s
}
225 \lstinputlisting[language=
{}]{pospopcount.s
}
230 \frame{\frametitle{strncpy
}
232 \lstinputlisting[language=
{}]{strncpy.c
}
240 \frame{\frametitle{strncpy assembler
}
242 \lstinputlisting[language=
{}]{strncpy.s
}
246 \frame{\frametitle{linked-list walking
}
251 \frame{\frametitle{Summary
}
254 \item Goal is to create a mass-volume low-power embedded SoC suitable
255 for use in netbooks, chromebooks, tablets, smartphones, IoT SBCs.
256 \item No way we could implement a project of this magnitude without
257 nmigen (being able to use python OO to HDL)
258 \item Collaboration with OpenPOWER Foundation and Members absolutely
259 essential. No short-cuts. Standards to be developed and ratified
260 so that everyone benefits.
261 \item Riding the wave of huge stability of OpenPOWER ecosystem
262 \item Greatly simplified open
3D and Video drivers reduces product
263 development costs for customers
264 \item It also happens to be fascinating, deeply rewarding technically
265 challenging, and funded by NLnet
273 {\Huge The end
\vspace{12pt
}\\
274 Thank you
\vspace{12pt
}\\
275 Questions?
\vspace{12pt
}
280 \item Discussion: http://lists.libre-soc.org
281 \item Freenode IRC \#libre-soc
282 \item http://libre-soc.org/
283 \item http://nlnet.nl/PET
284 \item https://libre-soc.org/nlnet/\#faq