1 # (DRAFT) Devroom Schedule
5 - Tobias requested 60 min. Unfortunately there simply isn't enough time, thus
6 Tobias will need to condense his talk down to 30min (or shorter). Assuming
7 Tobias adjusts the time down to 30 min (25+5), **we need to find another 20min
9 - Q&As are being used as breaks (only explicit break is between Sadoon's
11 - I (Andrey) have reduced the length of my talks to 10+5 and 15+5 respectively. I kept Cesar's talk at full 25+5 to make he has enough time to cover formal verification.
13 ## (Draft) Schedule for Saturday
15 |Time |Talk|Speaker|Comments|
16 |-----|----|-------|--------|
17 |10:30|Overview of LibreSOC|Andrey||
20 |10:45|Cologne Chip GateMate FPGA -- filling a gap between hardware and software (with a presentation of the GMM-7550 module)|Anton Kuzmin||
26 |11:15|Introduction to SimpleV and PowerISA+SVP64|Andrey||
30 | |Cryptographic Algorithm Vectorization for Mortals|Sadoon||
37 | |Linux Distribution Porting for Architecture Subsets - 20+5 min|Sadoon||
42 | |Advanced Simple-V: Data-dependent Fail-First|Luke||
48 | |How to write code for an experimental ISA like SVP64?|Konstantinos||
54 | |How to Commercialise Open-Source Work as a Business - Example LibreSOC and RED|James||
57 | |An introduction to Formal Verification of Digital Circuits|Cesar||
63 | |Using the ECP5 for Libre-SOC prototyping|Tobias||