bug 1244: add power isa v3.1 vstribr pseudocode
[libreriscv.git] / conferences / fosdem2024 / fosdem2024_schedule.mdwn
1 # (DRAFT) Devroom Schedule
2
3 ## Points of note
4
5 - Tobias requested 60 min. Unfortunately there simply isn't enough time, thus
6 Tobias will need to condense his talk down to 30min (or shorter). Assuming
7 Tobias adjusts the time down to 30 min (25+5), **we need to find another 20min
8 of time**.
9 - Q&As are being used as breaks (only explicit break is between Sadoon's
10 talks).
11 - I (Andrey) have reduced the length of my talks to 10+5 and 15+5 respectively. I kept Cesar's talk at full 25+5 to make he has enough time to cover formal verification.
12
13 ## (Draft) Schedule for Saturday
14
15 |Time |Talk|Speaker|Comments|
16 |-----|----|-------|--------|
17 |10:30|Overview of LibreSOC|Andrey||
18 | ||||
19 | |Q&A|||
20 |10:45|Cologne Chip GateMate FPGA -- filling a gap between hardware and software (with a presentation of the GMM-7550 module)|Anton Kuzmin||
21 | ||||
22 | ||||
23 |11:00||||
24 | ||||
25 | |Q&A|||
26 |11:15|Introduction to SimpleV and PowerISA+SVP64|Andrey||
27 | ||||
28 | ||||
29 |11:30|Q&A|||
30 | |Cryptographic Algorithm Vectorization for Mortals|Sadoon||
31 | ||||
32 |11:45||||
33 | ||||
34 | ||||
35 |12:00|Q&A|||
36 | |Break|||
37 | |Linux Distribution Porting for Architecture Subsets - 20+5 min|Sadoon||
38 |12:15||||
39 | ||||
40 | ||||
41 |12:30|Q&A|||
42 | |Advanced Simple-V: Data-dependent Fail-First|Luke||
43 | ||||
44 |12:45||||
45 | ||||
46 | ||||
47 |13:00|Q&A|||
48 | |How to write code for an experimental ISA like SVP64?|Konstantinos||
49 | ||||
50 |13:15||||
51 | ||||
52 | ||||
53 |13:30|Q&A|||
54 | |How to Commercialise Open-Source Work as a Business - Example LibreSOC and RED|James||
55 | ||||
56 |13:45|Q&A|||
57 | |An introduction to Formal Verification of Digital Circuits|Cesar||
58 | ||||
59 |14:00||||
60 | ||||
61 | ||||
62 |14:15|Q&A|||
63 | |Using the ECP5 for Libre-SOC prototyping|Tobias||
64 | ||||
65 |**14:30**||||
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