conferences/ics2021/ics2021_svp64.tex

   1 \documentclass[slidestop]{beamer}
   2 \usepackage{beamerthemesplit}
   3 \usepackage{graphics}
   4 \usepackage{pstricks}
   5
   6 \graphicspath{{./}}
   7
   8 \title{The Libre-SOC Hybrid 3D CPU}
   9 \author{Luke Kenneth Casson Leighton}
  10
  11
  12 \begin{document}
  13
  14 \frame{
  15    \begin{center}
  16     \huge{Libre-SOC SVP64 Vector Processing}\\
  17     \vspace{32pt}
  18     \Large{Augmenting the OpenPOWER ISA}\\
  19     \Large{to provide 3D and Video instructions}\\
  20     \Large{and add Cray-style Vector Extensions}\\
  21     \vspace{24pt}
  22     \Large{ICS2021}\\
  23     \vspace{16pt}
  24     \large{Sponsored by NLnet's PET Programme}\\
  25     \vspace{6pt}
  26     \large{June 14, 2021}
  27   \end{center}
  28 }
  29
  30
  31 \frame{\frametitle{OpenPOWER today}
  32
  33 \begin{center}
  34  \begin{itemize}
  35    \item Open ISA: EULA v3.0B announced August 2019\vspace{6pt}
  36    \item Compliancy subsets: mandatory and optional features
  37                  \vspace{6pt}
  38    \item Compliance provides royalty-free IBM Patent grant\vspace{6pt}
  39    \item Custom extensions permitted (see v3.0C): recommends "common-usage"
  40          ones be submitted as RFCs to OpenPOWER ISA WG
  41                 \vspace{6pt}
  42    \item On this basis we have the freedom and are encouraged to create
  43                 Cray-style Vectorisation Extensions
  44                 \vspace{6pt}
  45    \item VSX will not be part of that: it is fixed-width SIMD.\\
  46                   https://tinyurl.com/simd-considered-harmful\\
  47                   https://en.wikipedia.org/wiki/Vector\_processor
  48                 \vspace{6pt}
  49   \end{itemize}
  50 \end{center}
  51
  52 }
  53
  54
  55 \frame{\frametitle{Why OpenPOWER?}
  56
  57 \vspace{10pt}
  58
  59  \begin{itemize}
  60    \item Good ecosystem essential\\
  61                  linux kernel, u-boot, compilers, OSes,\\
  62                  Reference Implementation(s)\vspace{10pt}
  63    \item Supportive Foundation and Members\\
  64                  need to be able to submit ISA augmentations\\
  65                  (for proper peer review)\vspace{10pt}
  66    \item No NDAs, full transparency must be acceptable\\
  67              due to being funded under NLnet's PET Programme\vspace{10pt}
  68    \item OpenPOWER: established for decades, excellent Foundation,\\
  69              Microwatt as Reference, approachable and friendly.
  70   \end{itemize}
  71 }
  72
  73
  74 \frame{\frametitle{What's different about SVP64?}
  75
  76  \begin{itemize}
  77    \item SVP64 is similar to Intel x86 "REP" instruction\\
  78                  "please repeat the following instruction N times"\\
  79                  (but add some extra "stuff" in the process)
  80                   \vspace{9pt}
  81    \item Unlike "REP" there is additional "Vector context":\\
  82                  Predication, Twin-predication, Element-width Overrides,
  83                  Map-reduce, Iteration, Saturation and more.
  84                   \vspace{9pt}
  85    \item None of this requires extra instructions!\\
  86                  (except setvl and the "REP"-like prefix)\\
  87                   \vspace{6pt}
  88    \item "SIMD Considered Harmful" principle applies equally
  89                  to RISC-V Vectors (190+ instructions on top of RV64GC's 80)\\
  90                  \em{RVV more than doubles the number of RISC-V instructions}.
  91   \end{itemize}
  92 }
  93
  94
  95
  96 \begin{frame}[fragile]
  97 \frametitle{Simple-V ADD in a nutshell}
  98
  99 \begin{semiverbatim}
 100 function op\_add(rd, rs1, rs2, predr) # add not VADD!
 101   int i, id=0, irs1=0, irs2=0;
 102   for (i = 0; i < VL; i++)
 103     if (ireg[predr] & 1<<i) # predication uses intregs
 104        ireg[rd+id] <= ireg[rs1+irs1] + ireg[rs2+irs2];
 105     if (reg\_is\_vectorised[rd] )  \{ id += 1; \}
 106     if (reg\_is\_vectorised[rs1])  \{ irs1 += 1; \}
 107     if (reg\_is\_vectorised[rs2])  \{ irs2 += 1; \}
 108 \end{semiverbatim}
 109
 110   \begin{itemize}
 111    \item Above is oversimplified: Reg. indirection left out (for clarity).
 112    \item SIMD slightly more complex (case above is elwidth = default)
 113    \item Scalar-scalar and scalar-vector and vector-vector now all in one
 114    \item OoO may choose to push ADDs into instr. queue (v. busy!)
 115   \end{itemize}
 116 \end{frame}
 117
 118
 119 \frame{\frametitle{Additional Simple-V features}
 120
 121  \begin{itemize}
 122    \item "fail-on-first" (POWER9 VSX strncpy segfaults on boundary!)
 123    \item "Twin Predication" (covers VSPLAT, VGATHER, VSCATTER, VINDEX etc.)
 124    \item SVP64: extensive "tag" (Vector context) augmentation
 125    \item "Context propagation": a VLIW-like context.  Allows contexts
 126          to be repeatedly applied.
 127           Effectively a "hardware compression algorithm" for ISAs.
 128    \item Ultimate goal: cut down I-Cache usage, cuts down on power
 129    \item Typical GPU has its own I-Cache and small shaders.\\
 130         \textit{We are a Hybrid CPU/GPU: I-Cache is not separate!}
 131    \item Needs to go through OpenPOWER Foundation `approval'
 132   \end{itemize}
 133 }
 134
 135 \frame{\frametitle{How can you help?}
 136
 137 \vspace{5pt}
 138
 139  \begin{itemize}
 140    \item Start here! https://libre-soc.org \\
 141              Mailing lists https://lists.libre-soc.org \\
 142              IRC Freenode libre-soc \\
 143              etc. etc. (it's a Libre project, go figure) \\
 144                    \vspace{3pt}
 145    \item Can I get paid? Yes!  NLnet funded\\
 146                  See https://libre-soc.org/nlnet/\#faq \\
 147                  \vspace{3pt}
 148    \item Also profit-sharing in any commercial ventures \\
 149              \vspace{3pt}
 150    \item How many opportunities to develop Libre SoCs exist,\\
 151              and actually get paid for it?
 152                      \vspace{3pt}
 153    \item I'm not a developer, how can I help?\\
 154                 - Plenty of research needed, artwork, website \\
 155                 - Help find customers and OEMs willing to commit (LOI)
 156   \end{itemize}
 157 }
 158
 159 \frame{\frametitle{Simple SBC-style SoC}
 160
 161 \begin{center}
 162 \includegraphics[width=0.9\textwidth]{shakti_libre_soc.jpg}
 163 \end{center}
 164
 165 }
 166
 167 \frame{\frametitle{Summary}
 168
 169  \begin{itemize}
 170    \item Goal is to create a mass-volume low-power embedded SoC suitable
 171          for use in netbooks, chromebooks, tablets, smartphones, IoT SBCs.
 172    \item No way we could implement a project of this magnitude without
 173          nmigen (being able to use python OO to  HDL)
 174    \item Collaboration with OpenPOWER Foundation and Members absolutely
 175          essential. No short-cuts.  Standards to be developed and ratified
 176          so that everyone benefits.
 177    \item Riding the wave of huge stability of OpenPOWER ecosystem
 178    \item Greatly simplified open 3D and Video drivers reduces product
 179          development costs for customers
 180    \item It also happens to be fascinating, deeply rewarding technically
 181          challenging, and funded by NLnet
 182
 183   \end{itemize}
 184 }
 185
 186
 187 \frame{
 188   \begin{center}
 189     {\Huge The end\vspace{12pt}\\
 190                    Thank you\vspace{12pt}\\
 191                    Questions?\vspace{12pt}
 192         }
 193   \end{center}
 194
 195   \begin{itemize}
 196         \item Discussion: http://lists.libre-soc.org
 197         \item OFTC IRC \#libre-soc
 198         \item http://libre-soc.org/
 199         \item http://nlnet.nl/PET
 200         \item https://libre-soc.org/nlnet/\#faq
 201   \end{itemize}
 202 }
 203
 204 \end{document}