conferences/ics2021.mdwn

   1 # ICS2021
   2
   3 14 June 2021
   4
   5 * <https://ics21.github.io/>
   6 * <https://www.timeanddate.com/worldclock/meetingtime.html?day=14&month=6&year=2021&p1=%20141&p2=236&p3=1234&p4=250&p5=24&p6=224&iv=0>
   7 * <https://meep-project.eu/events/ics-2021>
   8
   9 # Luke Leighton bio
  10
  11 Luke Kenneth Casson Leighton specialises in Libre Ethical Technology.
  12 He has been using, programming and reverse-engineering computing
  13 devices continuously for 44 years, has a BEng (Hons), ACGI, in
  14 Theory of Computing from Imperial College, and recently put that
  15 education to good use in the form of the Libre-SOC
  16 Project: an entirely Libre-Licensed 3D Hybrid CPU-VPU-GPU based on
  17 OpenPOWER. He writes poetry and has been developing a HEP Physics theory
  18 for the past 36 years in his spare time.
  19
  20 # SVP64 Abstract
  21
  22 The OpenPOWER ISA has a strong multi-decades pedigree in Supercomputing:
  23 Matrix Multiply, 128-bit SIMD, BCD, Decimal Floating-point have been part
  24 of the ISA for decades, supporting Business and Scientific Computing.
  25 What the OpenPOWER ISA does not have is Vector processing, first
  26 successfully found in the Cray-1 Supercomputer, from 1976.
  27
  28 SVP64 is an initiative being developed by the Libre-SOC team and
  29 funded by NLnet, that brings Cray-style Variable-length Vectorisation
  30 to the OpenPOWER ISA in a seamless and non-disruptive fashion.  The team
  31 is keeping the OpenPOWER Foundation appraised of progress, and plans to
  32 submit SVP64 as an RFC to the newly-formed OpenPOWER ISA Working Group.
  33
  34 SVP64 is based on the concept of embedding scalar operations into
  35 a Vectorisation Context: effectively a simple Sub-Program-Counter for-loop.
  36 However that Vectorisation Context effectively extends each of the 200+
  37 primary scalar operations in the OpenPOWER ISA by a factor of 4,000,
  38 to produce a staggering and unprecedented 800,000 unique Vector opcodes.
  39
  40 Although SVP64 borrows from innovations in Computer Science over the
  41 past 50 years, including the original Cray Vectors, VLIW, Zero-overhead
  42 Loops from DSPs and Intel MMX, the end result is something entirely new.
  43 This talk will go through the development process of SVP64 and explain
  44 some of the innovative Vectorisation concepts that have never been seen
  45 before in any commercial or academic Vector ISA, including
  46 Twin-Predication and "Post-result" predication, and how these will
  47 benefit Supercomputing performance and decrease power consumption,
  48 by reducing I-Cache usage.
  49
  50 # Comprehensive life-cycle of mixed testing: HDL to gates
  51
  52 The Libre-SOC Project is developed by Software Engineers with a Hardware
  53 background: in particular, Software Engineers with decades of experience
  54 in the Libre / Open software ecosystem.  There is a huge difference.
  55
  56 Software Engineers have it drummed into them from either training or
  57 bitter experience that unit tests are critical at every level.  Whilst
  58 the Validation Process for an ASIC goes through a rigorous process
  59 in the Synthesis Tools to ensure its correctness at every step, the
  60 actual HDL itself, shockingly, is typically put together first and
  61 only on completion are high-level (binary) unit tests run.  Errors
  62 in a low-level subsystem thus become extremely hard to find.
  63
  64 In addition to that, as a Libre Project, we have had to use Libre
  65 VLSI tools. These are in active development and have not - yet -
  66 been used to develop ASICs beyond 130nm or over 1,000,000 gates.
  67 Our ASIC toolchain and HDL verification procedures are therefore
  68 functional but a little different from Industry-standard (proprietary)
  69 norm.
  70
  71 This talk will therefore show, by example, how we went from low-level
  72 modules (with unit tests and Formal Correctness Proofs), to pipelines
  73 (with unit tests and Formal Correctness Proofs), to a functional Core
  74 (with several thousand unit tests), right the way to ASIC layout,
  75 from which the Netlist was extracted and then co-simulated with cocotb.
  76 At each and every stage - both pre and post layout and on FPGA - it
  77 has been possible to run the exact same JTAG Boundary Scan and basic
  78 startup procedure.
  79