conferences/iit_roorkee_2021/iit_roorkee_2021.tex

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   7
   8 \title{The Libre-SOC OpenPOWER 180nm ASIC}
   9 \author{Luke Kenneth Casson Leighton}
  10
  11 \begin{document}
  12
  13 \frame{
  14    \begin{center}
  15     \huge{Libre-SOC Power ISA 180nm ASIC}\\
  16     \vspace{32pt}
  17     \Large{Concept to completion:}\\
  18     \Large{Why we chose nmigen and OpenPOWER}\\
  19     \Large{What happened along the way}\\
  20     \vspace{24pt}
  21     \Large{IIT Roorkee 2021}\\
  22     \vspace{16pt}
  23     \large{Sponsored by NLnet's PET Programme}\\
  24     \vspace{6pt}
  25     \large{\today}
  26   \end{center}
  27 }
  28
  29
  30 \frame{\frametitle{Why start a new SoC?}
  31
  32  \begin{itemize}
  33    \item Intel Management Engine, Apple QA issues, Spectre\vspace{6pt}
  34    \item Zero transparency: commodity hardware cannot be audited.
  35          \vspace{6pt}
  36    \item Endless proprietary drivers, "simplest" solution: \\
  37          License proprietary hard macros (with proprietary firmware)\\
  38                  Adversely affects product development cost\\
  39                 due to opaque driver bugs (Samsung S3C6410 / S5P100)
  40                  \vspace{6pt}
  41    \item Alternative: Intel and Valve-Steam collaboration\\
  42          "Most productive business meeting ever!"\\
  43          https://tinyurl.com/valve-steam-intel
  44                 \vspace{6pt}
  45    \item Ultimately it is a strategic \textit{business} objective to
  46          develop entirely Libre hardware, firmware and drivers.
  47   \end{itemize}
  48 }
  49
  50
  51 \frame{\frametitle{Why OpenPOWER?}
  52
  53 \vspace{15pt}
  54
  55  \begin{itemize}
  56    \item Good ecosystem essential\\
  57                  linux kernel, u-boot, compilers, OSes,\\
  58                  Reference Implementation(s)\vspace{10pt}
  59    \item Supportive Foundation and Members\\
  60                  need to be able to submit ISA augmentations\\
  61                  (for proper peer review)\vspace{10pt}
  62    \item No NDAs, full transparency must be acceptable\\
  63              due to being funded under NLnet's PET Programme\vspace{10pt}
  64    \item OpenPOWER: established for decades, excellent Foundation,\\
  65              Microwatt as Reference, approachable and friendly.
  66   \end{itemize}
  67 }
  68
  69
  70 \frame{\frametitle{Choosing an HDL}
  71
  72  \begin{itemize}
  73    \item 3 months careful evaluation: Chisel3, MyHDL, Verilog, VHDL, migen,
  74                 nmigen
  75    \item Love the OO capabilities of Chisel3, shame about the TIOBE Index
  76                 (below 20th)
  77         \item MyHDL is in python, but limits to a subset of python.  Also,
  78                  community not as large as for nmigen.
  79    \item migen extremely inconvenient: errors created and not caught until
  80          ASIC synthesis level!
  81     \item Verilog is 1980s (like BASIC and FORTRAN) - considered "machine
  82          code"
  83     \item VHDL is great (has records) but still no OO capability
  84     \item Ultimately nmigen chosen due to large community, and because
  85          python is 3rd on the TIOBE index (contd)
  86   \end{itemize}
  87 }
  88
  89 \frame{\frametitle{Why nmigen?}
  90
  91  \begin{itemize}
  92    \item Uses python to build an AST (Abstract Syntax Tree).
  93          Actually hands that over to yosys (to create ILANG file)
  94          after which verilog can (if necessary) be created
  95    \item Deterministic synthesiseable behaviour (Signals are declared
  96          with their reset pattern: no more forgetting "if rst" block).
  97    \item python OO programming techniques can be deployed.  classes
  98          and functions created which pass in parameters which change
  99          what HDL is created (IEEE754 FP16 / 32 / 64 for example)
 100    \item python-based for-loops can e.g. read CSV files then generate
 101          a hierarchical nested suite of HDL Switch / Case statements
 102          (this is how the Libre-soc PowerISA decoder is implemented)
 103    \item extreme OO abstraction can even be used to create "dynamic
 104          partitioned Signals" that have the same operator-overloaded
 105          "add", "subtract", "greater-than" operators
 106
 107   \end{itemize}
 108 }
 109
 110
 111 \frame{\frametitle{Software Engineering Techniques}
 112
 113  \begin{itemize}
 114    \item Entire project run along standard Libre Software Project
 115         Management: public bugtracker, public mailing lists, public IRC,
 116         public git repositories, Charter http://libre-soc.org/charter/
 117    \item None of our engineers are Hardware trained! They are all
 118          software developers who learned HDL!
 119    \item The other way round makes life much harder.
 120    \item Like Microwatt, we develop unit tests, use git revision control,
 121                 and bugtrackers (TODO, still - set up Continuous Integration)
 122    \item Unlike Microwatt, we also have a wiki for all documentation
 123          (backed by a git repository with full revision control)
 124    \item Software Engineering techniques are critical for large project
 125                 management! unit tests, unit tests, unit tests...
 126   \end{itemize}
 127 }
 128
 129 \frame{\frametitle{Auditability and Transparency}
 130
 131  \begin{itemize}
 132    \item Funded by NLnet's "Privacy and Enhanced Trust Programme"
 133    \item Matches well with business objectives to provide customers
 134                  with ability to inspect down to Gate Level (GDS-II files)
 135    \item (Impossible for Intel etc to do, due to 3rd party licensing
 136                 of 50-60 pieces of HDL).
 137         \item Sorbonne University LIP6.fr http://coriolis2.lip6.fr is
 138              an entirely Libre-licensed VLSI toolchain
 139         \item (coriolis2 is "Zero config" from HDL to GDS-II)
 140         \item Chips4Makers.io Cell Library - FlexLib - has "Symbolic"
 141               and "Real" versions.
 142         Symbolic is public and published, uses FreePDK45
 143         "Real" is NDA'd with Foundry.
 144     \item Therefore: Libre-SOC team can work side-by-side with
 145           LIP6.fr WITHOUT signing a Foundry NDA.
 146
 147   \end{itemize}
 148 }
 149
 150 \frame{\frametitle{Development Process}
 151
 152  \begin{itemize}
 153    \item nmigen HDL, in python, converted to verilog using yosys
 154    \item developed several thousand unit tests at every level
 155    \item Jean-Paul Chaput improved coriolis2 to cope with automated layout
 156                 of 130,000 Cells. Antenna, buffers, etc.
 157         \item Chips4Makers FlexLib Cell Library also needed development, including
 158            a custom 4k SRAM block (under NDA, sorry)
 159         \item Professor Galayko developed a Voltage-Controlled PLL, capable of
 160                 between 150 and 900 mhz.
 161     \item Marie-Minerve Louerat developed and ran HITAS (Static Timing
 162     Analysis tool).
 163     \item Tried simulating the laid-out ASIC, required too much resources.
 164         Instead, simulated smaller ASICs
 165
 166   \end{itemize}
 167 }
 168
 169 \frame{\frametitle{ASIC diagram sent to TSMC}
 170
 171 \begin{center}
 172 \includegraphics[width=0.7\textwidth]{ls180.png}
 173 \end{center}
 174
 175 }
 176
 177
 178
 179 \frame{
 180   \begin{center}
 181     {\Huge The end\vspace{12pt}\\
 182                    Thank you\vspace{12pt}\\
 183                    Questions?\vspace{12pt}
 184         }
 185   \end{center}
 186
 187   \begin{itemize}
 188         \item Discussion: http://lists.libre-soc.org
 189         \item Libera IRC \#libre-soc
 190         \item http://libre-soc.org/
 191         \item http://nlnet.nl/PET
 192         \item https://libre-soc.org/nlnet/\#faq
 193   \end{itemize}
 194 }
 195
 196
 197 \end{document}