conferences/ngipointer2021/cnect2022.tex

   1 \documentclass[slidestop]{beamer}
   2 \usepackage{beamerthemesplit}
   3 \usepackage{graphics}
   4 \usepackage{pstricks}
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   6 \graphicspath{{./}}
   7
   8 \title{The Libre-SOC Gigabit Router ASIC}
   9 \author{Luke Kenneth Casson Leighton}
  10
  11
  12 \begin{document}
  13
  14 \frame{
  15    \begin{center}
  16     \huge{The Libre-SOC Gigabit Router ASIC}\\
  17     \vspace{32pt}
  18     \Large{An entirely Libre-Licensed ASIC}\\
  19     \Large{with Gigabit Ethernet ports and USB2}\\
  20     \Large{and full Libre Firmware}\\
  21     \vspace{24pt}
  22     \Large{CNECT 2022}\\
  23     \vspace{16pt}
  24     \large{Sponsored by NGI POINTER and NLnet}\\
  25     \vspace{6pt}
  26     \large{\today}
  27   \end{center}
  28 }
  29
  30
  31 \frame{\frametitle{Why a Libre Gigabit Router?}
  32
  33  \begin{itemize}
  34    \item Most Router ASICs are proprietary\vspace{6pt}
  35    \item Persistent GPL violations \vspace{6pt}
  36    \item Could contain unknown spying back-doors\\
  37          nobody can tell\vspace{6pt}
  38    \item Full HDL and Firmware means it's fully-auditable \vspace{6pt}
  39   \end{itemize}
  40 }
  41
  42
  43 \frame{\frametitle{Who?}
  44
  45 \vspace{15pt}
  46
  47  \begin{itemize}
  48    \item Luke Leighton (Libre-SOC)\\
  49                  Lead developer \vspace{10pt}
  50    \item Jean-Paul Chaput, \\
  51                 Dmitry Galayko, \\
  52                 Marie-Minerve Louerat\\
  53                  LIP6.fr, Sorbonne University\\
  54                  Developers of Coriolis2 VLSI \vspace{10pt}
  55    \item Staf Verhaegen\\
  56                  Chips4Makers.io Belgium\\
  57                  Developer of FlexLib Cell Libraries \vspace{10pt}
  58   \end{itemize}
  59 }
  60
  61 \frame{\frametitle{What?}
  62
  63 \vspace{5pt}
  64
  65  \begin{itemize}
  66    \item Vector Processor based on the Power ISA, (Draft) SVP64
  67          Cray Vectors and efficient packet processing instructions
  68    \item Gigabit Ethernet Ports (RGMII) USB2 ports (USB-ULPI),
  69          GPIO, I2C, QSPI etc.
  70    \item DMA Engine to handle fast transfer between Ethernet Ports
  71    \item Analog PLL (Libre-Licensed, no NDA)
  72    \item Lots of simulations and FPGA testing
  73    \item Put it all together: MPW Shuttle Runs\\
  74          to be tested, report published
  75    \item All entirely Libre-Licensed\\
  76          as best we can comply with Foundry NDAs
  77   \end{itemize}
  78 }
  79
  80 \frame{\frametitle{How?}
  81
  82 \vspace{5pt}
  83
  84  \begin{itemize}
  85    \item Entirely in nmigen HDL (python-based, Libre-Licensed)
  86    \item Huge ancillary spin-off libraries created:
  87    \item IEEE754 pipelined FPU, SIMD Library, I/O HDL Library
  88    \item Power ISA now in Machine-readable form
  89    \item Coriolis2 VLSI now silicon-proven in 10x larger automated
  90                  layouts (800,000 gates)
  91    \item No NDAs, no commercial confidential agreements signed
  92          means full Academic and Ethical Freedom to talk about
  93          what we did and how we did it
  94   \end{itemize}
  95 }
  96
  97
  98 \frame{
  99   \begin{center}
 100     {\Large The end\vspace{12pt}\\
 101                    Thank you\vspace{12pt}\\
 102                    Questions?\vspace{12pt}
 103         }
 104   \end{center}
 105
 106   \begin{itemize}
 107         \item Discussion: http://lists.libre-soc.org
 108         \item Libera IRC \#libre-soc
 109         \item http://libre-soc.org/
 110         \item http://coriolis.lip6.fr
 111         \item http://chips4makers.io
 112   \end{itemize}
 113 }
 114
 115
 116 \end{document}