conferences/openpower2021.mdwn

   1 # OpenPOWER Summit 2021
   2
   3 Links
   4
   5 * Full Schedule: <https://cfp.openpower.foundation/summit2021/schedule/>
   6 * <https://cfp.openpower.foundation/summit2021/cfp>
   7 * <https://cfp.openpower.foundation/summit2021/talk/review/CA7XEWT9ZKMJ3D7NRXXEK9SYPXBAHPCD>
   8 * <https://events.linuxfoundation.org/openpower-summit-north-america/>
   9 * <https://cfp.openpower.foundation/summit2021/talk/NWMQTE/>
  10 * 2021-10-28, 13:00–13:45, RoomB <https://zoom.us/j/99048202175>
  11 * Slides <https://ftp.libre-soc.org/openpower_2021.pdf>
  12 * Talk Preview <https://www.youtube.com/watch?v=NpmbUfgiuFE>
  13 * SVP64 REMAP <https://libre-soc.org/openpower/sv/remap/>
  14 * <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/fastdctlee.py;hb=HEAD>
  15 * <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/remapyield.py;hb=HEAD>
  16 * <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/remap_dct_yield.py;hb=HEAD>
  17 * <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/remap_fft_yield.py;hb=HEAD>
  18 * <https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;hb=HEAD>
  19
  20 # Notes from the talk
  21
  22 ```
  23 those are all "in-place" (i.e. you use the register file to complete the entire operation, no LD/STs needed in the middle)
  24 it's a ridiculously-long list! https://en.wikipedia.org/wiki/Discrete_cosine_transform#Applications
  25 https://en.wikipedia.org/wiki/Discrete_Fourier_transform_(general)
  26 the NTT wiki page is here https://en.wikipedia.org/wiki/Discrete_Fourier_transform_(general)#Number-theoretic_transform
  27 like, not having 4-wide SIMD and only using 3 of the SIMD lanes
  28 https://arxiv.org/abs/2002.10143#
  29 fascinating paper
  30 that's down to not having to do branches
  31 because the zero-overhead loop doesn't even need a branch instruction
  32 no predication in VSX, either.
  33 it's a rather unfortunate dichotomy, here
  34 which according to the "strict" definition of "Custom Extension" would be in OPCODE 22
  35
  36 https://libre-soc.org/openpower/sv/overview/
  37 fascinatingly this was exactly what Peter Hsu (architect of the MIPS R8000) came up with back around 1994-5!
  38 unfortunately, the only reason they didn't go ahead with it was because they hadn't worked out Multi-Issue Out-of-Order Execution at the time
  39 so couldn't fully exploit the idea
  40 each REMAP can actually be applied to more than one register if required
  41 which is used (shown later) in the 5-operand (draft) instructions
  42 you _could_ do this but you have to have a massive number of Reservation Stations
  43 (an In-Order system would be hosed)
  44 so with this trick you get multiple pipelined FMACs outstanding
  45 the hope is that by the time the inner for-loop has completed, you can do another (partial) FMAC on the same register
  46 i meant, you rotate (not transpose) :)
  47 the matrix data is in order 0 1 2 3
  48 but REMAP can access it in 0 2 1 3
  49 or invert the X-dimension
  50 1 2 0 3
  51
  52 and that is basically the values of the matrix "rotated" :)
  53 https://libre-soc.org/openpower/sv/remap/
  54 Aspex was bought out by Ericsson, so the only information available on it now is papers by Argy Krikelis
  55 and the other co-designers
  56 https://www.researchgate.net/profile/Argy-Krikelis
  57 here's the source for that matrix unit test
  58 https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_matrix.py;hb=HEAD
  59 to experiment with Matrix "Schedules" this is a simple stand-alone program
  60 https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/remapyield.py;hb=HEAD
  61
  62 so you can have data appear to be re-ordered *in-place* (register numbers):
  63 r0 r3 r6
  64 r1 r4 r7
  65 r2 r5 r8
  66 we cut down the MP3 FFMPEG main loop from 450 instructions down to *only 100*.
  67 it was stunning, totally unexpected
  68 ohh dear. FFT. this was hellishly complicated :) took about 2 months to do both DCT and FFT
  69 that 5-operand draft instruction is crucial to do DCT and FFT in-place
  70 if you don't want to do in-place, you can get away with the "normal" approach of using a temp scalar variable (and 3-4 instructions)
  71 but, that kiinda defeats the object of the exercise :)
  72 https://www.ti.com/lit/an/sprabb6b/sprabb6b.pdf
  73 TMS320 FFT
  74 standard library for the nexagon
  75 https://developer.qualcomm.com/forum/qdn-forums/software/hexagon-dsp-sdk/audio-capiappi/33010
  76 definite "wow" on the number of VLIW uOps for Hexagon
  77
  78 https://developer.qualcomm.com/download/hexagon/hexagon-dsp-architecture.pdf
  79 https://www.nayuki.io/res/fast-discrete-cosine-transform-algorithms/lee-new-algo-discrete-cosine-transform.pdf
  80 the original paper by Byeong Gi Lee. 1984!
  81 here's the stand-alone program which can generate the triple-loop schedules
  82 https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/remap_fft_yield.py;h=422c2187867bba75c5a33d395e74d2d1081199d1;hb=0b7eb1cc2b6f1b820a54e668724f1e00967e85f3
  83 whoops i meant "add it to X[0]" :)
  84 https://www.nayuki.io/page/free-small-fft-in-multiple-languages
  85 https://developer.qualcomm.com/download/hexagon/hexagon-dsp-architecture.pdf
  86 https://www.nayuki.io/res/fast-discrete-cosine-transform-algorithms/lee-new-algo-discrete-cosine-transform.pdf
  87 the original paper by Byeong Gi Lee. 1984!
  88 here's the stand-alone program which can generate the triple-loop schedules
  89 https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/remap_fft_yield.py;h=422c2187867bba75c5a33d395e74d2d1081199d1;hb=0b7eb1cc2b6f1b820a54e668724f1e00967e85f3
  90 whoops i meant "add it to X[0]" :)
  91 https://www.nayuki.io/page/free-small-fft-in-multiple-languages
  92 really cool set of implementations of FFT
  93 this was mind-bending :)
  94 of course, if you are not doing in-place, it doesn't matter
  95 but when you don't do in-place, you end up using *double the number of registers* which is how a lot of implementations of FFT work. sigh
  96 that puts pressure on the regfile, which is a critical resource in 3D and Video applications
  97 power consumption ends up going through the roof if you have to "spill"
  98 the full unit test(s) for SVP64 FFT remap are here https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_fft.py;hb=HEAD
  99 this is where the bit about mapping any one of the 3 REMAPs to *five* possible target registers is needed
 100 which is why svremap takes so many operands :)
 101 https://opencores.org/projects/hwlu
 102 it's in VHDL.
 103 the paper on ZOLC is fascinating https://www.researchgate.net/publication/224647569_A_portable_specification_of_zero-overhead_looping_control_hardware_applied_to_embedded_processors
 104 and, like the Snitch core, has absolutely stunning reductions in instruction count (and power consumption)
 105 reverse-order
 106 0123
 107 7654
 108 for DCT
 109 where FFT is
 110 0123
 111 4567
 112 i was amazed by this elegant algorithm
 113 from looking at the numbers
 114 here's the source for a stand-alone program to create DCT schedules
 115 https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/remap_dct_yield.py;hb=HEAD
 116 i use it to auto-generate the SVG DCT diagrams used in this talk :)
 117 https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/dct_butterfly_svg.py;hb=HEAD
 118 https://www.youtube.com/watch?v=fn2KJvWyBKg
 119 trying to explain it without a slide, sigh :)
 120 it's in the video
 121 here's the unit test for draft svp64 dct
 122 https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/isa/test_caller_svp64_dct.py;hb=HEAD
 123 i meant, 25% :)
 124 they added a transpose-matrix instruction to turn 3x4 into 4x3
 125 it might have been NEON that ARM added that to, rather than MALI
 126
 127 Andrey:
 128 First time I heard about REP instruction (my knowledge of x86 is like a drop in the ocean), so perhaps a link might be useful:
 129 https://www.aldeid.com/wiki/X86-assembly/Instructions/rep
 130
 131 ```
 132
 133 # Abstract
 134
 135 *Draft SVP64 in-place Matrix Multiply and FFT / DCT for OpenPOWER*
 136
 137 Advanced Cray-style Vectors are being developed for the Power ISA, as a
 138 Draft Extension for submission to the new OpenPOWER ISA Working Group,
 139 named SVP64.  Whilst in-place Matrix Multiply was planned for a much
 140 later advanced version of SVP64, an investigation into putting FFMPEG's
 141 MP3 CODEC inner loop into Vectorised Assembler resulted in such a large
 142 drop in code size (over 4x reduction) that it warranted priority
 143 investigation.
 144
 145 Discrete Cosine Transform (DCT), Discrete Fourier Transform (DFT)
 146 and Number-Theory Transform (NTT) form the basis of too numerous
 147 high-priority algorithms to count.  Normal SIMD Processors and even
 148 normal Vector Processors have a hard time dealing with them: inspecting
 149 FFMPEG's source code reveals that heavily optimised inline assembler (no
 150 loops, just hundreds to thousands of lines of assembler) is not uncommon.
 151
 152 The focus of this NLnet-sponsored research is therefore to create enhancements
 153 to SVP64 to be able to cover DFT, DCT, NTT and Matrix-Multiply entirely
 154 in-place.  In-place is crucially important for many applications (3D, Video)
 155 to keep power consumption down by avoiding register spill as well as L1/L2
 156 cache strip-mining.  General-purpose RADIX-2 DCT and complex DFT will be
 157 shown and explained, as well as the in-place Matrix Multiply which does
 158 not require transposing or register spill for any sized Matrices
 159 (including non-power-two) up to 128 FMACs.  The basics of SVP64, covered
 160 in the Overview [1], will also be briefly described.
 161
 162 [1] https://libre-soc.org/openpower/sv/overview/