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8 \title{The Libre-SOC Hybrid
3D CPU
}
9 \author{Luke Kenneth Casson Leighton
}
16 \huge{The Libre-SOC Hybrid
3D CPU
}\\
18 \Large{Update on the Libre-SOC Core
}\\
19 \Large{Peripheral Fabric plans
}\\
20 \Large{and next steps
}\\
22 \large{Sponsored by NLnet and NGI POINTER
}\\
23 \large{under EU Grants
825310 and
825322
31 \frame{\frametitle{What's done already
}
33 \item 180 nm Test ASIC,
30 mm2,
130k Cells,
800k transistors\\
34 Implemented SFS (integer)
64-bit Power ISA
3.0B (ppc64le/be)
35 \item Created an IEEE764 FP Pipeline with ADD, MUL, SQRT, DIV
36 and CORDIC-based SIN/COS.
37 \item Created a Dynamic Partitionable SIMD infrastructure \\
38 using OO python-based nMigen
\textsuperscript{TM
} HDL
39 \item Thousands of unit tests at every level.
40 \item Machine-readable version of the Power ISA Specification \\
41 and a python-based Power ISA Simulator that uses it.\\
42 (including a RADIX MMU)
43 \item A basic implementation of Draft SVP64 with a lot of demos\\
44 including Matrix Multiply, DSP/VLIW-like FFT and DCT
48 \frame{\frametitle{Where we would like to get
}
51 \item Multi-core SMP high-end Superscalar Multi-issue OoO \\
52 that knocks the stuffing out of everything on the market \\
53 for performance and performance/watt\\
54 (and doing so efficiently and cleanly at the ISA level)\\
56 \item Introduce
3D GPU, Video and other accelerated tasks \\
57 as first-class citizens to the Power ISA \\
58 (i.e. not require a separate core) \\
60 \item Advance SVP64 to include Extra-V, Zero-Overhead Loops \\
61 (suitable for Multi-issue), Coherent Graph/Node Processing,
62 Large Matrices, Large FFT/DCT
64 \item Basically Extend and Supercharge the Power ISA \\
66 \item This is a lot of work! \\
71 \frame{\frametitle{Where we are now (what's underway)
}
74 \item Verilator, nmigen and Icarus Verilog simulations \\
75 which include Microwatt for interoperability
76 \item A new single-issue in-order Core using the exact \\
77 same pipelines already from the Test Core
78 \item Passing Microwatt unit tests in verilator simulation \\
79 (MMU, XICS, Timer/Dec, helloworld, micropython) \\
80 Buildroot Linux-
5.7 run for
20 hours
81 \item Running in FPGAs: VERSA
\_ECP5, ULX3S. \\
82 TODO: Arty A7-
100t, Orange-Crab.
83 \item New nMigen-based Peripheral Fabric, with a nMigen-based
84 DDR3 DRAM Controller, Opencores
16550,
10/
100 MAC \\
85 JTAG Boundary Scan, Pinmux: all Designed-for-Test
86 \item New Power ISA Simulator underway (Power ISA cavatools)
90 \frame{\frametitle{Funding and timescales
}
95 \item EUR
200,
000 from NGI POINTER, deadline Oct
1st
2022 \\
97 \item EUR
250,
000 from NLnet, deadline Oct
1st
2022 \\
99 \item EUR
150,
000 from NLnet (Assure Program). \\
101 \item Need help! Money available. \\
103 \item Everything is Libre-Licensed (LGPLv3+ the default license). \\
104 https://libre-soc.org
113 Thank you
\vspace{12pt
}\\
114 Questions?
\vspace{12pt
}
119 \item Discussion: http://lists.libre-soc.org
120 \item Libera Chat IRC \#libre-soc
121 \item http://libre-soc.org/
122 \item http://nlnet.nl/PET
123 \item https://libre-soc.org/nlnet/\#faq