1 \documentclass[slidestop
]{beamer
}
2 \usepackage{beamerthemesplit
}
8 \title{The Libre-SOC Hybrid CPU-VPU-GPU
}
9 \author{Luke Kenneth Casson Leighton
}
16 \huge{The Libre-SOC Hybrid CPU-VPU-GPU
}\\
18 \Large{and why Libre/Open is crucial
}\\
19 \Large{(even in a business context)
}\\
20 \Large{Practical gotchas for Silicon Transparency
}\\
22 \Large{Silicon Salon
2022}\\
24 \large{Sponsored by NLnet's PET Programme
}\\
31 \frame{\frametitle{What is the Libre-SOC Project
}
34 \item An entirely Libre Vector-enhanced Power ISA compliant
35 CPU with enough legs to tackle Supercomputing-class
38 \item Working closely with the OpenPOWER Foundation: no
39 rogue custom instructions. Both Long-term stability and
42 \item Huge reliance on Python OO and Software Engineering as
43 applied to HDL. Not just traditional Verification: unit
44 tests at every level, Formal Correctness Proofs as unit
45 tests. "python3 setup.py test"
47 \item Using Libre VLSI Tools: coriolis2 (by Sorbonne University)
48 ultimate goal is to have the GDS-II Files publicly reproducible
55 \frame{\frametitle{What challenges does a Crypto-Wallet ASIC face?
}
58 \item Industry-endemic paranoid
5-level-deep NDA Chain. Foundry NDAs
59 themselves are under NDA. Sharing between teams inside the same
60 company is prohibited! Cell Libraries: NDA'd. PDKs: NDA'd.
63 \item Power-analysis attacks. Timing attacks. EMF attacks. Standards
64 Verification (FIPS ain't it). Toolchain attacks. Cacheing is out:
65 performance will suck.
67 \item Achieving Full Transparency - a critical goal - is almost impossible
68 to achieve. Ultimately, you need to buy (or build) your own Foundry.
70 \item Production and Development costs (NREs) almost certainly dwarf the
77 \frame{\frametitle{Pragmatic solutions
}
80 \item Use Formal Correctness Proofs at every step. Caveat: proofs are
81 only as good as the mathematicians that write them!
83 \item Work with Standards bodies (e.g. OpenPOWER Foundation ISA WG) and
84 Members with similar interests.
85 Custom Extension with zero public review == bad.
87 \item Unstable PLLs to detect rogue EMF
89 \item Develop a product that has a larger total market (an SoC)
91 \item Accept that some levels of NDA are "out of reach" for now.
93 \item Use E-Fabless "ChipIgnite" to at least get the NREs down.
95 \item Ultimately: buy your own Foundry, make the PDK and Cell Library public.
96 Only use Libre VLSI tools (limits to around
130 nm at the moment).
97 Everything is "early days" in this space
105 {\Huge The end
\vspace{12pt
}\\
106 Thank you
\vspace{12pt
}\\
107 Questions?
\vspace{12pt
}
112 \item Discussion: http://lists.libre-soc.org
113 \item Libera.Chat IRC \#libre-soc
114 \item http://libre-soc.org/
115 \item http://nlnet.nl/PET
116 \item https://libre-soc.org/nlnet/\#faq