conferences.mdwn

   1 # 2020 Jun FSic2020 Eth Zurich, Switzerland
   2
   3 <https://wiki.f-si.org/index.php/FSiC2020>
   4
   5 # 2020 Jun OpenPOWER Summit North America.
   6
   7 25 and 26 June we'll be in lovely Austin, TX, the same week and venue as the Linux Foundation's Open Source Summit.
   8
   9 # To keep an eye on:
  10
  11 * <https://www.iscaconf.org/>
  12
  13 # XDC 2020
  14
  15 * <https://xdc2020.x.org/event/9/abstracts/>
  16 [[conferences/xdc2020]]
  17
  18 # OpenPOWER 2020
  19
  20 * <https://linuxfoundation.smapply.io/prog/openpower_na_2020/>
  21 * <https://openpowerna2020.sched.com/>
  22 * <https://openpowerna2020.sched.com/event/eDqa/the-libresoc-initiative-a-hybrid-cpuvpugpu-luke-leighton-libresoc?iframe=no&w=100%&sidebar=yes&bg=no>
  23
  24 # SFSCON 2020, italy
  25
  26 * <http://sfscon.it/> - Roberto PPC64 Notebook
  27 * <https://www.sfscon.it/talks/202x-open-hardware-concrete-approach/>
  28
  29 ## Why a Libre 3D CPU / GPU / VPU?
  30
  31 * Study of SoCs (Allwinner, Rockchip, NXP) shows none are fully Libre
  32   - Either GPU driver firmware is proprietary, or VPU firmware, or bootloader
  33 * This causes customer product development issues
  34   - https://tinyurl.com/valve-steam-intel
  35 * Businesses are waking up to lack of transparency
  36   - Intel Management Engine (spying backdoor co-processor)
  37   - Spectre, Meltdown, CSME (Chain-of-Trust) issues
  38 * Solution: full transparency.  All source available for everything.
  39
  40 ## How is LibreSOC being developed?
  41
  42 * Using Libre (rather than "open") development practices
  43   - no "I'll release it when it's ready": all development is real-time public access
  44 * No NDAs, no hidden discussions
  45   - we can invite anyone (any expert) to help with review
  46   - free to ask for help anywhere in the world (comp.arch, stackexchange)
  47 * Using litex, nmigen, opencores HDL
  48   - heavily depending on python OO (not possible with VHDL or Verilog)
  49   - leap-frogging ahead by not reinventing the wheel
  50
  51 ## What is being developed? Roadmap
  52
  53 * First simple core achieved in simulation Sep 2020
  54   - FPGA (ECP5) target followed shortly
  55 * First silicon tape-out 180nm deadline 2nd Dec 2020
  56   - sponsored by NLnet, with help from Chips4Makers Libre Cell Libraries
  57   - layout is entirely libre-licensed tools: coriolis2 from lip6.fr
  58 * Next chip is "SBC" style quad-core
  59   - similar spec to Allwinner A64, Rockchip RK3399
  60   - targets "Pi" boards, smartphones, tablets, Industrial IoT
  61
  62 ## Contact
  63
  64 * Freenode IRC #libre-soc
  65 * Website https://libre-soc.org
  66   - mailing list, git repos, bugtracker etc.
  67