1 # Copyright (c) 2012-2013 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
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11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2010 Advanced Micro Devices, Inc.
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41 # Configure the M5 cache hierarchy config in one place
45 from m5
.objects
import *
48 def config_cache(options
, system
):
49 if options
.cpu_type
== "arm_detailed":
51 from O3_ARM_v7a
import *
53 print "arm_detailed is unavailable. Did you compile the O3 model?"
56 dcache_class
, icache_class
, l2_cache_class
= \
57 O3_ARM_v7a_DCache
, O3_ARM_v7a_ICache
, O3_ARM_v7aL2
59 dcache_class
, icache_class
, l2_cache_class
= \
60 L1Cache
, L1Cache
, L2Cache
62 # Set the cache line size of the system
63 system
.cache_line_size
= options
.cacheline_size
66 # Provide a clock for the L2 and the L1-to-L2 bus here as they
67 # are not connected using addTwoLevelCacheHierarchy. Use the
68 # same clock as the CPUs, and set the L1-to-L2 bus width to 32
70 system
.l2
= l2_cache_class(clk_domain
=system
.cpu_clk_domain
,
72 assoc
=options
.l2_assoc
)
74 system
.tol2bus
= CoherentXBar(clk_domain
= system
.cpu_clk_domain
,
76 system
.l2
.cpu_side
= system
.tol2bus
.master
77 system
.l2
.mem_side
= system
.membus
.slave
79 for i
in xrange(options
.num_cpus
):
81 icache
= icache_class(size
=options
.l1i_size
,
82 assoc
=options
.l1i_assoc
)
83 dcache
= dcache_class(size
=options
.l1d_size
,
84 assoc
=options
.l1d_assoc
)
86 # When connecting the caches, the clock is also inherited
87 # from the CPU in question
88 if buildEnv
['TARGET_ISA'] == 'x86':
89 system
.cpu
[i
].addPrivateSplitL1Caches(icache
, dcache
,
90 PageTableWalkerCache(),
91 PageTableWalkerCache())
93 system
.cpu
[i
].addPrivateSplitL1Caches(icache
, dcache
)
94 system
.cpu
[i
].createInterruptController()
96 system
.cpu
[i
].connectAllPorts(system
.tol2bus
, system
.membus
)
98 system
.cpu
[i
].connectAllPorts(system
.membus
)