configs/common/CacheConfig.py

   1 # Copyright (c) 2012-2013, 2015-2016 ARM Limited
   2 # All rights reserved
   3 #
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  13 # Copyright (c) 2010 Advanced Micro Devices, Inc.
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  38
  39 # Configure the M5 cache hierarchy config in one place
  40 #
  41
  42 from __future__ import print_function
  43 from __future__ import absolute_import
  44
  45 import m5
  46 from m5.objects import *
  47 from .Caches import *
  48 from common import ObjectList
  49
  50 def config_cache(options, system):
  51     if options.external_memory_system and (options.caches or options.l2cache):
  52         print("External caches and internal caches are exclusive options.\n")
  53         sys.exit(1)
  54
  55     if options.external_memory_system:
  56         ExternalCache = ExternalCacheFactory(options.external_memory_system)
  57
  58     if options.cpu_type == "O3_ARM_v7a_3":
  59         try:
  60             import cores.arm.O3_ARM_v7a as core
  61         except:
  62             print("O3_ARM_v7a_3 is unavailable. Did you compile the O3 model?")
  63             sys.exit(1)
  64
  65         dcache_class, icache_class, l2_cache_class, walk_cache_class = \
  66             core.O3_ARM_v7a_DCache, core.O3_ARM_v7a_ICache, \
  67             core.O3_ARM_v7aL2, \
  68             core.O3_ARM_v7aWalkCache
  69     elif options.cpu_type == "HPI":
  70         try:
  71             import cores.arm.HPI as core
  72         except:
  73             print("HPI is unavailable.")
  74             sys.exit(1)
  75
  76         dcache_class, icache_class, l2_cache_class, walk_cache_class = \
  77             core.HPI_DCache, core.HPI_ICache, core.HPI_L2, core.HPI_WalkCache
  78     else:
  79         dcache_class, icache_class, l2_cache_class, walk_cache_class = \
  80             L1_DCache, L1_ICache, L2Cache, None
  81
  82         if buildEnv['TARGET_ISA'] == 'x86':
  83             walk_cache_class = PageTableWalkerCache
  84
  85     # Set the cache line size of the system
  86     system.cache_line_size = options.cacheline_size
  87
  88     # If elastic trace generation is enabled, make sure the memory system is
  89     # minimal so that compute delays do not include memory access latencies.
  90     # Configure the compulsory L1 caches for the O3CPU, do not configure
  91     # any more caches.
  92     if options.l2cache and options.elastic_trace_en:
  93         fatal("When elastic trace is enabled, do not configure L2 caches.")
  94
  95     if options.l2cache:
  96         # Provide a clock for the L2 and the L1-to-L2 bus here as they
  97         # are not connected using addTwoLevelCacheHierarchy. Use the
  98         # same clock as the CPUs.
  99         system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
 100                                    size=options.l2_size,
 101                                    assoc=options.l2_assoc)
 102
 103         system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
 104         system.l2.cpu_side = system.tol2bus.master
 105         system.l2.mem_side = system.membus.slave
 106         if options.l2_hwp_type:
 107             hwpClass = ObjectList.hwp_list.get(options.l2_hwp_type)
 108             if system.l2.prefetcher != "Null":
 109                 print("Warning: l2-hwp-type is set (", hwpClass, "), but",
 110                       "the current l2 has a default Hardware Prefetcher",
 111                       "of type", type(system.l2.prefetcher), ", using the",
 112                       "specified by the flag option.")
 113             system.l2.prefetcher = hwpClass()
 114
 115     if options.memchecker:
 116         system.memchecker = MemChecker()
 117
 118     for i in range(options.num_cpus):
 119         if options.caches:
 120             icache = icache_class(size=options.l1i_size,
 121                                   assoc=options.l1i_assoc)
 122             dcache = dcache_class(size=options.l1d_size,
 123                                   assoc=options.l1d_assoc)
 124
 125             # If we have a walker cache specified, instantiate two
 126             # instances here
 127             if walk_cache_class:
 128                 iwalkcache = walk_cache_class()
 129                 dwalkcache = walk_cache_class()
 130             else:
 131                 iwalkcache = None
 132                 dwalkcache = None
 133
 134             if options.memchecker:
 135                 dcache_mon = MemCheckerMonitor(warn_only=True)
 136                 dcache_real = dcache
 137
 138                 # Do not pass the memchecker into the constructor of
 139                 # MemCheckerMonitor, as it would create a copy; we require
 140                 # exactly one MemChecker instance.
 141                 dcache_mon.memchecker = system.memchecker
 142
 143                 # Connect monitor
 144                 dcache_mon.mem_side = dcache.cpu_side
 145
 146                 # Let CPU connect to monitors
 147                 dcache = dcache_mon
 148
 149             if options.l1d_hwp_type:
 150                 hwpClass = ObjectList.hwp_list.get(options.l1d_hwp_type)
 151                 if dcache.prefetcher != m5.params.NULL:
 152                     print("Warning: l1d-hwp-type is set (", hwpClass, "), but",
 153                           "the current l1d has a default Hardware Prefetcher",
 154                           "of type", type(dcache.prefetcher), ", using the",
 155                           "specified by the flag option.")
 156                 dcache.prefetcher = hwpClass()
 157
 158             if options.l1i_hwp_type:
 159                 hwpClass = ObjectList.hwp_list.get(options.l1i_hwp_type)
 160                 if icache.prefetcher != m5.params.NULL:
 161                     print("Warning: l1i-hwp-type is set (", hwpClass, "), but",
 162                           "the current l1i has a default Hardware Prefetcher",
 163                           "of type", type(icache.prefetcher), ", using the",
 164                           "specified by the flag option.")
 165                 icache.prefetcher = hwpClass()
 166
 167             # When connecting the caches, the clock is also inherited
 168             # from the CPU in question
 169             system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
 170                                                   iwalkcache, dwalkcache)
 171
 172             if options.memchecker:
 173                 # The mem_side ports of the caches haven't been connected yet.
 174                 # Make sure connectAllPorts connects the right objects.
 175                 system.cpu[i].dcache = dcache_real
 176                 system.cpu[i].dcache_mon = dcache_mon
 177
 178         elif options.external_memory_system:
 179             # These port names are presented to whatever 'external' system
 180             # gem5 is connecting to.  Its configuration will likely depend
 181             # on these names.  For simplicity, we would advise configuring
 182             # it to use this naming scheme; if this isn't possible, change
 183             # the names below.
 184             if buildEnv['TARGET_ISA'] in ['x86', 'arm']:
 185                 system.cpu[i].addPrivateSplitL1Caches(
 186                         ExternalCache("cpu%d.icache" % i),
 187                         ExternalCache("cpu%d.dcache" % i),
 188                         ExternalCache("cpu%d.itb_walker_cache" % i),
 189                         ExternalCache("cpu%d.dtb_walker_cache" % i))
 190             else:
 191                 system.cpu[i].addPrivateSplitL1Caches(
 192                         ExternalCache("cpu%d.icache" % i),
 193                         ExternalCache("cpu%d.dcache" % i))
 194
 195         system.cpu[i].createInterruptController()
 196         if options.l2cache:
 197             system.cpu[i].connectAllPorts(system.tol2bus, system.membus)
 198         elif options.external_memory_system:
 199             system.cpu[i].connectUncachedPorts(system.membus)
 200         else:
 201             system.cpu[i].connectAllPorts(system.membus)
 202
 203     return system
 204
 205 # ExternalSlave provides a "port", but when that port connects to a cache,
 206 # the connecting CPU SimObject wants to refer to its "cpu_side".
 207 # The 'ExternalCache' class provides this adaptation by rewriting the name,
 208 # eliminating distracting changes elsewhere in the config code.
 209 class ExternalCache(ExternalSlave):
 210     def __getattr__(cls, attr):
 211         if (attr == "cpu_side"):
 212             attr = "port"
 213         return super(ExternalSlave, cls).__getattr__(attr)
 214
 215     def __setattr__(cls, attr, value):
 216         if (attr == "cpu_side"):
 217             attr = "port"
 218         return super(ExternalSlave, cls).__setattr__(attr, value)
 219
 220 def ExternalCacheFactory(port_type):
 221     def make(name):
 222         return ExternalCache(port_data=name, port_type=port_type,
 223                              addr_ranges=[AllMemory])
 224     return make