1 # Copyright (c) 2012 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
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11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2006-2007 The Regents of The University of Michigan
14 # All rights reserved.
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17 # modification, are permitted provided that the following conditions are
18 # met: redistributions of source code must retain the above copyright
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20 # redistributions in binary form must reproduce the above copyright
21 # notice, this list of conditions and the following disclaimer in the
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23 # neither the name of the copyright holders nor the names of its
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25 # this software without specific prior written permission.
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41 from m5
.objects
import *
43 # Base implementations of L1, L2, IO and TLB-walker caches. There are
44 # used in the regressions and also as base components in the
45 # system-configuration scripts. The values are meant to serve as a
46 # starting point, and specific parameters can be overridden in the
47 # specific instantiations.
49 class L1Cache(BaseCache
):
57 class L1_ICache(L1Cache
):
60 class L1_DCache(L1Cache
):
63 class L2Cache(BaseCache
):
71 class IOCache(BaseCache
):
78 forward_snoops
= False
81 class PageTableWalkerCache(BaseCache
):
88 forward_snoops
= False
90 # the x86 table walker actually writes to the table-walker cache
91 if buildEnv
['TARGET_ISA'] == 'x86':