systemc: Implement the sc_*_resolved classes.
[gem5.git] / configs / common / CpuConfig.py
1 # Copyright (c) 2012, 2017-2018 ARM Limited
2 # All rights reserved.
3 #
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
12 #
13 # Redistribution and use in source and binary forms, with or without
14 # modification, are permitted provided that the following conditions are
15 # met: redistributions of source code must retain the above copyright
16 # notice, this list of conditions and the following disclaimer;
17 # redistributions in binary form must reproduce the above copyright
18 # notice, this list of conditions and the following disclaimer in the
19 # documentation and/or other materials provided with the distribution;
20 # neither the name of the copyright holders nor the names of its
21 # contributors may be used to endorse or promote products derived from
22 # this software without specific prior written permission.
23 #
24 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 #
36 # Authors: Andreas Sandberg
37
38 from __future__ import print_function
39
40 from m5 import fatal
41 import m5.objects
42 import inspect
43 import sys
44 from textwrap import TextWrapper
45
46 # Dictionary of mapping names of real CPU models to classes.
47 _cpu_classes = {}
48
49
50 def is_cpu_class(cls):
51 """Determine if a class is a CPU that can be instantiated"""
52
53 # We can't use the normal inspect.isclass because the ParamFactory
54 # and ProxyFactory classes have a tendency to confuse it.
55 try:
56 return issubclass(cls, m5.objects.BaseCPU) and \
57 not cls.abstract and \
58 not issubclass(cls, m5.objects.CheckerCPU)
59 except (TypeError, AttributeError):
60 return False
61
62 def _cpu_subclass_tester(name):
63 cpu_class = getattr(m5.objects, name, None)
64
65 def tester(cls):
66 return cpu_class is not None and cls is not None and \
67 issubclass(cls, cpu_class)
68
69 return tester
70
71 is_kvm_cpu = _cpu_subclass_tester("BaseKvmCPU")
72 is_atomic_cpu = _cpu_subclass_tester("AtomicSimpleCPU")
73
74 def get(name):
75 """Get a CPU class from a user provided class name or alias."""
76
77 try:
78 cpu_class = _cpu_classes[name]
79 return cpu_class
80 except KeyError:
81 print("%s is not a valid CPU model." % (name,))
82 sys.exit(1)
83
84 def print_cpu_list():
85 """Print a list of available CPU classes including their aliases."""
86
87 print("Available CPU classes:")
88 doc_wrapper = TextWrapper(initial_indent="\t\t", subsequent_indent="\t\t")
89 for name, cls in _cpu_classes.items():
90 print("\t%s" % name)
91
92 # Try to extract the class documentation from the class help
93 # string.
94 doc = inspect.getdoc(cls)
95 if doc:
96 for line in doc_wrapper.wrap(doc):
97 print(line)
98
99 def cpu_names():
100 """Return a list of valid CPU names."""
101 return _cpu_classes.keys()
102
103 def config_etrace(cpu_cls, cpu_list, options):
104 if issubclass(cpu_cls, m5.objects.DerivO3CPU):
105 # Assign the same file name to all cpus for now. This must be
106 # revisited when creating elastic traces for multi processor systems.
107 for cpu in cpu_list:
108 # Attach the elastic trace probe listener. Set the protobuf trace
109 # file names. Set the dependency window size equal to the cpu it
110 # is attached to.
111 cpu.traceListener = m5.objects.ElasticTrace(
112 instFetchTraceFile = options.inst_trace_file,
113 dataDepTraceFile = options.data_trace_file,
114 depWindowSize = 3 * cpu.numROBEntries)
115 # Make the number of entries in the ROB, LQ and SQ very
116 # large so that there are no stalls due to resource
117 # limitation as such stalls will get captured in the trace
118 # as compute delay. For replay, ROB, LQ and SQ sizes are
119 # modelled in the Trace CPU.
120 cpu.numROBEntries = 512;
121 cpu.LQEntries = 128;
122 cpu.SQEntries = 128;
123 else:
124 fatal("%s does not support data dependency tracing. Use a CPU model of"
125 " type or inherited from DerivO3CPU.", cpu_cls)
126
127 # Add all CPUs in the object hierarchy.
128 for name, cls in inspect.getmembers(m5.objects, is_cpu_class):
129 _cpu_classes[name] = cls
130
131
132 from m5.defines import buildEnv
133 from importlib import import_module
134 for package in [ "generic", buildEnv['TARGET_ISA']]:
135 try:
136 package = import_module(".cores." + package, package=__package__)
137 except ImportError:
138 # No timing models for this ISA
139 continue
140
141 for mod_name, module in inspect.getmembers(package, inspect.ismodule):
142 for name, cls in inspect.getmembers(module, is_cpu_class):
143 _cpu_classes[name] = cls