configs/common/FSConfig.py

   1 # Copyright (c) 2010-2012, 2015-2019 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
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   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
  14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  15 # All rights reserved.
  16 #
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  26 # this software without specific prior written permission.
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  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39
  40 from __future__ import print_function
  41 from __future__ import absolute_import
  42
  43 import m5
  44 from m5.objects import *
  45 from m5.util import *
  46 from common.Benchmarks import *
  47 from common import ObjectList
  48
  49 # Populate to reflect supported os types per target ISA
  50 os_types = { 'mips'  : [ 'linux' ],
  51              'sparc' : [ 'linux' ],
  52              'x86'   : [ 'linux' ],
  53              'arm'   : [ 'linux',
  54                          'android-gingerbread',
  55                          'android-ics',
  56                          'android-jellybean',
  57                          'android-kitkat',
  58                          'android-nougat', ],
  59            }
  60
  61 class CowIdeDisk(IdeDisk):
  62     image = CowDiskImage(child=RawDiskImage(read_only=True),
  63                          read_only=False)
  64
  65     def childImage(self, ci):
  66         self.image.child.image_file = ci
  67
  68 class MemBus(SystemXBar):
  69     badaddr_responder = BadAddr()
  70     default = Self.badaddr_responder.pio
  71
  72 def attach_9p(parent, bus):
  73     viopci = PciVirtIO()
  74     viopci.vio = VirtIO9PDiod()
  75     viodir = os.path.join(m5.options.outdir, '9p')
  76     viopci.vio.root = os.path.join(viodir, 'share')
  77     viopci.vio.socketPath = os.path.join(viodir, 'socket')
  78     if not os.path.exists(viopci.vio.root):
  79         os.makedirs(viopci.vio.root)
  80     if os.path.exists(viopci.vio.socketPath):
  81         os.remove(viopci.vio.socketPath)
  82     parent.viopci = viopci
  83     parent.attachPciDevice(viopci, bus)
  84
  85 def fillInCmdline(mdesc, template, **kwargs):
  86     kwargs.setdefault('rootdev', mdesc.rootdev())
  87     kwargs.setdefault('mem', mdesc.mem())
  88     kwargs.setdefault('script', mdesc.script())
  89     return template % kwargs
  90
  91 def makeCowDisks(disk_paths):
  92     disks = []
  93     for disk_path in disk_paths:
  94         disk = CowIdeDisk(driveID='master')
  95         disk.childImage(disk_path);
  96         disks.append(disk)
  97     return disks
  98
  99 def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
 100     # Constants from iob.cc and uart8250.cc
 101     iob_man_addr = 0x9800000000
 102     uart_pio_size = 8
 103
 104     class CowMmDisk(MmDisk):
 105         image = CowDiskImage(child=RawDiskImage(read_only=True),
 106                              read_only=False)
 107
 108         def childImage(self, ci):
 109             self.image.child.image_file = ci
 110
 111     self = SparcSystem()
 112     if not mdesc:
 113         # generic system
 114         mdesc = SysConfig()
 115     self.readfile = mdesc.script()
 116     self.iobus = IOXBar()
 117     self.membus = MemBus()
 118     self.bridge = Bridge(delay='50ns')
 119     self.t1000 = T1000()
 120     self.t1000.attachOnChipIO(self.membus)
 121     self.t1000.attachIO(self.iobus)
 122     self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
 123                        AddrRange(Addr('2GB'), size ='256MB')]
 124     self.bridge.master = self.iobus.slave
 125     self.bridge.slave = self.membus.master
 126     self.intrctrl = IntrControl()
 127     self.disk0 = CowMmDisk()
 128     self.disk0.childImage(mdesc.disks()[0])
 129     self.disk0.pio = self.iobus.master
 130
 131     # The puart0 and hvuart are placed on the IO bus, so create ranges
 132     # for them. The remaining IO range is rather fragmented, so poke
 133     # holes for the iob and partition descriptors etc.
 134     self.bridge.ranges = \
 135         [
 136         AddrRange(self.t1000.puart0.pio_addr,
 137                   self.t1000.puart0.pio_addr + uart_pio_size - 1),
 138         AddrRange(self.disk0.pio_addr,
 139                   self.t1000.fake_jbi.pio_addr +
 140                   self.t1000.fake_jbi.pio_size - 1),
 141         AddrRange(self.t1000.fake_clk.pio_addr,
 142                   iob_man_addr - 1),
 143         AddrRange(self.t1000.fake_l2_1.pio_addr,
 144                   self.t1000.fake_ssi.pio_addr +
 145                   self.t1000.fake_ssi.pio_size - 1),
 146         AddrRange(self.t1000.hvuart.pio_addr,
 147                   self.t1000.hvuart.pio_addr + uart_pio_size - 1)
 148         ]
 149
 150     workload = SparcFsWorkload(
 151         reset_bin=binary('reset_new.bin'),
 152         hypervisor_bin=binary('q_new.bin'),
 153         openboot_bin=binary('openboot_new.bin'),
 154         nvram_bin=binary('nvram1'),
 155         hypervisor_desc_bin=binary('1up-hv.bin'),
 156         partition_desc_bin=binary('1up-md.bin'),
 157     )
 158
 159     # ROM for OBP/Reset/Hypervisor
 160     self.rom = SimpleMemory(range=AddrRange(workload._rom_base, size='8MB'))
 161     # nvram
 162     self.nvram = SimpleMemory(
 163             range=AddrRange(workload._nvram_base, size='8kB'))
 164     # hypervisor description
 165     self.hypervisor_desc = SimpleMemory(
 166             range=AddrRange(workload._hypervisor_desc_base, size='8kB'))
 167     # partition description
 168     self.partition_desc = SimpleMemory(
 169             range=AddrRange(workload._partition_desc_base, size='8kB'))
 170
 171     self.rom.port = self.membus.master
 172     self.nvram.port = self.membus.master
 173     self.hypervisor_desc.port = self.membus.master
 174     self.partition_desc.port = self.membus.master
 175
 176     self.system_port = self.membus.slave
 177
 178     self.workload = workload
 179
 180     return self
 181
 182 def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
 183                   dtb_filename=None, bare_metal=False, cmdline=None,
 184                   external_memory="", ruby=False, security=False,
 185                   vio_9p=None, bootloader=None):
 186     assert machine_type
 187
 188     pci_devices = []
 189
 190     self = ArmSystem()
 191
 192     if not mdesc:
 193         # generic system
 194         mdesc = SysConfig()
 195
 196     self.readfile = mdesc.script()
 197     self.iobus = IOXBar()
 198     if not ruby:
 199         self.bridge = Bridge(delay='50ns')
 200         self.bridge.master = self.iobus.slave
 201         self.membus = MemBus()
 202         self.membus.badaddr_responder.warn_access = "warn"
 203         self.bridge.slave = self.membus.master
 204
 205     self.mem_mode = mem_mode
 206
 207     platform_class = ObjectList.platform_list.get(machine_type)
 208     # Resolve the real platform name, the original machine_type
 209     # variable might have been an alias.
 210     machine_type = platform_class.__name__
 211     self.realview = platform_class()
 212     self._bootmem = self.realview.bootmem
 213
 214     if isinstance(self.realview, VExpress_EMM64):
 215         if os.path.split(mdesc.disks()[0])[-1] == 'linux-aarch32-ael.img':
 216             print("Selected 64-bit ARM architecture, updating default "
 217                   "disk image...")
 218             mdesc.diskname = 'linaro-minimal-aarch64.img'
 219
 220
 221     # Attach any PCI devices this platform supports
 222     self.realview.attachPciDevices()
 223
 224     disks = makeCowDisks(mdesc.disks())
 225     # Old platforms have a built-in IDE or CF controller. Default to
 226     # the IDE controller if both exist. New platforms expect the
 227     # storage controller to be added from the config script.
 228     if hasattr(self.realview, "ide"):
 229         self.realview.ide.disks = disks
 230     elif hasattr(self.realview, "cf_ctrl"):
 231         self.realview.cf_ctrl.disks = disks
 232     else:
 233         self.pci_ide = IdeController(disks=disks)
 234         pci_devices.append(self.pci_ide)
 235
 236     self.mem_ranges = []
 237     size_remain = long(Addr(mdesc.mem()))
 238     for region in self.realview._mem_regions:
 239         if size_remain > long(region.size()):
 240             self.mem_ranges.append(region)
 241             size_remain = size_remain - long(region.size())
 242         else:
 243             self.mem_ranges.append(AddrRange(region.start, size=size_remain))
 244             size_remain = 0
 245             break
 246         warn("Memory size specified spans more than one region. Creating" \
 247              " another memory controller for that range.")
 248
 249     if size_remain > 0:
 250         fatal("The currently selected ARM platforms doesn't support" \
 251               " the amount of DRAM you've selected. Please try" \
 252               " another platform")
 253
 254     self.have_security = security
 255
 256     if bare_metal:
 257         # EOT character on UART will end the simulation
 258         self.realview.uart[0].end_on_eot = True
 259     else:
 260         workload = ArmFsLinux()
 261
 262         if dtb_filename:
 263             workload.dtb_filename = binary(dtb_filename)
 264
 265         workload.machine_type = \
 266             machine_type if machine_type in ArmMachineType.map else "DTOnly"
 267
 268         # Ensure that writes to the UART actually go out early in the boot
 269         if not cmdline:
 270             cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
 271                       'lpj=19988480 norandmaps rw loglevel=8 ' + \
 272                       'mem=%(mem)s root=%(rootdev)s'
 273
 274         if hasattr(self.realview.gic, 'cpu_addr'):
 275             self.gic_cpu_addr = self.realview.gic.cpu_addr
 276
 277         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 278
 279         # This check is for users who have previously put 'android' in
 280         # the disk image filename to tell the config scripts to
 281         # prepare the kernel with android-specific boot options. That
 282         # behavior has been replaced with a more explicit option per
 283         # the error message below. The disk can have any name now and
 284         # doesn't need to include 'android' substring.
 285         if (mdesc.disks() and
 286                 os.path.split(mdesc.disks()[0])[-1]).lower().count('android'):
 287             if 'android' not in mdesc.os_type():
 288                 fatal("It looks like you are trying to boot an Android " \
 289                       "platform.  To boot Android, you must specify " \
 290                       "--os-type with an appropriate Android release on " \
 291                       "the command line.")
 292
 293         # android-specific tweaks
 294         if 'android' in mdesc.os_type():
 295             # generic tweaks
 296             cmdline += " init=/init"
 297
 298             # release-specific tweaks
 299             if 'kitkat' in mdesc.os_type():
 300                 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
 301                            "android.bootanim=0 "
 302             elif 'nougat' in mdesc.os_type():
 303                 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
 304                            "android.bootanim=0 " + \
 305                            "vmalloc=640MB " + \
 306                            "android.early.fstab=/fstab.gem5 " + \
 307                            "androidboot.selinux=permissive " + \
 308                            "video=Virtual-1:1920x1080-16"
 309
 310         workload.command_line = fillInCmdline(mdesc, cmdline)
 311
 312         self.workload = workload
 313
 314         self.realview.setupBootLoader(self, binary, bootloader)
 315
 316     if external_memory:
 317         # I/O traffic enters iobus
 318         self.external_io = ExternalMaster(port_data="external_io",
 319                                           port_type=external_memory)
 320         self.external_io.port = self.iobus.slave
 321
 322         # Ensure iocache only receives traffic destined for (actual) memory.
 323         self.iocache = ExternalSlave(port_data="iocache",
 324                                      port_type=external_memory,
 325                                      addr_ranges=self.mem_ranges)
 326         self.iocache.port = self.iobus.master
 327
 328         # Let system_port get to nvmem and nothing else.
 329         self.bridge.ranges = [self.realview.nvmem.range]
 330
 331         self.realview.attachOnChipIO(self.iobus)
 332         # Attach off-chip devices
 333         self.realview.attachIO(self.iobus)
 334     elif ruby:
 335         self._dma_ports = [ ]
 336         self._mem_ports = [ ]
 337         self.realview.attachOnChipIO(self.iobus,
 338             dma_ports=self._dma_ports, mem_ports=self._mem_ports)
 339         self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
 340     else:
 341         self.realview.attachOnChipIO(self.membus, self.bridge)
 342         # Attach off-chip devices
 343         self.realview.attachIO(self.iobus)
 344
 345     for dev in pci_devices:
 346         self.realview.attachPciDevice(
 347             dev, self.iobus,
 348             dma_ports=self._dma_ports if ruby else None)
 349
 350     self.intrctrl = IntrControl()
 351     self.terminal = Terminal()
 352     self.vncserver = VncServer()
 353
 354     if vio_9p:
 355         attach_9p(self.realview, self.iobus)
 356
 357     if not ruby:
 358         self.system_port = self.membus.slave
 359
 360     if ruby:
 361         if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
 362             fatal("The MI_example protocol cannot implement Load/Store "
 363                   "Exclusive operations. Multicore ARM systems configured "
 364                   "with the MI_example protocol will not work properly.")
 365         warn("You are trying to use Ruby on ARM, which is not working "
 366              "properly yet.")
 367
 368     return self
 369
 370
 371 def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
 372     class BaseMalta(Malta):
 373         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 374         ide = IdeController(disks=Parent.disks,
 375                             pci_func=0, pci_dev=0, pci_bus=0)
 376
 377     self = LinuxMipsSystem()
 378     if not mdesc:
 379         # generic system
 380         mdesc = SysConfig()
 381     self.readfile = mdesc.script()
 382     self.iobus = IOXBar()
 383     self.membus = MemBus()
 384     self.bridge = Bridge(delay='50ns')
 385     self.mem_ranges = [AddrRange('1GB')]
 386     self.bridge.master = self.iobus.slave
 387     self.bridge.slave = self.membus.master
 388     self.disks = makeCowDisks(mdesc.disks())
 389     self.malta = BaseMalta()
 390     self.malta.attachIO(self.iobus)
 391     self.malta.ide.pio = self.iobus.master
 392     self.malta.ide.dma = self.iobus.slave
 393     self.malta.ethernet.pio = self.iobus.master
 394     self.malta.ethernet.dma = self.iobus.slave
 395     self.simple_disk = SimpleDisk(disk=RawDiskImage(
 396         image_file = mdesc.disks()[0], read_only = True))
 397     self.intrctrl = IntrControl()
 398     self.mem_mode = mem_mode
 399     self.terminal = Terminal()
 400     self.console = binary('mips/console')
 401     if not cmdline:
 402         cmdline = 'root=/dev/hda1 console=ttyS0'
 403     self.workload = OsKernel(command_line=fillInCmdline(mdesc, cmdline))
 404
 405     self.system_port = self.membus.slave
 406
 407     return self
 408
 409 def x86IOAddress(port):
 410     IO_address_space_base = 0x8000000000000000
 411     return IO_address_space_base + port
 412
 413 def connectX86ClassicSystem(x86_sys, numCPUs):
 414     # Constants similar to x86_traits.hh
 415     IO_address_space_base = 0x8000000000000000
 416     pci_config_address_space_base = 0xc000000000000000
 417     interrupts_address_space_base = 0xa000000000000000
 418     APIC_range_size = 1 << 12;
 419
 420     x86_sys.membus = MemBus()
 421
 422     # North Bridge
 423     x86_sys.iobus = IOXBar()
 424     x86_sys.bridge = Bridge(delay='50ns')
 425     x86_sys.bridge.master = x86_sys.iobus.slave
 426     x86_sys.bridge.slave = x86_sys.membus.master
 427     # Allow the bridge to pass through:
 428     #  1) kernel configured PCI device memory map address: address range
 429     #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
 430     #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
 431     #  3) everything in the IO address range up to the local APIC, and
 432     #  4) then the entire PCI address space and beyond.
 433     x86_sys.bridge.ranges = \
 434         [
 435         AddrRange(0xC0000000, 0xFFFF0000),
 436         AddrRange(IO_address_space_base,
 437                   interrupts_address_space_base - 1),
 438         AddrRange(pci_config_address_space_base,
 439                   Addr.max)
 440         ]
 441
 442     # Create a bridge from the IO bus to the memory bus to allow access to
 443     # the local APIC (two pages)
 444     x86_sys.apicbridge = Bridge(delay='50ns')
 445     x86_sys.apicbridge.slave = x86_sys.iobus.master
 446     x86_sys.apicbridge.master = x86_sys.membus.slave
 447     x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
 448                                            interrupts_address_space_base +
 449                                            numCPUs * APIC_range_size
 450                                            - 1)]
 451
 452     # connect the io bus
 453     x86_sys.pc.attachIO(x86_sys.iobus)
 454
 455     x86_sys.system_port = x86_sys.membus.slave
 456
 457 def connectX86RubySystem(x86_sys):
 458     # North Bridge
 459     x86_sys.iobus = IOXBar()
 460
 461     # add the ide to the list of dma devices that later need to attach to
 462     # dma controllers
 463     x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
 464     x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
 465
 466
 467 def makeX86System(mem_mode, numCPUs=1, mdesc=None, workload=None, Ruby=False):
 468     self = X86System()
 469
 470     if workload is None:
 471         workload = X86FsWorkload()
 472     self.workload = workload
 473
 474     if not mdesc:
 475         # generic system
 476         mdesc = SysConfig()
 477     self.readfile = mdesc.script()
 478
 479     self.mem_mode = mem_mode
 480
 481     # Physical memory
 482     # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
 483     # for various devices.  Hence, if the physical memory size is greater than
 484     # 3GB, we need to split it into two parts.
 485     excess_mem_size = \
 486         convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
 487     if excess_mem_size <= 0:
 488         self.mem_ranges = [AddrRange(mdesc.mem())]
 489     else:
 490         warn("Physical memory size specified is %s which is greater than " \
 491              "3GB.  Twice the number of memory controllers would be " \
 492              "created."  % (mdesc.mem()))
 493
 494         self.mem_ranges = [AddrRange('3GB'),
 495             AddrRange(Addr('4GB'), size = excess_mem_size)]
 496
 497     # Platform
 498     self.pc = Pc()
 499
 500     # Create and connect the busses required by each memory system
 501     if Ruby:
 502         connectX86RubySystem(self)
 503     else:
 504         connectX86ClassicSystem(self, numCPUs)
 505
 506     self.intrctrl = IntrControl()
 507
 508     # Disks
 509     disks = makeCowDisks(mdesc.disks())
 510     self.pc.south_bridge.ide.disks = disks
 511
 512     # Add in a Bios information structure.
 513     structures = [X86SMBiosBiosInformation()]
 514     workload.smbios_table.structures = structures
 515
 516     # Set up the Intel MP table
 517     base_entries = []
 518     ext_entries = []
 519     for i in range(numCPUs):
 520         bp = X86IntelMPProcessor(
 521                 local_apic_id = i,
 522                 local_apic_version = 0x14,
 523                 enable = True,
 524                 bootstrap = (i == 0))
 525         base_entries.append(bp)
 526     io_apic = X86IntelMPIOAPIC(
 527             id = numCPUs,
 528             version = 0x11,
 529             enable = True,
 530             address = 0xfec00000)
 531     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 532     base_entries.append(io_apic)
 533     # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
 534     # but linux kernel cannot config PCI device if it was not connected to
 535     # PCI bus, so we fix PCI bus id to 0, and ISA bus id to 1.
 536     pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI   ')
 537     base_entries.append(pci_bus)
 538     isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA   ')
 539     base_entries.append(isa_bus)
 540     connect_busses = X86IntelMPBusHierarchy(bus_id=1,
 541             subtractive_decode=True, parent_bus=0)
 542     ext_entries.append(connect_busses)
 543     pci_dev4_inta = X86IntelMPIOIntAssignment(
 544             interrupt_type = 'INT',
 545             polarity = 'ConformPolarity',
 546             trigger = 'ConformTrigger',
 547             source_bus_id = 0,
 548             source_bus_irq = 0 + (4 << 2),
 549             dest_io_apic_id = io_apic.id,
 550             dest_io_apic_intin = 16)
 551     base_entries.append(pci_dev4_inta)
 552     def assignISAInt(irq, apicPin):
 553         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 554                 interrupt_type = 'ExtInt',
 555                 polarity = 'ConformPolarity',
 556                 trigger = 'ConformTrigger',
 557                 source_bus_id = 1,
 558                 source_bus_irq = irq,
 559                 dest_io_apic_id = io_apic.id,
 560                 dest_io_apic_intin = 0)
 561         base_entries.append(assign_8259_to_apic)
 562         assign_to_apic = X86IntelMPIOIntAssignment(
 563                 interrupt_type = 'INT',
 564                 polarity = 'ConformPolarity',
 565                 trigger = 'ConformTrigger',
 566                 source_bus_id = 1,
 567                 source_bus_irq = irq,
 568                 dest_io_apic_id = io_apic.id,
 569                 dest_io_apic_intin = apicPin)
 570         base_entries.append(assign_to_apic)
 571     assignISAInt(0, 2)
 572     assignISAInt(1, 1)
 573     for i in range(3, 15):
 574         assignISAInt(i, i)
 575     workload.intel_mp_table.base_entries = base_entries
 576     workload.intel_mp_table.ext_entries = ext_entries
 577
 578     return self
 579
 580 def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
 581                        cmdline=None):
 582     # Build up the x86 system and then specialize it for Linux
 583     self = makeX86System(mem_mode, numCPUs, mdesc, X86FsLinux(), Ruby)
 584
 585     # We assume below that there's at least 1MB of memory. We'll require 2
 586     # just to avoid corner cases.
 587     phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
 588     assert(phys_mem_size >= 0x200000)
 589     assert(len(self.mem_ranges) <= 2)
 590
 591     entries = \
 592        [
 593         # Mark the first megabyte of memory as reserved
 594         X86E820Entry(addr = 0, size = '639kB', range_type = 1),
 595         X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
 596         # Mark the rest of physical memory as available
 597         X86E820Entry(addr = 0x100000,
 598                 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
 599                 range_type = 1),
 600         ]
 601
 602     # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
 603     # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
 604     # specific range can pass though bridge to iobus.
 605     if len(self.mem_ranges) == 1:
 606         entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
 607             size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
 608             range_type=2))
 609
 610     # Reserve the last 16kB of the 32-bit address space for the m5op interface
 611     entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
 612
 613     # In case the physical memory is greater than 3GB, we split it into two
 614     # parts and add a separate e820 entry for the second part.  This entry
 615     # starts at 0x100000000,  which is the first address after the space
 616     # reserved for devices.
 617     if len(self.mem_ranges) == 2:
 618         entries.append(X86E820Entry(addr = 0x100000000,
 619             size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
 620
 621     self.workload.e820_table.entries = entries
 622
 623     # Command line
 624     if not cmdline:
 625         cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
 626     self.workload.command_line = fillInCmdline(mdesc, cmdline)
 627     return self
 628
 629
 630 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 631     self = Root(full_system = full_system)
 632     self.testsys = testSystem
 633     self.drivesys = driveSystem
 634     self.etherlink = EtherLink()
 635
 636     if hasattr(testSystem, 'realview'):
 637         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 638         self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
 639     elif hasattr(testSystem, 'tsunami'):
 640         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 641         self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 642     else:
 643         fatal("Don't know how to connect these system together")
 644
 645     if dumpfile:
 646         self.etherdump = EtherDump(file=dumpfile)
 647         self.etherlink.dump = Parent.etherdump
 648
 649     return self
 650
 651
 652 def makeDistRoot(testSystem,
 653                  rank,
 654                  size,
 655                  server_name,
 656                  server_port,
 657                  sync_repeat,
 658                  sync_start,
 659                  linkspeed,
 660                  linkdelay,
 661                  dumpfile):
 662     self = Root(full_system = True)
 663     self.testsys = testSystem
 664
 665     self.etherlink = DistEtherLink(speed = linkspeed,
 666                                    delay = linkdelay,
 667                                    dist_rank = rank,
 668                                    dist_size = size,
 669                                    server_name = server_name,
 670                                    server_port = server_port,
 671                                    sync_start = sync_start,
 672                                    sync_repeat = sync_repeat)
 673
 674     if hasattr(testSystem, 'realview'):
 675         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 676     elif hasattr(testSystem, 'tsunami'):
 677         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 678     else:
 679         fatal("Don't know how to connect DistEtherLink to this system")
 680
 681     if dumpfile:
 682         self.etherdump = EtherDump(file=dumpfile)
 683         self.etherlink.dump = Parent.etherdump
 684
 685     return self