configs/common/FSConfig.py

   1 # Copyright (c) 2010 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
  14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  15 # All rights reserved.
  16 #
  17 # Redistribution and use in source and binary forms, with or without
  18 # modification, are permitted provided that the following conditions are
  19 # met: redistributions of source code must retain the above copyright
  20 # notice, this list of conditions and the following disclaimer;
  21 # redistributions in binary form must reproduce the above copyright
  22 # notice, this list of conditions and the following disclaimer in the
  23 # documentation and/or other materials provided with the distribution;
  24 # neither the name of the copyright holders nor the names of its
  25 # contributors may be used to endorse or promote products derived from
  26 # this software without specific prior written permission.
  27 #
  28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39 #
  40 # Authors: Kevin Lim
  41
  42 from m5.objects import *
  43 from Benchmarks import *
  44
  45 class CowIdeDisk(IdeDisk):
  46     image = CowDiskImage(child=RawDiskImage(read_only=True),
  47                          read_only=False)
  48
  49     def childImage(self, ci):
  50         self.image.child.image_file = ci
  51
  52 class MemBus(Bus):
  53     badaddr_responder = BadAddr()
  54     default = Self.badaddr_responder.pio
  55
  56
  57 def makeLinuxAlphaSystem(mem_mode, mdesc = None):
  58     class BaseTsunami(Tsunami):
  59         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
  60         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
  61                             pci_func=0, pci_dev=0, pci_bus=0)
  62
  63     self = LinuxAlphaSystem()
  64     if not mdesc:
  65         # generic system
  66         mdesc = SysConfig()
  67     self.readfile = mdesc.script()
  68     self.iobus = Bus(bus_id=0)
  69     self.membus = MemBus(bus_id=1)
  70     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
  71     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
  72     self.bridge.side_a = self.iobus.port
  73     self.bridge.side_b = self.membus.port
  74     self.physmem.port = self.membus.port
  75     self.disk0 = CowIdeDisk(driveID='master')
  76     self.disk2 = CowIdeDisk(driveID='master')
  77     self.disk0.childImage(mdesc.disk())
  78     self.disk2.childImage(disk('linux-bigswap2.img'))
  79     self.tsunami = BaseTsunami()
  80     self.tsunami.attachIO(self.iobus)
  81     self.tsunami.ide.pio = self.iobus.port
  82     self.tsunami.ethernet.pio = self.iobus.port
  83     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
  84                                                read_only = True))
  85     self.intrctrl = IntrControl()
  86     self.mem_mode = mem_mode
  87     self.terminal = Terminal()
  88     self.kernel = binary('vmlinux')
  89     self.pal = binary('ts_osfpal')
  90     self.console = binary('console')
  91     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
  92
  93     return self
  94
  95 def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
  96     class BaseTsunami(Tsunami):
  97         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
  98         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
  99                             pci_func=0, pci_dev=0, pci_bus=0)
 100
 101     physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
 102     self = LinuxAlphaSystem(physmem = physmem)
 103     if not mdesc:
 104         # generic system
 105         mdesc = SysConfig()
 106     self.readfile = mdesc.script()
 107
 108     # Create pio bus to connect all device pio ports to rubymem's pio port
 109     self.piobus = Bus(bus_id=0)
 110
 111     #
 112     # Pio functional accesses from devices need direct access to memory
 113     # RubyPort currently does support functional accesses.  Therefore provide
 114     # the piobus a direct connection to physical memory
 115     #
 116     self.piobus.port = physmem.port
 117
 118     self.disk0 = CowIdeDisk(driveID='master')
 119     self.disk2 = CowIdeDisk(driveID='master')
 120     self.disk0.childImage(mdesc.disk())
 121     self.disk2.childImage(disk('linux-bigswap2.img'))
 122     self.tsunami = BaseTsunami()
 123     self.tsunami.attachIO(self.piobus)
 124     self.tsunami.ide.pio = self.piobus.port
 125     self.tsunami.ethernet.pio = self.piobus.port
 126
 127     #
 128     # Store the dma devices for later connection to dma ruby ports.
 129     # Append an underscore to dma_devices to avoid the SimObjectVector check.
 130     #
 131     self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
 132
 133     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 134                                                read_only = True))
 135     self.intrctrl = IntrControl()
 136     self.mem_mode = mem_mode
 137     self.terminal = Terminal()
 138     self.kernel = binary('vmlinux')
 139     self.pal = binary('ts_osfpal')
 140     self.console = binary('console')
 141     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 142
 143     return self
 144
 145 def makeSparcSystem(mem_mode, mdesc = None):
 146     class CowMmDisk(MmDisk):
 147         image = CowDiskImage(child=RawDiskImage(read_only=True),
 148                              read_only=False)
 149
 150         def childImage(self, ci):
 151             self.image.child.image_file = ci
 152
 153     self = SparcSystem()
 154     if not mdesc:
 155         # generic system
 156         mdesc = SysConfig()
 157     self.readfile = mdesc.script()
 158     self.iobus = Bus(bus_id=0)
 159     self.membus = MemBus(bus_id=1)
 160     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
 161     self.t1000 = T1000()
 162     self.t1000.attachOnChipIO(self.membus)
 163     self.t1000.attachIO(self.iobus)
 164     self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
 165     self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
 166     self.bridge.side_a = self.iobus.port
 167     self.bridge.side_b = self.membus.port
 168     self.physmem.port = self.membus.port
 169     self.physmem2.port = self.membus.port
 170     self.rom.port = self.membus.port
 171     self.nvram.port = self.membus.port
 172     self.hypervisor_desc.port = self.membus.port
 173     self.partition_desc.port = self.membus.port
 174     self.intrctrl = IntrControl()
 175     self.disk0 = CowMmDisk()
 176     self.disk0.childImage(disk('disk.s10hw2'))
 177     self.disk0.pio = self.iobus.port
 178     self.reset_bin = binary('reset_new.bin')
 179     self.hypervisor_bin = binary('q_new.bin')
 180     self.openboot_bin = binary('openboot_new.bin')
 181     self.nvram_bin = binary('nvram1')
 182     self.hypervisor_desc_bin = binary('1up-hv.bin')
 183     self.partition_desc_bin = binary('1up-md.bin')
 184
 185     return self
 186
 187 def makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False,
 188         machine_type = None):
 189     if bare_metal:
 190         self = ArmSystem()
 191     else:
 192         self = LinuxArmSystem()
 193
 194     if not mdesc:
 195         # generic system
 196         mdesc = SysConfig()
 197
 198     self.readfile = mdesc.script()
 199     self.iobus = Bus(bus_id=0)
 200     self.membus = MemBus(bus_id=1)
 201     self.membus.badaddr_responder.warn_access = "warn"
 202     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
 203     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
 204     self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'),
 205                                   file = disk('ael-arm.ext2'))
 206     self.bridge.side_a = self.iobus.port
 207     self.bridge.side_b = self.membus.port
 208     self.physmem.port = self.membus.port
 209     self.diskmem.port = self.membus.port
 210
 211     self.mem_mode = mem_mode
 212
 213     #self.cf0 = CowIdeDisk(driveID='master')
 214     #self.cf0.childImage(mdesc.disk())
 215     #self.cf_ctrl = IdeController(disks=[self.cf0],
 216     #                             pci_func = 0, pci_dev = 0, pci_bus = 0,
 217     #                             io_shift = 1, ctrl_offset = 2, Command = 0x1,
 218     #                             BAR0 = 0x18000000, BAR0Size = '16B',
 219     #                             BAR1 = 0x18000100, BAR1Size = '1B',
 220     #                             BAR0LegacyIO = True, BAR1LegacyIO = True,)
 221     #self.cf_ctrl.pio = self.iobus.port
 222
 223     if machine_type == "RealView_PBX":
 224         self.realview = RealViewPBX()
 225     elif machine_type == "RealView_EB":
 226         self.realview = RealViewEB()
 227     else:
 228         print "Unknown Machine Type"
 229         sys.exit(1)
 230
 231     if not bare_metal and machine_type:
 232         self.machine_type = machine_type
 233     elif bare_metal:
 234         self.realview.uart.end_on_eot = True
 235
 236     self.realview.attachOnChipIO(self.membus)
 237     self.realview.attachIO(self.iobus)
 238
 239     self.intrctrl = IntrControl()
 240     self.terminal = Terminal()
 241     self.kernel = binary('vmlinux.arm')
 242     self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' + \
 243                         ' norandmaps slram=slram0,0x8000000,+0x8000000' +      \
 244                         ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0'
 245
 246     return self
 247
 248
 249 def makeLinuxMipsSystem(mem_mode, mdesc = None):
 250     class BaseMalta(Malta):
 251         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 252         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
 253                             pci_func=0, pci_dev=0, pci_bus=0)
 254
 255     self = LinuxMipsSystem()
 256     if not mdesc:
 257         # generic system
 258         mdesc = SysConfig()
 259     self.readfile = mdesc.script()
 260     self.iobus = Bus(bus_id=0)
 261     self.membus = MemBus(bus_id=1)
 262     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
 263     self.physmem = PhysicalMemory(range = AddrRange('1GB'))
 264     self.bridge.side_a = self.iobus.port
 265     self.bridge.side_b = self.membus.port
 266     self.physmem.port = self.membus.port
 267     self.disk0 = CowIdeDisk(driveID='master')
 268     self.disk2 = CowIdeDisk(driveID='master')
 269     self.disk0.childImage(mdesc.disk())
 270     self.disk2.childImage(disk('linux-bigswap2.img'))
 271     self.malta = BaseMalta()
 272     self.malta.attachIO(self.iobus)
 273     self.malta.ide.pio = self.iobus.port
 274     self.malta.ethernet.pio = self.iobus.port
 275     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 276                                                read_only = True))
 277     self.intrctrl = IntrControl()
 278     self.mem_mode = mem_mode
 279     self.terminal = Terminal()
 280     self.kernel = binary('mips/vmlinux')
 281     self.console = binary('mips/console')
 282     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 283
 284     return self
 285
 286 def x86IOAddress(port):
 287     IO_address_space_base = 0x8000000000000000
 288     return IO_address_space_base + port;
 289
 290 def connectX86ClassicSystem(x86_sys):
 291     x86_sys.membus = MemBus(bus_id=1)
 292     x86_sys.physmem.port = x86_sys.membus.port
 293
 294     # North Bridge
 295     x86_sys.iobus = Bus(bus_id=0)
 296     x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
 297     x86_sys.bridge.side_a = x86_sys.iobus.port
 298     x86_sys.bridge.side_b = x86_sys.membus.port
 299
 300     # connect the io bus
 301     x86_sys.pc.attachIO(x86_sys.iobus)
 302
 303 def connectX86RubySystem(x86_sys):
 304     # North Bridge
 305     x86_sys.piobus = Bus(bus_id=0)
 306
 307     #
 308     # Pio functional accesses from devices need direct access to memory
 309     # RubyPort currently does support functional accesses.  Therefore provide
 310     # the piobus a direct connection to physical memory
 311     #
 312     x86_sys.piobus.port = x86_sys.physmem.port
 313
 314     x86_sys.pc.attachIO(x86_sys.piobus)
 315
 316
 317 def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
 318     if self == None:
 319         self = X86System()
 320
 321     if not mdesc:
 322         # generic system
 323         mdesc = SysConfig()
 324     self.readfile = mdesc.script()
 325
 326     self.mem_mode = mem_mode
 327
 328     # Physical memory
 329     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
 330
 331     # Platform
 332     self.pc = Pc()
 333
 334     # Create and connect the busses required by each memory system
 335     if Ruby:
 336         connectX86RubySystem(self)
 337     else:
 338         connectX86ClassicSystem(self)
 339
 340     self.intrctrl = IntrControl()
 341
 342     # Disks
 343     disk0 = CowIdeDisk(driveID='master')
 344     disk2 = CowIdeDisk(driveID='master')
 345     disk0.childImage(mdesc.disk())
 346     disk2.childImage(disk('linux-bigswap2.img'))
 347     self.pc.south_bridge.ide.disks = [disk0, disk2]
 348
 349     # Add in a Bios information structure.
 350     structures = [X86SMBiosBiosInformation()]
 351     self.smbios_table.structures = structures
 352
 353     # Set up the Intel MP table
 354     for i in xrange(numCPUs):
 355         bp = X86IntelMPProcessor(
 356                 local_apic_id = i,
 357                 local_apic_version = 0x14,
 358                 enable = True,
 359                 bootstrap = (i == 0))
 360         self.intel_mp_table.add_entry(bp)
 361     io_apic = X86IntelMPIOAPIC(
 362             id = numCPUs,
 363             version = 0x11,
 364             enable = True,
 365             address = 0xfec00000)
 366     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 367     self.intel_mp_table.add_entry(io_apic)
 368     isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
 369     self.intel_mp_table.add_entry(isa_bus)
 370     pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
 371     self.intel_mp_table.add_entry(pci_bus)
 372     connect_busses = X86IntelMPBusHierarchy(bus_id=0,
 373             subtractive_decode=True, parent_bus=1)
 374     self.intel_mp_table.add_entry(connect_busses)
 375     pci_dev4_inta = X86IntelMPIOIntAssignment(
 376             interrupt_type = 'INT',
 377             polarity = 'ConformPolarity',
 378             trigger = 'ConformTrigger',
 379             source_bus_id = 1,
 380             source_bus_irq = 0 + (4 << 2),
 381             dest_io_apic_id = io_apic.id,
 382             dest_io_apic_intin = 16)
 383     self.intel_mp_table.add_entry(pci_dev4_inta);
 384     def assignISAInt(irq, apicPin):
 385         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 386                 interrupt_type = 'ExtInt',
 387                 polarity = 'ConformPolarity',
 388                 trigger = 'ConformTrigger',
 389                 source_bus_id = 0,
 390                 source_bus_irq = irq,
 391                 dest_io_apic_id = io_apic.id,
 392                 dest_io_apic_intin = 0)
 393         self.intel_mp_table.add_entry(assign_8259_to_apic)
 394         assign_to_apic = X86IntelMPIOIntAssignment(
 395                 interrupt_type = 'INT',
 396                 polarity = 'ConformPolarity',
 397                 trigger = 'ConformTrigger',
 398                 source_bus_id = 0,
 399                 source_bus_irq = irq,
 400                 dest_io_apic_id = io_apic.id,
 401                 dest_io_apic_intin = apicPin)
 402         self.intel_mp_table.add_entry(assign_to_apic)
 403     assignISAInt(0, 2)
 404     assignISAInt(1, 1)
 405     for i in range(3, 15):
 406         assignISAInt(i, i)
 407
 408 def setWorkCountOptions(system, options):
 409     if options.work_item_id != None:
 410         system.work_item_id = options.work_item_id
 411     if options.work_begin_cpu_id_exit != None:
 412         system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
 413     if options.work_end_exit_count != None:
 414         system.work_end_exit_count = options.work_end_exit_count
 415     if options.work_end_checkpoint_count != None:
 416         system.work_end_ckpt_count = options.work_end_checkpoint_count
 417     if options.work_begin_exit_count != None:
 418         system.work_begin_exit_count = options.work_begin_exit_count
 419     if options.work_begin_checkpoint_count != None:
 420         system.work_begin_ckpt_count = options.work_begin_checkpoint_count
 421     if options.work_cpus_checkpoint_count != None:
 422         system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
 423
 424
 425 def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
 426     self = LinuxX86System()
 427
 428     # Build up the x86 system and then specialize it for Linux
 429     makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
 430
 431     # We assume below that there's at least 1MB of memory. We'll require 2
 432     # just to avoid corner cases.
 433     assert(self.physmem.range.second.getValue() >= 0x200000)
 434
 435     # Mark the first megabyte of memory as reserved
 436     self.e820_table.entries.append(X86E820Entry(
 437                 addr = 0,
 438                 size = '1MB',
 439                 range_type = 2))
 440
 441     # Mark the rest as available
 442     self.e820_table.entries.append(X86E820Entry(
 443                 addr = 0x100000,
 444                 size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
 445                 range_type = 1))
 446
 447     # Command line
 448     self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
 449                         'root=/dev/hda1'
 450     return self
 451
 452
 453 def makeDualRoot(testSystem, driveSystem, dumpfile):
 454     self = Root()
 455     self.testsys = testSystem
 456     self.drivesys = driveSystem
 457     self.etherlink = EtherLink()
 458     self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 459     self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 460
 461     if dumpfile:
 462         self.etherdump = EtherDump(file=dumpfile)
 463         self.etherlink.dump = Parent.etherdump
 464
 465     return self
 466
 467 def setMipsOptions(TestCPUClass):
 468         #CP0 Configuration
 469         TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
 470         TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
 471         TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
 472         TestCPUClass.CoreParams.CP0_PRId_Revision = 0
 473
 474         #CP0 Interrupt Control
 475         TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
 476         TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
 477
 478         # Config Register
 479         #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
 480         #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
 481         TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
 482         TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
 483         TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
 484         TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
 485         #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
 486
 487         #Config 1 Register
 488         TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
 489         TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
 490         # ***VERY IMPORTANT***
 491         # Remember to modify CP0_Config1 according to cache specs
 492         # Examine file ../common/Cache.py
 493         TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
 494         TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
 495         TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
 496         TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
 497         TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
 498         TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
 499         TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
 500         TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
 501         TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
 502         TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
 503         TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
 504         TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
 505         TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
 506
 507         #Config 2 Register
 508         TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
 509         TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
 510         TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
 511         TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
 512         TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
 513         TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
 514         TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
 515         TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
 516         TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
 517
 518
 519         #Config 3 Register
 520         TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
 521         TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
 522         TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
 523         TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
 524         TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
 525         TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
 526         TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
 527         TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
 528         TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
 529
 530         #SRS Ctl - HSS
 531         TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
 532
 533
 534         #TestCPUClass.CoreParams.tlb = TLB()
 535         #TestCPUClass.CoreParams.UnifiedTLB = 1