configs/common/FSConfig.py

   1 # Copyright (c) 2010-2012, 2015-2019 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
  14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  15 # All rights reserved.
  16 #
  17 # Redistribution and use in source and binary forms, with or without
  18 # modification, are permitted provided that the following conditions are
  19 # met: redistributions of source code must retain the above copyright
  20 # notice, this list of conditions and the following disclaimer;
  21 # redistributions in binary form must reproduce the above copyright
  22 # notice, this list of conditions and the following disclaimer in the
  23 # documentation and/or other materials provided with the distribution;
  24 # neither the name of the copyright holders nor the names of its
  25 # contributors may be used to endorse or promote products derived from
  26 # this software without specific prior written permission.
  27 #
  28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39 #
  40 # Authors: Kevin Lim
  41
  42 from __future__ import print_function
  43 from __future__ import absolute_import
  44
  45 import m5
  46 from m5.objects import *
  47 from m5.util import *
  48 from .Benchmarks import *
  49 from . import ObjectList
  50
  51 # Populate to reflect supported os types per target ISA
  52 os_types = { 'mips'  : [ 'linux' ],
  53              'sparc' : [ 'linux' ],
  54              'x86'   : [ 'linux' ],
  55              'arm'   : [ 'linux',
  56                          'android-gingerbread',
  57                          'android-ics',
  58                          'android-jellybean',
  59                          'android-kitkat',
  60                          'android-nougat', ],
  61            }
  62
  63 class CowIdeDisk(IdeDisk):
  64     image = CowDiskImage(child=RawDiskImage(read_only=True),
  65                          read_only=False)
  66
  67     def childImage(self, ci):
  68         self.image.child.image_file = ci
  69
  70 class MemBus(SystemXBar):
  71     badaddr_responder = BadAddr()
  72     default = Self.badaddr_responder.pio
  73
  74 def attach_9p(parent, bus):
  75     viopci = PciVirtIO()
  76     viopci.vio = VirtIO9PDiod()
  77     viodir = os.path.join(m5.options.outdir, '9p')
  78     viopci.vio.root = os.path.join(viodir, 'share')
  79     viopci.vio.socketPath = os.path.join(viodir, 'socket')
  80     if not os.path.exists(viopci.vio.root):
  81         os.makedirs(viopci.vio.root)
  82     if os.path.exists(viopci.vio.socketPath):
  83         os.remove(viopci.vio.socketPath)
  84     parent.viopci = viopci
  85     parent.attachPciDevice(viopci, bus)
  86
  87 def fillInCmdline(mdesc, template, **kwargs):
  88     kwargs.setdefault('rootdev', mdesc.rootdev())
  89     kwargs.setdefault('mem', mdesc.mem())
  90     kwargs.setdefault('script', mdesc.script())
  91     return template % kwargs
  92
  93 def makeCowDisks(disk_paths):
  94     disks = []
  95     for disk_path in disk_paths:
  96         disk = CowIdeDisk(driveID='master')
  97         disk.childImage(disk_path);
  98         disks.append(disk)
  99     return disks
 100
 101 def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
 102     # Constants from iob.cc and uart8250.cc
 103     iob_man_addr = 0x9800000000
 104     uart_pio_size = 8
 105
 106     class CowMmDisk(MmDisk):
 107         image = CowDiskImage(child=RawDiskImage(read_only=True),
 108                              read_only=False)
 109
 110         def childImage(self, ci):
 111             self.image.child.image_file = ci
 112
 113     self = SparcSystem()
 114     if not mdesc:
 115         # generic system
 116         mdesc = SysConfig()
 117     self.readfile = mdesc.script()
 118     self.iobus = IOXBar()
 119     self.membus = MemBus()
 120     self.bridge = Bridge(delay='50ns')
 121     self.t1000 = T1000()
 122     self.t1000.attachOnChipIO(self.membus)
 123     self.t1000.attachIO(self.iobus)
 124     self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
 125                        AddrRange(Addr('2GB'), size ='256MB')]
 126     self.bridge.master = self.iobus.slave
 127     self.bridge.slave = self.membus.master
 128     self.rom.port = self.membus.master
 129     self.nvram.port = self.membus.master
 130     self.hypervisor_desc.port = self.membus.master
 131     self.partition_desc.port = self.membus.master
 132     self.intrctrl = IntrControl()
 133     self.disk0 = CowMmDisk()
 134     self.disk0.childImage(mdesc.disks()[0])
 135     self.disk0.pio = self.iobus.master
 136
 137     # The puart0 and hvuart are placed on the IO bus, so create ranges
 138     # for them. The remaining IO range is rather fragmented, so poke
 139     # holes for the iob and partition descriptors etc.
 140     self.bridge.ranges = \
 141         [
 142         AddrRange(self.t1000.puart0.pio_addr,
 143                   self.t1000.puart0.pio_addr + uart_pio_size - 1),
 144         AddrRange(self.disk0.pio_addr,
 145                   self.t1000.fake_jbi.pio_addr +
 146                   self.t1000.fake_jbi.pio_size - 1),
 147         AddrRange(self.t1000.fake_clk.pio_addr,
 148                   iob_man_addr - 1),
 149         AddrRange(self.t1000.fake_l2_1.pio_addr,
 150                   self.t1000.fake_ssi.pio_addr +
 151                   self.t1000.fake_ssi.pio_size - 1),
 152         AddrRange(self.t1000.hvuart.pio_addr,
 153                   self.t1000.hvuart.pio_addr + uart_pio_size - 1)
 154         ]
 155     self.reset_bin = binary('reset_new.bin')
 156     self.hypervisor_bin = binary('q_new.bin')
 157     self.openboot_bin = binary('openboot_new.bin')
 158     self.nvram_bin = binary('nvram1')
 159     self.hypervisor_desc_bin = binary('1up-hv.bin')
 160     self.partition_desc_bin = binary('1up-md.bin')
 161
 162     self.system_port = self.membus.slave
 163
 164     return self
 165
 166 def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
 167                   dtb_filename=None, bare_metal=False, cmdline=None,
 168                   external_memory="", ruby=False, security=False,
 169                   vio_9p=None, bootloader=None):
 170     assert machine_type
 171
 172     pci_devices = []
 173
 174     if bare_metal:
 175         self = ArmSystem()
 176     else:
 177         self = LinuxArmSystem()
 178
 179     if not mdesc:
 180         # generic system
 181         mdesc = SysConfig()
 182
 183     self.readfile = mdesc.script()
 184     self.iobus = IOXBar()
 185     if not ruby:
 186         self.bridge = Bridge(delay='50ns')
 187         self.bridge.master = self.iobus.slave
 188         self.membus = MemBus()
 189         self.membus.badaddr_responder.warn_access = "warn"
 190         self.bridge.slave = self.membus.master
 191
 192     self.mem_mode = mem_mode
 193
 194     platform_class = ObjectList.platform_list.get(machine_type)
 195     # Resolve the real platform name, the original machine_type
 196     # variable might have been an alias.
 197     machine_type = platform_class.__name__
 198     self.realview = platform_class()
 199     self._bootmem = self.realview.bootmem
 200
 201     if isinstance(self.realview, VExpress_EMM64):
 202         if os.path.split(mdesc.disks()[0])[-1] == 'linux-aarch32-ael.img':
 203             print("Selected 64-bit ARM architecture, updating default "
 204                   "disk image...")
 205             mdesc.diskname = 'linaro-minimal-aarch64.img'
 206
 207
 208     # Attach any PCI devices this platform supports
 209     self.realview.attachPciDevices()
 210
 211     disks = makeCowDisks(mdesc.disks())
 212     # Old platforms have a built-in IDE or CF controller. Default to
 213     # the IDE controller if both exist. New platforms expect the
 214     # storage controller to be added from the config script.
 215     if hasattr(self.realview, "ide"):
 216         self.realview.ide.disks = disks
 217     elif hasattr(self.realview, "cf_ctrl"):
 218         self.realview.cf_ctrl.disks = disks
 219     else:
 220         self.pci_ide = IdeController(disks=disks)
 221         pci_devices.append(self.pci_ide)
 222
 223     self.mem_ranges = []
 224     size_remain = long(Addr(mdesc.mem()))
 225     for region in self.realview._mem_regions:
 226         if size_remain > long(region.size()):
 227             self.mem_ranges.append(region)
 228             size_remain = size_remain - long(region.size())
 229         else:
 230             self.mem_ranges.append(AddrRange(region.start, size=size_remain))
 231             size_remain = 0
 232             break
 233         warn("Memory size specified spans more than one region. Creating" \
 234              " another memory controller for that range.")
 235
 236     if size_remain > 0:
 237         fatal("The currently selected ARM platforms doesn't support" \
 238               " the amount of DRAM you've selected. Please try" \
 239               " another platform")
 240
 241     self.have_security = security
 242
 243     if bare_metal:
 244         # EOT character on UART will end the simulation
 245         self.realview.uart[0].end_on_eot = True
 246     else:
 247         if dtb_filename:
 248             self.dtb_filename = binary(dtb_filename)
 249
 250         self.machine_type = machine_type if machine_type in ArmMachineType.map \
 251                             else "DTOnly"
 252
 253         # Ensure that writes to the UART actually go out early in the boot
 254         if not cmdline:
 255             cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
 256                       'lpj=19988480 norandmaps rw loglevel=8 ' + \
 257                       'mem=%(mem)s root=%(rootdev)s'
 258
 259         self.realview.setupBootLoader(self, binary, bootloader)
 260
 261         if hasattr(self.realview.gic, 'cpu_addr'):
 262             self.gic_cpu_addr = self.realview.gic.cpu_addr
 263
 264         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 265
 266         # This check is for users who have previously put 'android' in
 267         # the disk image filename to tell the config scripts to
 268         # prepare the kernel with android-specific boot options. That
 269         # behavior has been replaced with a more explicit option per
 270         # the error message below. The disk can have any name now and
 271         # doesn't need to include 'android' substring.
 272         if (mdesc.disks() and
 273                 os.path.split(mdesc.disks()[0])[-1]).lower().count('android'):
 274             if 'android' not in mdesc.os_type():
 275                 fatal("It looks like you are trying to boot an Android " \
 276                       "platform.  To boot Android, you must specify " \
 277                       "--os-type with an appropriate Android release on " \
 278                       "the command line.")
 279
 280         # android-specific tweaks
 281         if 'android' in mdesc.os_type():
 282             # generic tweaks
 283             cmdline += " init=/init"
 284
 285             # release-specific tweaks
 286             if 'kitkat' in mdesc.os_type():
 287                 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
 288                            "android.bootanim=0 "
 289             elif 'nougat' in mdesc.os_type():
 290                 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
 291                            "android.bootanim=0 " + \
 292                            "vmalloc=640MB " + \
 293                            "android.early.fstab=/fstab.gem5 " + \
 294                            "androidboot.selinux=permissive " + \
 295                            "video=Virtual-1:1920x1080-16"
 296
 297         self.boot_osflags = fillInCmdline(mdesc, cmdline)
 298
 299     if external_memory:
 300         # I/O traffic enters iobus
 301         self.external_io = ExternalMaster(port_data="external_io",
 302                                           port_type=external_memory)
 303         self.external_io.port = self.iobus.slave
 304
 305         # Ensure iocache only receives traffic destined for (actual) memory.
 306         self.iocache = ExternalSlave(port_data="iocache",
 307                                      port_type=external_memory,
 308                                      addr_ranges=self.mem_ranges)
 309         self.iocache.port = self.iobus.master
 310
 311         # Let system_port get to nvmem and nothing else.
 312         self.bridge.ranges = [self.realview.nvmem.range]
 313
 314         self.realview.attachOnChipIO(self.iobus)
 315         # Attach off-chip devices
 316         self.realview.attachIO(self.iobus)
 317     elif ruby:
 318         self._dma_ports = [ ]
 319         self._mem_ports = [ ]
 320         self.realview.attachOnChipIO(self.iobus,
 321             dma_ports=self._dma_ports, mem_ports=self._mem_ports)
 322         self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
 323     else:
 324         self.realview.attachOnChipIO(self.membus, self.bridge)
 325         # Attach off-chip devices
 326         self.realview.attachIO(self.iobus)
 327
 328     for dev in pci_devices:
 329         self.realview.attachPciDevice(
 330             dev, self.iobus,
 331             dma_ports=self._dma_ports if ruby else None)
 332
 333     self.intrctrl = IntrControl()
 334     self.terminal = Terminal()
 335     self.vncserver = VncServer()
 336
 337     if vio_9p:
 338         attach_9p(self.realview, self.iobus)
 339
 340     if not ruby:
 341         self.system_port = self.membus.slave
 342
 343     if ruby:
 344         if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
 345             fatal("The MI_example protocol cannot implement Load/Store "
 346                   "Exclusive operations. Multicore ARM systems configured "
 347                   "with the MI_example protocol will not work properly.")
 348         warn("You are trying to use Ruby on ARM, which is not working "
 349              "properly yet.")
 350
 351     return self
 352
 353
 354 def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
 355     class BaseMalta(Malta):
 356         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 357         ide = IdeController(disks=Parent.disks,
 358                             pci_func=0, pci_dev=0, pci_bus=0)
 359
 360     self = LinuxMipsSystem()
 361     if not mdesc:
 362         # generic system
 363         mdesc = SysConfig()
 364     self.readfile = mdesc.script()
 365     self.iobus = IOXBar()
 366     self.membus = MemBus()
 367     self.bridge = Bridge(delay='50ns')
 368     self.mem_ranges = [AddrRange('1GB')]
 369     self.bridge.master = self.iobus.slave
 370     self.bridge.slave = self.membus.master
 371     self.disks = makeCowDisks(mdesc.disks())
 372     self.malta = BaseMalta()
 373     self.malta.attachIO(self.iobus)
 374     self.malta.ide.pio = self.iobus.master
 375     self.malta.ide.dma = self.iobus.slave
 376     self.malta.ethernet.pio = self.iobus.master
 377     self.malta.ethernet.dma = self.iobus.slave
 378     self.simple_disk = SimpleDisk(disk=RawDiskImage(
 379         image_file = mdesc.disks()[0], read_only = True))
 380     self.intrctrl = IntrControl()
 381     self.mem_mode = mem_mode
 382     self.terminal = Terminal()
 383     self.console = binary('mips/console')
 384     if not cmdline:
 385         cmdline = 'root=/dev/hda1 console=ttyS0'
 386     self.boot_osflags = fillInCmdline(mdesc, cmdline)
 387
 388     self.system_port = self.membus.slave
 389
 390     return self
 391
 392 def x86IOAddress(port):
 393     IO_address_space_base = 0x8000000000000000
 394     return IO_address_space_base + port
 395
 396 def connectX86ClassicSystem(x86_sys, numCPUs):
 397     # Constants similar to x86_traits.hh
 398     IO_address_space_base = 0x8000000000000000
 399     pci_config_address_space_base = 0xc000000000000000
 400     interrupts_address_space_base = 0xa000000000000000
 401     APIC_range_size = 1 << 12;
 402
 403     x86_sys.membus = MemBus()
 404
 405     # North Bridge
 406     x86_sys.iobus = IOXBar()
 407     x86_sys.bridge = Bridge(delay='50ns')
 408     x86_sys.bridge.master = x86_sys.iobus.slave
 409     x86_sys.bridge.slave = x86_sys.membus.master
 410     # Allow the bridge to pass through:
 411     #  1) kernel configured PCI device memory map address: address range
 412     #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
 413     #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
 414     #  3) everything in the IO address range up to the local APIC, and
 415     #  4) then the entire PCI address space and beyond.
 416     x86_sys.bridge.ranges = \
 417         [
 418         AddrRange(0xC0000000, 0xFFFF0000),
 419         AddrRange(IO_address_space_base,
 420                   interrupts_address_space_base - 1),
 421         AddrRange(pci_config_address_space_base,
 422                   Addr.max)
 423         ]
 424
 425     # Create a bridge from the IO bus to the memory bus to allow access to
 426     # the local APIC (two pages)
 427     x86_sys.apicbridge = Bridge(delay='50ns')
 428     x86_sys.apicbridge.slave = x86_sys.iobus.master
 429     x86_sys.apicbridge.master = x86_sys.membus.slave
 430     x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
 431                                            interrupts_address_space_base +
 432                                            numCPUs * APIC_range_size
 433                                            - 1)]
 434
 435     # connect the io bus
 436     x86_sys.pc.attachIO(x86_sys.iobus)
 437
 438     x86_sys.system_port = x86_sys.membus.slave
 439
 440 def connectX86RubySystem(x86_sys):
 441     # North Bridge
 442     x86_sys.iobus = IOXBar()
 443
 444     # add the ide to the list of dma devices that later need to attach to
 445     # dma controllers
 446     x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
 447     x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
 448
 449
 450 def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
 451     if self == None:
 452         self = X86System()
 453
 454     if not mdesc:
 455         # generic system
 456         mdesc = SysConfig()
 457     self.readfile = mdesc.script()
 458
 459     self.mem_mode = mem_mode
 460
 461     # Physical memory
 462     # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
 463     # for various devices.  Hence, if the physical memory size is greater than
 464     # 3GB, we need to split it into two parts.
 465     excess_mem_size = \
 466         convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
 467     if excess_mem_size <= 0:
 468         self.mem_ranges = [AddrRange(mdesc.mem())]
 469     else:
 470         warn("Physical memory size specified is %s which is greater than " \
 471              "3GB.  Twice the number of memory controllers would be " \
 472              "created."  % (mdesc.mem()))
 473
 474         self.mem_ranges = [AddrRange('3GB'),
 475             AddrRange(Addr('4GB'), size = excess_mem_size)]
 476
 477     # Platform
 478     self.pc = Pc()
 479
 480     # Create and connect the busses required by each memory system
 481     if Ruby:
 482         connectX86RubySystem(self)
 483     else:
 484         connectX86ClassicSystem(self, numCPUs)
 485
 486     self.intrctrl = IntrControl()
 487
 488     # Disks
 489     disks = makeCowDisks(mdesc.disks())
 490     self.pc.south_bridge.ide.disks = disks
 491
 492     # Add in a Bios information structure.
 493     structures = [X86SMBiosBiosInformation()]
 494     self.smbios_table.structures = structures
 495
 496     # Set up the Intel MP table
 497     base_entries = []
 498     ext_entries = []
 499     for i in range(numCPUs):
 500         bp = X86IntelMPProcessor(
 501                 local_apic_id = i,
 502                 local_apic_version = 0x14,
 503                 enable = True,
 504                 bootstrap = (i == 0))
 505         base_entries.append(bp)
 506     io_apic = X86IntelMPIOAPIC(
 507             id = numCPUs,
 508             version = 0x11,
 509             enable = True,
 510             address = 0xfec00000)
 511     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 512     base_entries.append(io_apic)
 513     # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
 514     # but linux kernel cannot config PCI device if it was not connected to PCI bus,
 515     # so we fix PCI bus id to 0, and ISA bus id to 1.
 516     pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI   ')
 517     base_entries.append(pci_bus)
 518     isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA   ')
 519     base_entries.append(isa_bus)
 520     connect_busses = X86IntelMPBusHierarchy(bus_id=1,
 521             subtractive_decode=True, parent_bus=0)
 522     ext_entries.append(connect_busses)
 523     pci_dev4_inta = X86IntelMPIOIntAssignment(
 524             interrupt_type = 'INT',
 525             polarity = 'ConformPolarity',
 526             trigger = 'ConformTrigger',
 527             source_bus_id = 0,
 528             source_bus_irq = 0 + (4 << 2),
 529             dest_io_apic_id = io_apic.id,
 530             dest_io_apic_intin = 16)
 531     base_entries.append(pci_dev4_inta)
 532     def assignISAInt(irq, apicPin):
 533         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 534                 interrupt_type = 'ExtInt',
 535                 polarity = 'ConformPolarity',
 536                 trigger = 'ConformTrigger',
 537                 source_bus_id = 1,
 538                 source_bus_irq = irq,
 539                 dest_io_apic_id = io_apic.id,
 540                 dest_io_apic_intin = 0)
 541         base_entries.append(assign_8259_to_apic)
 542         assign_to_apic = X86IntelMPIOIntAssignment(
 543                 interrupt_type = 'INT',
 544                 polarity = 'ConformPolarity',
 545                 trigger = 'ConformTrigger',
 546                 source_bus_id = 1,
 547                 source_bus_irq = irq,
 548                 dest_io_apic_id = io_apic.id,
 549                 dest_io_apic_intin = apicPin)
 550         base_entries.append(assign_to_apic)
 551     assignISAInt(0, 2)
 552     assignISAInt(1, 1)
 553     for i in range(3, 15):
 554         assignISAInt(i, i)
 555     self.intel_mp_table.base_entries = base_entries
 556     self.intel_mp_table.ext_entries = ext_entries
 557
 558 def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
 559                        cmdline=None):
 560     self = LinuxX86System()
 561
 562     # Build up the x86 system and then specialize it for Linux
 563     makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
 564
 565     # We assume below that there's at least 1MB of memory. We'll require 2
 566     # just to avoid corner cases.
 567     phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
 568     assert(phys_mem_size >= 0x200000)
 569     assert(len(self.mem_ranges) <= 2)
 570
 571     entries = \
 572        [
 573         # Mark the first megabyte of memory as reserved
 574         X86E820Entry(addr = 0, size = '639kB', range_type = 1),
 575         X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
 576         # Mark the rest of physical memory as available
 577         X86E820Entry(addr = 0x100000,
 578                 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
 579                 range_type = 1),
 580         ]
 581
 582     # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
 583     # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
 584     # specific range can pass though bridge to iobus.
 585     if len(self.mem_ranges) == 1:
 586         entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
 587             size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
 588             range_type=2))
 589
 590     # Reserve the last 16kB of the 32-bit address space for the m5op interface
 591     entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
 592
 593     # In case the physical memory is greater than 3GB, we split it into two
 594     # parts and add a separate e820 entry for the second part.  This entry
 595     # starts at 0x100000000,  which is the first address after the space
 596     # reserved for devices.
 597     if len(self.mem_ranges) == 2:
 598         entries.append(X86E820Entry(addr = 0x100000000,
 599             size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
 600
 601     self.e820_table.entries = entries
 602
 603     # Command line
 604     if not cmdline:
 605         cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
 606     self.boot_osflags = fillInCmdline(mdesc, cmdline)
 607     return self
 608
 609
 610 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 611     self = Root(full_system = full_system)
 612     self.testsys = testSystem
 613     self.drivesys = driveSystem
 614     self.etherlink = EtherLink()
 615
 616     if hasattr(testSystem, 'realview'):
 617         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 618         self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
 619     elif hasattr(testSystem, 'tsunami'):
 620         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 621         self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 622     else:
 623         fatal("Don't know how to connect these system together")
 624
 625     if dumpfile:
 626         self.etherdump = EtherDump(file=dumpfile)
 627         self.etherlink.dump = Parent.etherdump
 628
 629     return self
 630
 631
 632 def makeDistRoot(testSystem,
 633                  rank,
 634                  size,
 635                  server_name,
 636                  server_port,
 637                  sync_repeat,
 638                  sync_start,
 639                  linkspeed,
 640                  linkdelay,
 641                  dumpfile):
 642     self = Root(full_system = True)
 643     self.testsys = testSystem
 644
 645     self.etherlink = DistEtherLink(speed = linkspeed,
 646                                    delay = linkdelay,
 647                                    dist_rank = rank,
 648                                    dist_size = size,
 649                                    server_name = server_name,
 650                                    server_port = server_port,
 651                                    sync_start = sync_start,
 652                                    sync_repeat = sync_repeat)
 653
 654     if hasattr(testSystem, 'realview'):
 655         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 656     elif hasattr(testSystem, 'tsunami'):
 657         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 658     else:
 659         fatal("Don't know how to connect DistEtherLink to this system")
 660
 661     if dumpfile:
 662         self.etherdump = EtherDump(file=dumpfile)
 663         self.etherlink.dump = Parent.etherdump
 664
 665     return self