1 # Copyright (c) 2010-2012, 2015-2018 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
15 # All rights reserved.
17 # Redistribution and use in source and binary forms, with or without
18 # modification, are permitted provided that the following conditions are
19 # met: redistributions of source code must retain the above copyright
20 # notice, this list of conditions and the following disclaimer;
21 # redistributions in binary form must reproduce the above copyright
22 # notice, this list of conditions and the following disclaimer in the
23 # documentation and/or other materials provided with the distribution;
24 # neither the name of the copyright holders nor the names of its
25 # contributors may be used to endorse or promote products derived from
26 # this software without specific prior written permission.
28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 from __future__
import print_function
44 from m5
.objects
import *
45 from Benchmarks
import *
47 from common
import PlatformConfig
49 # Populate to reflect supported os types per target ISA
50 os_types
= { 'alpha' : [ 'linux' ],
52 'sparc' : [ 'linux' ],
55 'android-gingerbread',
62 class CowIdeDisk(IdeDisk
):
63 image
= CowDiskImage(child
=RawDiskImage(read_only
=True),
66 def childImage(self
, ci
):
67 self
.image
.child
.image_file
= ci
69 class MemBus(SystemXBar
):
70 badaddr_responder
= BadAddr()
71 default
= Self
.badaddr_responder
.pio
73 def fillInCmdline(mdesc
, template
, **kwargs
):
74 kwargs
.setdefault('disk', mdesc
.disk())
75 kwargs
.setdefault('rootdev', mdesc
.rootdev())
76 kwargs
.setdefault('mem', mdesc
.mem())
77 kwargs
.setdefault('script', mdesc
.script())
78 return template
% kwargs
80 def makeLinuxAlphaSystem(mem_mode
, mdesc
=None, ruby
=False, cmdline
=None):
82 class BaseTsunami(Tsunami
):
83 ethernet
= NSGigE(pci_bus
=0, pci_dev
=1, pci_func
=0)
84 ide
= IdeController(disks
=[Parent
.disk0
, Parent
.disk2
],
85 pci_func
=0, pci_dev
=0, pci_bus
=0)
87 self
= LinuxAlphaSystem()
91 self
.readfile
= mdesc
.script()
93 self
.tsunami
= BaseTsunami()
95 # Create the io bus to connect all device ports
97 self
.tsunami
.attachIO(self
.iobus
)
99 self
.tsunami
.ide
.pio
= self
.iobus
.master
101 self
.tsunami
.ethernet
.pio
= self
.iobus
.master
104 # Store the dma devices for later connection to dma ruby ports.
105 # Append an underscore to dma_ports to avoid the SimObjectVector check.
106 self
._dma
_ports
= [self
.tsunami
.ide
.dma
, self
.tsunami
.ethernet
.dma
]
108 self
.membus
= MemBus()
110 # By default the bridge responds to all addresses above the I/O
111 # base address (including the PCI config space)
112 IO_address_space_base
= 0x80000000000
113 self
.bridge
= Bridge(delay
='50ns',
114 ranges
= [AddrRange(IO_address_space_base
, Addr
.max)])
115 self
.bridge
.master
= self
.iobus
.slave
116 self
.bridge
.slave
= self
.membus
.master
118 self
.tsunami
.ide
.dma
= self
.iobus
.slave
119 self
.tsunami
.ethernet
.dma
= self
.iobus
.slave
121 self
.system_port
= self
.membus
.slave
123 self
.mem_ranges
= [AddrRange(mdesc
.mem())]
124 self
.disk0
= CowIdeDisk(driveID
='master')
125 self
.disk2
= CowIdeDisk(driveID
='master')
126 self
.disk0
.childImage(mdesc
.disk())
127 self
.disk2
.childImage(disk('linux-bigswap2.img'))
128 self
.simple_disk
= SimpleDisk(disk
=RawDiskImage(image_file
= mdesc
.disk(),
130 self
.intrctrl
= IntrControl()
131 self
.mem_mode
= mem_mode
132 self
.terminal
= Terminal()
133 self
.kernel
= binary('vmlinux')
134 self
.pal
= binary('ts_osfpal')
135 self
.console
= binary('console')
137 cmdline
= 'root=/dev/hda1 console=ttyS0'
138 self
.boot_osflags
= fillInCmdline(mdesc
, cmdline
)
142 def makeSparcSystem(mem_mode
, mdesc
=None, cmdline
=None):
143 # Constants from iob.cc and uart8250.cc
144 iob_man_addr
= 0x9800000000
147 class CowMmDisk(MmDisk
):
148 image
= CowDiskImage(child
=RawDiskImage(read_only
=True),
151 def childImage(self
, ci
):
152 self
.image
.child
.image_file
= ci
158 self
.readfile
= mdesc
.script()
159 self
.iobus
= IOXBar()
160 self
.membus
= MemBus()
161 self
.bridge
= Bridge(delay
='50ns')
163 self
.t1000
.attachOnChipIO(self
.membus
)
164 self
.t1000
.attachIO(self
.iobus
)
165 self
.mem_ranges
= [AddrRange(Addr('1MB'), size
= '64MB'),
166 AddrRange(Addr('2GB'), size
='256MB')]
167 self
.bridge
.master
= self
.iobus
.slave
168 self
.bridge
.slave
= self
.membus
.master
169 self
.rom
.port
= self
.membus
.master
170 self
.nvram
.port
= self
.membus
.master
171 self
.hypervisor_desc
.port
= self
.membus
.master
172 self
.partition_desc
.port
= self
.membus
.master
173 self
.intrctrl
= IntrControl()
174 self
.disk0
= CowMmDisk()
175 self
.disk0
.childImage(mdesc
.disk())
176 self
.disk0
.pio
= self
.iobus
.master
178 # The puart0 and hvuart are placed on the IO bus, so create ranges
179 # for them. The remaining IO range is rather fragmented, so poke
180 # holes for the iob and partition descriptors etc.
181 self
.bridge
.ranges
= \
183 AddrRange(self
.t1000
.puart0
.pio_addr
,
184 self
.t1000
.puart0
.pio_addr
+ uart_pio_size
- 1),
185 AddrRange(self
.disk0
.pio_addr
,
186 self
.t1000
.fake_jbi
.pio_addr
+
187 self
.t1000
.fake_jbi
.pio_size
- 1),
188 AddrRange(self
.t1000
.fake_clk
.pio_addr
,
190 AddrRange(self
.t1000
.fake_l2_1
.pio_addr
,
191 self
.t1000
.fake_ssi
.pio_addr
+
192 self
.t1000
.fake_ssi
.pio_size
- 1),
193 AddrRange(self
.t1000
.hvuart
.pio_addr
,
194 self
.t1000
.hvuart
.pio_addr
+ uart_pio_size
- 1)
196 self
.reset_bin
= binary('reset_new.bin')
197 self
.hypervisor_bin
= binary('q_new.bin')
198 self
.openboot_bin
= binary('openboot_new.bin')
199 self
.nvram_bin
= binary('nvram1')
200 self
.hypervisor_desc_bin
= binary('1up-hv.bin')
201 self
.partition_desc_bin
= binary('1up-md.bin')
203 self
.system_port
= self
.membus
.slave
207 def makeArmSystem(mem_mode
, machine_type
, num_cpus
=1, mdesc
=None,
208 dtb_filename
=None, bare_metal
=False, cmdline
=None,
209 external_memory
="", ruby
=False, security
=False,
215 "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus
,
216 "VExpress_EMM64": "vexpress.aarch64.20140821.dtb",
220 "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8",
221 "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5",
222 "VExpress_EMM64": "vmlinux.aarch64.20140821",
230 self
= LinuxArmSystem()
236 self
.readfile
= mdesc
.script()
237 self
.iobus
= IOXBar()
239 self
.bridge
= Bridge(delay
='50ns')
240 self
.bridge
.master
= self
.iobus
.slave
241 self
.membus
= MemBus()
242 self
.membus
.badaddr_responder
.warn_access
= "warn"
243 self
.bridge
.slave
= self
.membus
.master
245 self
.mem_mode
= mem_mode
247 platform_class
= PlatformConfig
.get(machine_type
)
248 # Resolve the real platform name, the original machine_type
249 # variable might have been an alias.
250 machine_type
= platform_class
.__name
__
251 self
.realview
= platform_class()
253 if not dtb_filename
and not (bare_metal
or ignore_dtb
):
255 dtb_filename
= default_dtbs
[machine_type
]
257 fatal("No DTB specified and no default DTB known for '%s'" % \
260 if isinstance(self
.realview
, VExpress_EMM64
):
261 if os
.path
.split(mdesc
.disk())[-1] == 'linux-aarch32-ael.img':
262 print("Selected 64-bit ARM architecture, updating default "
264 mdesc
.diskname
= 'linaro-minimal-aarch64.img'
267 # Attach any PCI devices this platform supports
268 self
.realview
.attachPciDevices()
270 self
.cf0
= CowIdeDisk(driveID
='master')
271 self
.cf0
.childImage(mdesc
.disk())
272 # Old platforms have a built-in IDE or CF controller. Default to
273 # the IDE controller if both exist. New platforms expect the
274 # storage controller to be added from the config script.
275 if hasattr(self
.realview
, "ide"):
276 self
.realview
.ide
.disks
= [self
.cf0
]
277 elif hasattr(self
.realview
, "cf_ctrl"):
278 self
.realview
.cf_ctrl
.disks
= [self
.cf0
]
280 self
.pci_ide
= IdeController(disks
=[self
.cf0
])
281 pci_devices
.append(self
.pci_ide
)
284 size_remain
= long(Addr(mdesc
.mem()))
285 for region
in self
.realview
._mem
_regions
:
286 if size_remain
> long(region
[1]):
287 self
.mem_ranges
.append(AddrRange(region
[0], size
=region
[1]))
288 size_remain
= size_remain
- long(region
[1])
290 self
.mem_ranges
.append(AddrRange(region
[0], size
=size_remain
))
293 warn("Memory size specified spans more than one region. Creating" \
294 " another memory controller for that range.")
297 fatal("The currently selected ARM platforms doesn't support" \
298 " the amount of DRAM you've selected. Please try" \
301 self
.have_security
= security
304 # EOT character on UART will end the simulation
305 self
.realview
.uart
[0].end_on_eot
= True
307 if machine_type
in default_kernels
:
308 self
.kernel
= binary(default_kernels
[machine_type
])
310 if dtb_filename
and not ignore_dtb
:
311 self
.dtb_filename
= binary(dtb_filename
)
313 self
.machine_type
= machine_type
if machine_type
in ArmMachineType
.map \
316 # Ensure that writes to the UART actually go out early in the boot
318 cmdline
= 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
319 'lpj=19988480 norandmaps rw loglevel=8 ' + \
320 'mem=%(mem)s root=%(rootdev)s'
322 # When using external memory, gem5 writes the boot loader to nvmem
323 # and then SST will read from it, but SST can only get to nvmem from
324 # iobus, as gem5's membus is only used for initialization and
325 # SST doesn't use it. Attaching nvmem to iobus solves this issue.
326 # During initialization, system_port -> membus -> iobus -> nvmem.
328 self
.realview
.setupBootLoader(self
.iobus
, self
, binary
)
330 self
.realview
.setupBootLoader(None, self
, binary
)
332 self
.realview
.setupBootLoader(self
.membus
, self
, binary
)
333 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
334 self
.flags_addr
= self
.realview
.realview_io
.pio_addr
+ 0x30
336 # This check is for users who have previously put 'android' in
337 # the disk image filename to tell the config scripts to
338 # prepare the kernel with android-specific boot options. That
339 # behavior has been replaced with a more explicit option per
340 # the error message below. The disk can have any name now and
341 # doesn't need to include 'android' substring.
342 if (os
.path
.split(mdesc
.disk())[-1]).lower().count('android'):
343 if 'android' not in mdesc
.os_type():
344 fatal("It looks like you are trying to boot an Android " \
345 "platform. To boot Android, you must specify " \
346 "--os-type with an appropriate Android release on " \
349 # android-specific tweaks
350 if 'android' in mdesc
.os_type():
352 cmdline
+= " init=/init"
354 # release-specific tweaks
355 if 'kitkat' in mdesc
.os_type():
356 cmdline
+= " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
357 "android.bootanim=0 "
358 elif 'nougat' in mdesc
.os_type():
359 cmdline
+= " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
360 "android.bootanim=0 " + \
362 "android.early.fstab=/fstab.gem5 " + \
363 "androidboot.selinux=permissive " + \
364 "video=Virtual-1:1920x1080-16"
366 self
.boot_osflags
= fillInCmdline(mdesc
, cmdline
)
369 # I/O traffic enters iobus
370 self
.external_io
= ExternalMaster(port_data
="external_io",
371 port_type
=external_memory
)
372 self
.external_io
.port
= self
.iobus
.slave
374 # Ensure iocache only receives traffic destined for (actual) memory.
375 self
.iocache
= ExternalSlave(port_data
="iocache",
376 port_type
=external_memory
,
377 addr_ranges
=self
.mem_ranges
)
378 self
.iocache
.port
= self
.iobus
.master
380 # Let system_port get to nvmem and nothing else.
381 self
.bridge
.ranges
= [self
.realview
.nvmem
.range]
383 self
.realview
.attachOnChipIO(self
.iobus
)
384 # Attach off-chip devices
385 self
.realview
.attachIO(self
.iobus
)
387 self
._dma
_ports
= [ ]
388 self
.realview
.attachOnChipIO(self
.iobus
, dma_ports
=self
._dma
_ports
)
389 self
.realview
.attachIO(self
.iobus
, dma_ports
=self
._dma
_ports
)
391 self
.realview
.attachOnChipIO(self
.membus
, self
.bridge
)
392 # Attach off-chip devices
393 self
.realview
.attachIO(self
.iobus
)
395 for dev_id
, dev
in enumerate(pci_devices
):
396 dev
.pci_bus
, dev
.pci_dev
, dev
.pci_func
= (0, dev_id
+ 1, 0)
397 self
.realview
.attachPciDevice(
399 dma_ports
=self
._dma
_ports
if ruby
else None)
401 self
.intrctrl
= IntrControl()
402 self
.terminal
= Terminal()
403 self
.vncserver
= VncServer()
406 self
.system_port
= self
.membus
.slave
409 if buildEnv
['PROTOCOL'] == 'MI_example' and num_cpus
> 1:
410 fatal("The MI_example protocol cannot implement Load/Store "
411 "Exclusive operations. Multicore ARM systems configured "
412 "with the MI_example protocol will not work properly.")
413 warn("You are trying to use Ruby on ARM, which is not working "
419 def makeLinuxMipsSystem(mem_mode
, mdesc
=None, cmdline
=None):
420 class BaseMalta(Malta
):
421 ethernet
= NSGigE(pci_bus
=0, pci_dev
=1, pci_func
=0)
422 ide
= IdeController(disks
=[Parent
.disk0
, Parent
.disk2
],
423 pci_func
=0, pci_dev
=0, pci_bus
=0)
425 self
= LinuxMipsSystem()
429 self
.readfile
= mdesc
.script()
430 self
.iobus
= IOXBar()
431 self
.membus
= MemBus()
432 self
.bridge
= Bridge(delay
='50ns')
433 self
.mem_ranges
= [AddrRange('1GB')]
434 self
.bridge
.master
= self
.iobus
.slave
435 self
.bridge
.slave
= self
.membus
.master
436 self
.disk0
= CowIdeDisk(driveID
='master')
437 self
.disk2
= CowIdeDisk(driveID
='master')
438 self
.disk0
.childImage(mdesc
.disk())
439 self
.disk2
.childImage(disk('linux-bigswap2.img'))
440 self
.malta
= BaseMalta()
441 self
.malta
.attachIO(self
.iobus
)
442 self
.malta
.ide
.pio
= self
.iobus
.master
443 self
.malta
.ide
.dma
= self
.iobus
.slave
444 self
.malta
.ethernet
.pio
= self
.iobus
.master
445 self
.malta
.ethernet
.dma
= self
.iobus
.slave
446 self
.simple_disk
= SimpleDisk(disk
=RawDiskImage(image_file
= mdesc
.disk(),
448 self
.intrctrl
= IntrControl()
449 self
.mem_mode
= mem_mode
450 self
.terminal
= Terminal()
451 self
.kernel
= binary('mips/vmlinux')
452 self
.console
= binary('mips/console')
454 cmdline
= 'root=/dev/hda1 console=ttyS0'
455 self
.boot_osflags
= fillInCmdline(mdesc
, cmdline
)
457 self
.system_port
= self
.membus
.slave
461 def x86IOAddress(port
):
462 IO_address_space_base
= 0x8000000000000000
463 return IO_address_space_base
+ port
465 def connectX86ClassicSystem(x86_sys
, numCPUs
):
466 # Constants similar to x86_traits.hh
467 IO_address_space_base
= 0x8000000000000000
468 pci_config_address_space_base
= 0xc000000000000000
469 interrupts_address_space_base
= 0xa000000000000000
470 APIC_range_size
= 1 << 12;
472 x86_sys
.membus
= MemBus()
475 x86_sys
.iobus
= IOXBar()
476 x86_sys
.bridge
= Bridge(delay
='50ns')
477 x86_sys
.bridge
.master
= x86_sys
.iobus
.slave
478 x86_sys
.bridge
.slave
= x86_sys
.membus
.master
479 # Allow the bridge to pass through:
480 # 1) kernel configured PCI device memory map address: address range
481 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
482 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
483 # 3) everything in the IO address range up to the local APIC, and
484 # 4) then the entire PCI address space and beyond.
485 x86_sys
.bridge
.ranges
= \
487 AddrRange(0xC0000000, 0xFFFF0000),
488 AddrRange(IO_address_space_base
,
489 interrupts_address_space_base
- 1),
490 AddrRange(pci_config_address_space_base
,
494 # Create a bridge from the IO bus to the memory bus to allow access to
495 # the local APIC (two pages)
496 x86_sys
.apicbridge
= Bridge(delay
='50ns')
497 x86_sys
.apicbridge
.slave
= x86_sys
.iobus
.master
498 x86_sys
.apicbridge
.master
= x86_sys
.membus
.slave
499 x86_sys
.apicbridge
.ranges
= [AddrRange(interrupts_address_space_base
,
500 interrupts_address_space_base
+
501 numCPUs
* APIC_range_size
505 x86_sys
.pc
.attachIO(x86_sys
.iobus
)
507 x86_sys
.system_port
= x86_sys
.membus
.slave
509 def connectX86RubySystem(x86_sys
):
511 x86_sys
.iobus
= IOXBar()
513 # add the ide to the list of dma devices that later need to attach to
515 x86_sys
._dma
_ports
= [x86_sys
.pc
.south_bridge
.ide
.dma
]
516 x86_sys
.pc
.attachIO(x86_sys
.iobus
, x86_sys
._dma
_ports
)
519 def makeX86System(mem_mode
, numCPUs
=1, mdesc
=None, self
=None, Ruby
=False):
526 self
.readfile
= mdesc
.script()
528 self
.mem_mode
= mem_mode
531 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
532 # for various devices. Hence, if the physical memory size is greater than
533 # 3GB, we need to split it into two parts.
535 convert
.toMemorySize(mdesc
.mem()) - convert
.toMemorySize('3GB')
536 if excess_mem_size
<= 0:
537 self
.mem_ranges
= [AddrRange(mdesc
.mem())]
539 warn("Physical memory size specified is %s which is greater than " \
540 "3GB. Twice the number of memory controllers would be " \
541 "created." % (mdesc
.mem()))
543 self
.mem_ranges
= [AddrRange('3GB'),
544 AddrRange(Addr('4GB'), size
= excess_mem_size
)]
549 # Create and connect the busses required by each memory system
551 connectX86RubySystem(self
)
553 connectX86ClassicSystem(self
, numCPUs
)
555 self
.intrctrl
= IntrControl()
558 disk0
= CowIdeDisk(driveID
='master')
559 disk2
= CowIdeDisk(driveID
='master')
560 disk0
.childImage(mdesc
.disk())
561 disk2
.childImage(disk('linux-bigswap2.img'))
562 self
.pc
.south_bridge
.ide
.disks
= [disk0
, disk2
]
564 # Add in a Bios information structure.
565 structures
= [X86SMBiosBiosInformation()]
566 self
.smbios_table
.structures
= structures
568 # Set up the Intel MP table
571 for i
in xrange(numCPUs
):
572 bp
= X86IntelMPProcessor(
574 local_apic_version
= 0x14,
576 bootstrap
= (i
== 0))
577 base_entries
.append(bp
)
578 io_apic
= X86IntelMPIOAPIC(
582 address
= 0xfec00000)
583 self
.pc
.south_bridge
.io_apic
.apic_id
= io_apic
.id
584 base_entries
.append(io_apic
)
585 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
586 # but linux kernel cannot config PCI device if it was not connected to PCI bus,
587 # so we fix PCI bus id to 0, and ISA bus id to 1.
588 pci_bus
= X86IntelMPBus(bus_id
= 0, bus_type
='PCI ')
589 base_entries
.append(pci_bus
)
590 isa_bus
= X86IntelMPBus(bus_id
= 1, bus_type
='ISA ')
591 base_entries
.append(isa_bus
)
592 connect_busses
= X86IntelMPBusHierarchy(bus_id
=1,
593 subtractive_decode
=True, parent_bus
=0)
594 ext_entries
.append(connect_busses
)
595 pci_dev4_inta
= X86IntelMPIOIntAssignment(
596 interrupt_type
= 'INT',
597 polarity
= 'ConformPolarity',
598 trigger
= 'ConformTrigger',
600 source_bus_irq
= 0 + (4 << 2),
601 dest_io_apic_id
= io_apic
.id,
602 dest_io_apic_intin
= 16)
603 base_entries
.append(pci_dev4_inta
)
604 def assignISAInt(irq
, apicPin
):
605 assign_8259_to_apic
= X86IntelMPIOIntAssignment(
606 interrupt_type
= 'ExtInt',
607 polarity
= 'ConformPolarity',
608 trigger
= 'ConformTrigger',
610 source_bus_irq
= irq
,
611 dest_io_apic_id
= io_apic
.id,
612 dest_io_apic_intin
= 0)
613 base_entries
.append(assign_8259_to_apic
)
614 assign_to_apic
= X86IntelMPIOIntAssignment(
615 interrupt_type
= 'INT',
616 polarity
= 'ConformPolarity',
617 trigger
= 'ConformTrigger',
619 source_bus_irq
= irq
,
620 dest_io_apic_id
= io_apic
.id,
621 dest_io_apic_intin
= apicPin
)
622 base_entries
.append(assign_to_apic
)
625 for i
in range(3, 15):
627 self
.intel_mp_table
.base_entries
= base_entries
628 self
.intel_mp_table
.ext_entries
= ext_entries
630 def makeLinuxX86System(mem_mode
, numCPUs
=1, mdesc
=None, Ruby
=False,
632 self
= LinuxX86System()
634 # Build up the x86 system and then specialize it for Linux
635 makeX86System(mem_mode
, numCPUs
, mdesc
, self
, Ruby
)
637 # We assume below that there's at least 1MB of memory. We'll require 2
638 # just to avoid corner cases.
639 phys_mem_size
= sum(map(lambda r
: r
.size(), self
.mem_ranges
))
640 assert(phys_mem_size
>= 0x200000)
641 assert(len(self
.mem_ranges
) <= 2)
645 # Mark the first megabyte of memory as reserved
646 X86E820Entry(addr
= 0, size
= '639kB', range_type
= 1),
647 X86E820Entry(addr
= 0x9fc00, size
= '385kB', range_type
= 2),
648 # Mark the rest of physical memory as available
649 X86E820Entry(addr
= 0x100000,
650 size
= '%dB' % (self
.mem_ranges
[0].size() - 0x100000),
654 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
655 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
656 # specific range can pass though bridge to iobus.
657 if len(self
.mem_ranges
) == 1:
658 entries
.append(X86E820Entry(addr
= self
.mem_ranges
[0].size(),
659 size
='%dB' % (0xC0000000 - self
.mem_ranges
[0].size()),
662 # Reserve the last 16kB of the 32-bit address space for the m5op interface
663 entries
.append(X86E820Entry(addr
=0xFFFF0000, size
='64kB', range_type
=2))
665 # In case the physical memory is greater than 3GB, we split it into two
666 # parts and add a separate e820 entry for the second part. This entry
667 # starts at 0x100000000, which is the first address after the space
668 # reserved for devices.
669 if len(self
.mem_ranges
) == 2:
670 entries
.append(X86E820Entry(addr
= 0x100000000,
671 size
= '%dB' % (self
.mem_ranges
[1].size()), range_type
= 1))
673 self
.e820_table
.entries
= entries
677 cmdline
= 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
678 self
.boot_osflags
= fillInCmdline(mdesc
, cmdline
)
679 self
.kernel
= binary('x86_64-vmlinux-2.6.22.9')
683 def makeDualRoot(full_system
, testSystem
, driveSystem
, dumpfile
):
684 self
= Root(full_system
= full_system
)
685 self
.testsys
= testSystem
686 self
.drivesys
= driveSystem
687 self
.etherlink
= EtherLink()
689 if hasattr(testSystem
, 'realview'):
690 self
.etherlink
.int0
= Parent
.testsys
.realview
.ethernet
.interface
691 self
.etherlink
.int1
= Parent
.drivesys
.realview
.ethernet
.interface
692 elif hasattr(testSystem
, 'tsunami'):
693 self
.etherlink
.int0
= Parent
.testsys
.tsunami
.ethernet
.interface
694 self
.etherlink
.int1
= Parent
.drivesys
.tsunami
.ethernet
.interface
696 fatal("Don't know how to connect these system together")
699 self
.etherdump
= EtherDump(file=dumpfile
)
700 self
.etherlink
.dump
= Parent
.etherdump
705 def makeDistRoot(testSystem
,
715 self
= Root(full_system
= True)
716 self
.testsys
= testSystem
718 self
.etherlink
= DistEtherLink(speed
= linkspeed
,
722 server_name
= server_name
,
723 server_port
= server_port
,
724 sync_start
= sync_start
,
725 sync_repeat
= sync_repeat
)
727 if hasattr(testSystem
, 'realview'):
728 self
.etherlink
.int0
= Parent
.testsys
.realview
.ethernet
.interface
729 elif hasattr(testSystem
, 'tsunami'):
730 self
.etherlink
.int0
= Parent
.testsys
.tsunami
.ethernet
.interface
732 fatal("Don't know how to connect DistEtherLink to this system")
735 self
.etherdump
= EtherDump(file=dumpfile
)
736 self
.etherlink
.dump
= Parent
.etherdump