configs/common/FSConfig.py

   1 # Copyright (c) 2010-2012, 2015-2019 ARM Limited
   2 # All rights reserved.
   3 #
   4 # The license below extends only to copyright in the software and shall
   5 # not be construed as granting a license to any other intellectual
   6 # property including but not limited to intellectual property relating
   7 # to a hardware implementation of the functionality of the software
   8 # licensed hereunder.  You may use the software subject to the license
   9 # terms below provided that you ensure that this notice is replicated
  10 # unmodified and in its entirety in all distributions of the software,
  11 # modified or unmodified, in source code or in binary form.
  12 #
  13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
  14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
  15 # All rights reserved.
  16 #
  17 # Redistribution and use in source and binary forms, with or without
  18 # modification, are permitted provided that the following conditions are
  19 # met: redistributions of source code must retain the above copyright
  20 # notice, this list of conditions and the following disclaimer;
  21 # redistributions in binary form must reproduce the above copyright
  22 # notice, this list of conditions and the following disclaimer in the
  23 # documentation and/or other materials provided with the distribution;
  24 # neither the name of the copyright holders nor the names of its
  25 # contributors may be used to endorse or promote products derived from
  26 # this software without specific prior written permission.
  27 #
  28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39
  40 from __future__ import print_function
  41 from __future__ import absolute_import
  42
  43 import m5
  44 from m5.objects import *
  45 from m5.util import *
  46 from common.Benchmarks import *
  47 from common import ObjectList
  48
  49 # Populate to reflect supported os types per target ISA
  50 os_types = { 'mips'  : [ 'linux' ],
  51              'sparc' : [ 'linux' ],
  52              'x86'   : [ 'linux' ],
  53              'arm'   : [ 'linux',
  54                          'android-gingerbread',
  55                          'android-ics',
  56                          'android-jellybean',
  57                          'android-kitkat',
  58                          'android-nougat', ],
  59            }
  60
  61 class CowIdeDisk(IdeDisk):
  62     image = CowDiskImage(child=RawDiskImage(read_only=True),
  63                          read_only=False)
  64
  65     def childImage(self, ci):
  66         self.image.child.image_file = ci
  67
  68 class MemBus(SystemXBar):
  69     badaddr_responder = BadAddr()
  70     default = Self.badaddr_responder.pio
  71
  72 def attach_9p(parent, bus):
  73     viopci = PciVirtIO()
  74     viopci.vio = VirtIO9PDiod()
  75     viodir = os.path.join(m5.options.outdir, '9p')
  76     viopci.vio.root = os.path.join(viodir, 'share')
  77     viopci.vio.socketPath = os.path.join(viodir, 'socket')
  78     if not os.path.exists(viopci.vio.root):
  79         os.makedirs(viopci.vio.root)
  80     if os.path.exists(viopci.vio.socketPath):
  81         os.remove(viopci.vio.socketPath)
  82     parent.viopci = viopci
  83     parent.attachPciDevice(viopci, bus)
  84
  85 def fillInCmdline(mdesc, template, **kwargs):
  86     kwargs.setdefault('rootdev', mdesc.rootdev())
  87     kwargs.setdefault('mem', mdesc.mem())
  88     kwargs.setdefault('script', mdesc.script())
  89     return template % kwargs
  90
  91 def makeCowDisks(disk_paths):
  92     disks = []
  93     for disk_path in disk_paths:
  94         disk = CowIdeDisk(driveID='master')
  95         disk.childImage(disk_path);
  96         disks.append(disk)
  97     return disks
  98
  99 def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
 100     # Constants from iob.cc and uart8250.cc
 101     iob_man_addr = 0x9800000000
 102     uart_pio_size = 8
 103
 104     class CowMmDisk(MmDisk):
 105         image = CowDiskImage(child=RawDiskImage(read_only=True),
 106                              read_only=False)
 107
 108         def childImage(self, ci):
 109             self.image.child.image_file = ci
 110
 111     self = SparcSystem()
 112     if not mdesc:
 113         # generic system
 114         mdesc = SysConfig()
 115     self.readfile = mdesc.script()
 116     self.iobus = IOXBar()
 117     self.membus = MemBus()
 118     self.bridge = Bridge(delay='50ns')
 119     self.t1000 = T1000()
 120     self.t1000.attachOnChipIO(self.membus)
 121     self.t1000.attachIO(self.iobus)
 122     self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
 123                        AddrRange(Addr('2GB'), size ='256MB')]
 124     self.bridge.master = self.iobus.slave
 125     self.bridge.slave = self.membus.master
 126     self.rom.port = self.membus.master
 127     self.nvram.port = self.membus.master
 128     self.hypervisor_desc.port = self.membus.master
 129     self.partition_desc.port = self.membus.master
 130     self.intrctrl = IntrControl()
 131     self.disk0 = CowMmDisk()
 132     self.disk0.childImage(mdesc.disks()[0])
 133     self.disk0.pio = self.iobus.master
 134
 135     # The puart0 and hvuart are placed on the IO bus, so create ranges
 136     # for them. The remaining IO range is rather fragmented, so poke
 137     # holes for the iob and partition descriptors etc.
 138     self.bridge.ranges = \
 139         [
 140         AddrRange(self.t1000.puart0.pio_addr,
 141                   self.t1000.puart0.pio_addr + uart_pio_size - 1),
 142         AddrRange(self.disk0.pio_addr,
 143                   self.t1000.fake_jbi.pio_addr +
 144                   self.t1000.fake_jbi.pio_size - 1),
 145         AddrRange(self.t1000.fake_clk.pio_addr,
 146                   iob_man_addr - 1),
 147         AddrRange(self.t1000.fake_l2_1.pio_addr,
 148                   self.t1000.fake_ssi.pio_addr +
 149                   self.t1000.fake_ssi.pio_size - 1),
 150         AddrRange(self.t1000.hvuart.pio_addr,
 151                   self.t1000.hvuart.pio_addr + uart_pio_size - 1)
 152         ]
 153     self.reset_bin = binary('reset_new.bin')
 154     self.hypervisor_bin = binary('q_new.bin')
 155     self.openboot_bin = binary('openboot_new.bin')
 156     self.nvram_bin = binary('nvram1')
 157     self.hypervisor_desc_bin = binary('1up-hv.bin')
 158     self.partition_desc_bin = binary('1up-md.bin')
 159
 160     self.system_port = self.membus.slave
 161
 162     return self
 163
 164 def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
 165                   dtb_filename=None, bare_metal=False, cmdline=None,
 166                   external_memory="", ruby=False, security=False,
 167                   vio_9p=None, bootloader=None):
 168     assert machine_type
 169
 170     pci_devices = []
 171
 172     if bare_metal:
 173         self = ArmSystem()
 174     else:
 175         self = LinuxArmSystem()
 176
 177     if not mdesc:
 178         # generic system
 179         mdesc = SysConfig()
 180
 181     self.readfile = mdesc.script()
 182     self.iobus = IOXBar()
 183     if not ruby:
 184         self.bridge = Bridge(delay='50ns')
 185         self.bridge.master = self.iobus.slave
 186         self.membus = MemBus()
 187         self.membus.badaddr_responder.warn_access = "warn"
 188         self.bridge.slave = self.membus.master
 189
 190     self.mem_mode = mem_mode
 191
 192     platform_class = ObjectList.platform_list.get(machine_type)
 193     # Resolve the real platform name, the original machine_type
 194     # variable might have been an alias.
 195     machine_type = platform_class.__name__
 196     self.realview = platform_class()
 197     self._bootmem = self.realview.bootmem
 198
 199     if isinstance(self.realview, VExpress_EMM64):
 200         if os.path.split(mdesc.disks()[0])[-1] == 'linux-aarch32-ael.img':
 201             print("Selected 64-bit ARM architecture, updating default "
 202                   "disk image...")
 203             mdesc.diskname = 'linaro-minimal-aarch64.img'
 204
 205
 206     # Attach any PCI devices this platform supports
 207     self.realview.attachPciDevices()
 208
 209     disks = makeCowDisks(mdesc.disks())
 210     # Old platforms have a built-in IDE or CF controller. Default to
 211     # the IDE controller if both exist. New platforms expect the
 212     # storage controller to be added from the config script.
 213     if hasattr(self.realview, "ide"):
 214         self.realview.ide.disks = disks
 215     elif hasattr(self.realview, "cf_ctrl"):
 216         self.realview.cf_ctrl.disks = disks
 217     else:
 218         self.pci_ide = IdeController(disks=disks)
 219         pci_devices.append(self.pci_ide)
 220
 221     self.mem_ranges = []
 222     size_remain = long(Addr(mdesc.mem()))
 223     for region in self.realview._mem_regions:
 224         if size_remain > long(region.size()):
 225             self.mem_ranges.append(region)
 226             size_remain = size_remain - long(region.size())
 227         else:
 228             self.mem_ranges.append(AddrRange(region.start, size=size_remain))
 229             size_remain = 0
 230             break
 231         warn("Memory size specified spans more than one region. Creating" \
 232              " another memory controller for that range.")
 233
 234     if size_remain > 0:
 235         fatal("The currently selected ARM platforms doesn't support" \
 236               " the amount of DRAM you've selected. Please try" \
 237               " another platform")
 238
 239     self.have_security = security
 240
 241     if bare_metal:
 242         # EOT character on UART will end the simulation
 243         self.realview.uart[0].end_on_eot = True
 244     else:
 245         if dtb_filename:
 246             self.dtb_filename = binary(dtb_filename)
 247
 248         self.machine_type = machine_type if machine_type in ArmMachineType.map \
 249                             else "DTOnly"
 250
 251         # Ensure that writes to the UART actually go out early in the boot
 252         if not cmdline:
 253             cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
 254                       'lpj=19988480 norandmaps rw loglevel=8 ' + \
 255                       'mem=%(mem)s root=%(rootdev)s'
 256
 257         self.realview.setupBootLoader(self, binary, bootloader)
 258
 259         if hasattr(self.realview.gic, 'cpu_addr'):
 260             self.gic_cpu_addr = self.realview.gic.cpu_addr
 261
 262         self.flags_addr = self.realview.realview_io.pio_addr + 0x30
 263
 264         # This check is for users who have previously put 'android' in
 265         # the disk image filename to tell the config scripts to
 266         # prepare the kernel with android-specific boot options. That
 267         # behavior has been replaced with a more explicit option per
 268         # the error message below. The disk can have any name now and
 269         # doesn't need to include 'android' substring.
 270         if (mdesc.disks() and
 271                 os.path.split(mdesc.disks()[0])[-1]).lower().count('android'):
 272             if 'android' not in mdesc.os_type():
 273                 fatal("It looks like you are trying to boot an Android " \
 274                       "platform.  To boot Android, you must specify " \
 275                       "--os-type with an appropriate Android release on " \
 276                       "the command line.")
 277
 278         # android-specific tweaks
 279         if 'android' in mdesc.os_type():
 280             # generic tweaks
 281             cmdline += " init=/init"
 282
 283             # release-specific tweaks
 284             if 'kitkat' in mdesc.os_type():
 285                 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
 286                            "android.bootanim=0 "
 287             elif 'nougat' in mdesc.os_type():
 288                 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
 289                            "android.bootanim=0 " + \
 290                            "vmalloc=640MB " + \
 291                            "android.early.fstab=/fstab.gem5 " + \
 292                            "androidboot.selinux=permissive " + \
 293                            "video=Virtual-1:1920x1080-16"
 294
 295         self.boot_osflags = fillInCmdline(mdesc, cmdline)
 296
 297     if external_memory:
 298         # I/O traffic enters iobus
 299         self.external_io = ExternalMaster(port_data="external_io",
 300                                           port_type=external_memory)
 301         self.external_io.port = self.iobus.slave
 302
 303         # Ensure iocache only receives traffic destined for (actual) memory.
 304         self.iocache = ExternalSlave(port_data="iocache",
 305                                      port_type=external_memory,
 306                                      addr_ranges=self.mem_ranges)
 307         self.iocache.port = self.iobus.master
 308
 309         # Let system_port get to nvmem and nothing else.
 310         self.bridge.ranges = [self.realview.nvmem.range]
 311
 312         self.realview.attachOnChipIO(self.iobus)
 313         # Attach off-chip devices
 314         self.realview.attachIO(self.iobus)
 315     elif ruby:
 316         self._dma_ports = [ ]
 317         self._mem_ports = [ ]
 318         self.realview.attachOnChipIO(self.iobus,
 319             dma_ports=self._dma_ports, mem_ports=self._mem_ports)
 320         self.realview.attachIO(self.iobus, dma_ports=self._dma_ports)
 321     else:
 322         self.realview.attachOnChipIO(self.membus, self.bridge)
 323         # Attach off-chip devices
 324         self.realview.attachIO(self.iobus)
 325
 326     for dev in pci_devices:
 327         self.realview.attachPciDevice(
 328             dev, self.iobus,
 329             dma_ports=self._dma_ports if ruby else None)
 330
 331     self.intrctrl = IntrControl()
 332     self.terminal = Terminal()
 333     self.vncserver = VncServer()
 334
 335     if vio_9p:
 336         attach_9p(self.realview, self.iobus)
 337
 338     if not ruby:
 339         self.system_port = self.membus.slave
 340
 341     if ruby:
 342         if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
 343             fatal("The MI_example protocol cannot implement Load/Store "
 344                   "Exclusive operations. Multicore ARM systems configured "
 345                   "with the MI_example protocol will not work properly.")
 346         warn("You are trying to use Ruby on ARM, which is not working "
 347              "properly yet.")
 348
 349     return self
 350
 351
 352 def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
 353     class BaseMalta(Malta):
 354         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 355         ide = IdeController(disks=Parent.disks,
 356                             pci_func=0, pci_dev=0, pci_bus=0)
 357
 358     self = LinuxMipsSystem()
 359     if not mdesc:
 360         # generic system
 361         mdesc = SysConfig()
 362     self.readfile = mdesc.script()
 363     self.iobus = IOXBar()
 364     self.membus = MemBus()
 365     self.bridge = Bridge(delay='50ns')
 366     self.mem_ranges = [AddrRange('1GB')]
 367     self.bridge.master = self.iobus.slave
 368     self.bridge.slave = self.membus.master
 369     self.disks = makeCowDisks(mdesc.disks())
 370     self.malta = BaseMalta()
 371     self.malta.attachIO(self.iobus)
 372     self.malta.ide.pio = self.iobus.master
 373     self.malta.ide.dma = self.iobus.slave
 374     self.malta.ethernet.pio = self.iobus.master
 375     self.malta.ethernet.dma = self.iobus.slave
 376     self.simple_disk = SimpleDisk(disk=RawDiskImage(
 377         image_file = mdesc.disks()[0], read_only = True))
 378     self.intrctrl = IntrControl()
 379     self.mem_mode = mem_mode
 380     self.terminal = Terminal()
 381     self.console = binary('mips/console')
 382     if not cmdline:
 383         cmdline = 'root=/dev/hda1 console=ttyS0'
 384     self.boot_osflags = fillInCmdline(mdesc, cmdline)
 385
 386     self.system_port = self.membus.slave
 387
 388     return self
 389
 390 def x86IOAddress(port):
 391     IO_address_space_base = 0x8000000000000000
 392     return IO_address_space_base + port
 393
 394 def connectX86ClassicSystem(x86_sys, numCPUs):
 395     # Constants similar to x86_traits.hh
 396     IO_address_space_base = 0x8000000000000000
 397     pci_config_address_space_base = 0xc000000000000000
 398     interrupts_address_space_base = 0xa000000000000000
 399     APIC_range_size = 1 << 12;
 400
 401     x86_sys.membus = MemBus()
 402
 403     # North Bridge
 404     x86_sys.iobus = IOXBar()
 405     x86_sys.bridge = Bridge(delay='50ns')
 406     x86_sys.bridge.master = x86_sys.iobus.slave
 407     x86_sys.bridge.slave = x86_sys.membus.master
 408     # Allow the bridge to pass through:
 409     #  1) kernel configured PCI device memory map address: address range
 410     #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
 411     #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
 412     #  3) everything in the IO address range up to the local APIC, and
 413     #  4) then the entire PCI address space and beyond.
 414     x86_sys.bridge.ranges = \
 415         [
 416         AddrRange(0xC0000000, 0xFFFF0000),
 417         AddrRange(IO_address_space_base,
 418                   interrupts_address_space_base - 1),
 419         AddrRange(pci_config_address_space_base,
 420                   Addr.max)
 421         ]
 422
 423     # Create a bridge from the IO bus to the memory bus to allow access to
 424     # the local APIC (two pages)
 425     x86_sys.apicbridge = Bridge(delay='50ns')
 426     x86_sys.apicbridge.slave = x86_sys.iobus.master
 427     x86_sys.apicbridge.master = x86_sys.membus.slave
 428     x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
 429                                            interrupts_address_space_base +
 430                                            numCPUs * APIC_range_size
 431                                            - 1)]
 432
 433     # connect the io bus
 434     x86_sys.pc.attachIO(x86_sys.iobus)
 435
 436     x86_sys.system_port = x86_sys.membus.slave
 437
 438 def connectX86RubySystem(x86_sys):
 439     # North Bridge
 440     x86_sys.iobus = IOXBar()
 441
 442     # add the ide to the list of dma devices that later need to attach to
 443     # dma controllers
 444     x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
 445     x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
 446
 447
 448 def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
 449     if self == None:
 450         self = X86System()
 451
 452     if not mdesc:
 453         # generic system
 454         mdesc = SysConfig()
 455     self.readfile = mdesc.script()
 456
 457     self.mem_mode = mem_mode
 458
 459     # Physical memory
 460     # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
 461     # for various devices.  Hence, if the physical memory size is greater than
 462     # 3GB, we need to split it into two parts.
 463     excess_mem_size = \
 464         convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
 465     if excess_mem_size <= 0:
 466         self.mem_ranges = [AddrRange(mdesc.mem())]
 467     else:
 468         warn("Physical memory size specified is %s which is greater than " \
 469              "3GB.  Twice the number of memory controllers would be " \
 470              "created."  % (mdesc.mem()))
 471
 472         self.mem_ranges = [AddrRange('3GB'),
 473             AddrRange(Addr('4GB'), size = excess_mem_size)]
 474
 475     # Platform
 476     self.pc = Pc()
 477
 478     # Create and connect the busses required by each memory system
 479     if Ruby:
 480         connectX86RubySystem(self)
 481     else:
 482         connectX86ClassicSystem(self, numCPUs)
 483
 484     self.intrctrl = IntrControl()
 485
 486     # Disks
 487     disks = makeCowDisks(mdesc.disks())
 488     self.pc.south_bridge.ide.disks = disks
 489
 490     # Add in a Bios information structure.
 491     structures = [X86SMBiosBiosInformation()]
 492     self.smbios_table.structures = structures
 493
 494     # Set up the Intel MP table
 495     base_entries = []
 496     ext_entries = []
 497     for i in range(numCPUs):
 498         bp = X86IntelMPProcessor(
 499                 local_apic_id = i,
 500                 local_apic_version = 0x14,
 501                 enable = True,
 502                 bootstrap = (i == 0))
 503         base_entries.append(bp)
 504     io_apic = X86IntelMPIOAPIC(
 505             id = numCPUs,
 506             version = 0x11,
 507             enable = True,
 508             address = 0xfec00000)
 509     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 510     base_entries.append(io_apic)
 511     # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
 512     # but linux kernel cannot config PCI device if it was not connected to PCI bus,
 513     # so we fix PCI bus id to 0, and ISA bus id to 1.
 514     pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI   ')
 515     base_entries.append(pci_bus)
 516     isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA   ')
 517     base_entries.append(isa_bus)
 518     connect_busses = X86IntelMPBusHierarchy(bus_id=1,
 519             subtractive_decode=True, parent_bus=0)
 520     ext_entries.append(connect_busses)
 521     pci_dev4_inta = X86IntelMPIOIntAssignment(
 522             interrupt_type = 'INT',
 523             polarity = 'ConformPolarity',
 524             trigger = 'ConformTrigger',
 525             source_bus_id = 0,
 526             source_bus_irq = 0 + (4 << 2),
 527             dest_io_apic_id = io_apic.id,
 528             dest_io_apic_intin = 16)
 529     base_entries.append(pci_dev4_inta)
 530     def assignISAInt(irq, apicPin):
 531         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 532                 interrupt_type = 'ExtInt',
 533                 polarity = 'ConformPolarity',
 534                 trigger = 'ConformTrigger',
 535                 source_bus_id = 1,
 536                 source_bus_irq = irq,
 537                 dest_io_apic_id = io_apic.id,
 538                 dest_io_apic_intin = 0)
 539         base_entries.append(assign_8259_to_apic)
 540         assign_to_apic = X86IntelMPIOIntAssignment(
 541                 interrupt_type = 'INT',
 542                 polarity = 'ConformPolarity',
 543                 trigger = 'ConformTrigger',
 544                 source_bus_id = 1,
 545                 source_bus_irq = irq,
 546                 dest_io_apic_id = io_apic.id,
 547                 dest_io_apic_intin = apicPin)
 548         base_entries.append(assign_to_apic)
 549     assignISAInt(0, 2)
 550     assignISAInt(1, 1)
 551     for i in range(3, 15):
 552         assignISAInt(i, i)
 553     self.intel_mp_table.base_entries = base_entries
 554     self.intel_mp_table.ext_entries = ext_entries
 555
 556 def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
 557                        cmdline=None):
 558     self = LinuxX86System()
 559
 560     # Build up the x86 system and then specialize it for Linux
 561     makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
 562
 563     # We assume below that there's at least 1MB of memory. We'll require 2
 564     # just to avoid corner cases.
 565     phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
 566     assert(phys_mem_size >= 0x200000)
 567     assert(len(self.mem_ranges) <= 2)
 568
 569     entries = \
 570        [
 571         # Mark the first megabyte of memory as reserved
 572         X86E820Entry(addr = 0, size = '639kB', range_type = 1),
 573         X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
 574         # Mark the rest of physical memory as available
 575         X86E820Entry(addr = 0x100000,
 576                 size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
 577                 range_type = 1),
 578         ]
 579
 580     # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
 581     # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
 582     # specific range can pass though bridge to iobus.
 583     if len(self.mem_ranges) == 1:
 584         entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
 585             size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
 586             range_type=2))
 587
 588     # Reserve the last 16kB of the 32-bit address space for the m5op interface
 589     entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
 590
 591     # In case the physical memory is greater than 3GB, we split it into two
 592     # parts and add a separate e820 entry for the second part.  This entry
 593     # starts at 0x100000000,  which is the first address after the space
 594     # reserved for devices.
 595     if len(self.mem_ranges) == 2:
 596         entries.append(X86E820Entry(addr = 0x100000000,
 597             size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
 598
 599     self.e820_table.entries = entries
 600
 601     # Command line
 602     if not cmdline:
 603         cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
 604     self.boot_osflags = fillInCmdline(mdesc, cmdline)
 605     return self
 606
 607
 608 def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
 609     self = Root(full_system = full_system)
 610     self.testsys = testSystem
 611     self.drivesys = driveSystem
 612     self.etherlink = EtherLink()
 613
 614     if hasattr(testSystem, 'realview'):
 615         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 616         self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
 617     elif hasattr(testSystem, 'tsunami'):
 618         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 619         self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 620     else:
 621         fatal("Don't know how to connect these system together")
 622
 623     if dumpfile:
 624         self.etherdump = EtherDump(file=dumpfile)
 625         self.etherlink.dump = Parent.etherdump
 626
 627     return self
 628
 629
 630 def makeDistRoot(testSystem,
 631                  rank,
 632                  size,
 633                  server_name,
 634                  server_port,
 635                  sync_repeat,
 636                  sync_start,
 637                  linkspeed,
 638                  linkdelay,
 639                  dumpfile):
 640     self = Root(full_system = True)
 641     self.testsys = testSystem
 642
 643     self.etherlink = DistEtherLink(speed = linkspeed,
 644                                    delay = linkdelay,
 645                                    dist_rank = rank,
 646                                    dist_size = size,
 647                                    server_name = server_name,
 648                                    server_port = server_port,
 649                                    sync_start = sync_start,
 650                                    sync_repeat = sync_repeat)
 651
 652     if hasattr(testSystem, 'realview'):
 653         self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
 654     elif hasattr(testSystem, 'tsunami'):
 655         self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 656     else:
 657         fatal("Don't know how to connect DistEtherLink to this system")
 658
 659     if dumpfile:
 660         self.etherdump = EtherDump(file=dumpfile)
 661         self.etherlink.dump = Parent.etherdump
 662
 663     return self