configs/common/FSConfig.py

   1 # Copyright (c) 2006-2008 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
   6 # met: redistributions of source code must retain the above copyright
   7 # notice, this list of conditions and the following disclaimer;
   8 # redistributions in binary form must reproduce the above copyright
   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Kevin Lim
  28
  29 from m5.objects import *
  30 from Benchmarks import *
  31
  32 class CowIdeDisk(IdeDisk):
  33     image = CowDiskImage(child=RawDiskImage(read_only=True),
  34                          read_only=False)
  35
  36     def childImage(self, ci):
  37         self.image.child.image_file = ci
  38
  39 class MemBus(Bus):
  40     badaddr_responder = BadAddr()
  41     default = Self.badaddr_responder.pio
  42
  43
  44 def makeLinuxAlphaSystem(mem_mode, mdesc = None):
  45     class BaseTsunami(Tsunami):
  46         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
  47         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
  48                             pci_func=0, pci_dev=0, pci_bus=0)
  49
  50     self = LinuxAlphaSystem()
  51     if not mdesc:
  52         # generic system
  53         mdesc = SysConfig()
  54     self.readfile = mdesc.script()
  55     self.iobus = Bus(bus_id=0)
  56     self.membus = MemBus(bus_id=1)
  57     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
  58     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
  59     self.bridge.side_a = self.iobus.port
  60     self.bridge.side_b = self.membus.port
  61     self.physmem.port = self.membus.port
  62     self.disk0 = CowIdeDisk(driveID='master')
  63     self.disk2 = CowIdeDisk(driveID='master')
  64     self.disk0.childImage(mdesc.disk())
  65     self.disk2.childImage(disk('linux-bigswap2.img'))
  66     self.tsunami = BaseTsunami()
  67     self.tsunami.attachIO(self.iobus)
  68     self.tsunami.ide.pio = self.iobus.port
  69     self.tsunami.ethernet.pio = self.iobus.port
  70     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
  71                                                read_only = True))
  72     self.intrctrl = IntrControl()
  73     self.mem_mode = mem_mode
  74     self.terminal = Terminal()
  75     self.kernel = binary('vmlinux')
  76     self.pal = binary('ts_osfpal')
  77     self.console = binary('console')
  78     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
  79
  80     return self
  81
  82 def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
  83     class BaseTsunami(Tsunami):
  84         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
  85         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
  86                             pci_func=0, pci_dev=0, pci_bus=0)
  87
  88     physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
  89     self = LinuxAlphaSystem(physmem = physmem)
  90     if not mdesc:
  91         # generic system
  92         mdesc = SysConfig()
  93     self.readfile = mdesc.script()
  94
  95     # Create pio bus to connect all device pio ports to rubymem's pio port
  96     self.piobus = Bus(bus_id=0)
  97
  98     #
  99     # Pio functional accesses from devices need direct access to memory
 100     # RubyPort currently does support functional accesses.  Therefore provide
 101     # the piobus a direct connection to physical memory
 102     #
 103     self.piobus.port = physmem.port
 104
 105     self.disk0 = CowIdeDisk(driveID='master')
 106     self.disk2 = CowIdeDisk(driveID='master')
 107     self.disk0.childImage(mdesc.disk())
 108     self.disk2.childImage(disk('linux-bigswap2.img'))
 109     self.tsunami = BaseTsunami()
 110     self.tsunami.attachIO(self.piobus)
 111     self.tsunami.ide.pio = self.piobus.port
 112     self.tsunami.ethernet.pio = self.piobus.port
 113
 114     #
 115     # store the dma devices for later connection to dma ruby ports
 116     #
 117     self.dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
 118
 119     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 120                                                read_only = True))
 121     self.intrctrl = IntrControl()
 122     self.mem_mode = mem_mode
 123     self.terminal = Terminal()
 124     self.kernel = binary('vmlinux')
 125     self.pal = binary('ts_osfpal')
 126     self.console = binary('console')
 127     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 128
 129     return self
 130
 131 def makeSparcSystem(mem_mode, mdesc = None):
 132     class CowMmDisk(MmDisk):
 133         image = CowDiskImage(child=RawDiskImage(read_only=True),
 134                              read_only=False)
 135
 136         def childImage(self, ci):
 137             self.image.child.image_file = ci
 138
 139     self = SparcSystem()
 140     if not mdesc:
 141         # generic system
 142         mdesc = SysConfig()
 143     self.readfile = mdesc.script()
 144     self.iobus = Bus(bus_id=0)
 145     self.membus = MemBus(bus_id=1)
 146     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
 147     self.t1000 = T1000()
 148     self.t1000.attachOnChipIO(self.membus)
 149     self.t1000.attachIO(self.iobus)
 150     self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
 151     self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
 152     self.bridge.side_a = self.iobus.port
 153     self.bridge.side_b = self.membus.port
 154     self.physmem.port = self.membus.port
 155     self.physmem2.port = self.membus.port
 156     self.rom.port = self.membus.port
 157     self.nvram.port = self.membus.port
 158     self.hypervisor_desc.port = self.membus.port
 159     self.partition_desc.port = self.membus.port
 160     self.intrctrl = IntrControl()
 161     self.disk0 = CowMmDisk()
 162     self.disk0.childImage(disk('disk.s10hw2'))
 163     self.disk0.pio = self.iobus.port
 164     self.reset_bin = binary('reset_new.bin')
 165     self.hypervisor_bin = binary('q_new.bin')
 166     self.openboot_bin = binary('openboot_new.bin')
 167     self.nvram_bin = binary('nvram1')
 168     self.hypervisor_desc_bin = binary('1up-hv.bin')
 169     self.partition_desc_bin = binary('1up-md.bin')
 170
 171     return self
 172
 173 def makeLinuxMipsSystem(mem_mode, mdesc = None):
 174     class BaseMalta(Malta):
 175         ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
 176         ide = IdeController(disks=[Parent.disk0, Parent.disk2],
 177                             pci_func=0, pci_dev=0, pci_bus=0)
 178
 179     self = LinuxMipsSystem()
 180     if not mdesc:
 181         # generic system
 182         mdesc = SysConfig()
 183     self.readfile = mdesc.script()
 184     self.iobus = Bus(bus_id=0)
 185     self.membus = MemBus(bus_id=1)
 186     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
 187     self.physmem = PhysicalMemory(range = AddrRange('1GB'))
 188     self.bridge.side_a = self.iobus.port
 189     self.bridge.side_b = self.membus.port
 190     self.physmem.port = self.membus.port
 191     self.disk0 = CowIdeDisk(driveID='master')
 192     self.disk2 = CowIdeDisk(driveID='master')
 193     self.disk0.childImage(mdesc.disk())
 194     self.disk2.childImage(disk('linux-bigswap2.img'))
 195     self.malta = BaseMalta()
 196     self.malta.attachIO(self.iobus)
 197     self.malta.ide.pio = self.iobus.port
 198     self.malta.ethernet.pio = self.iobus.port
 199     self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
 200                                                read_only = True))
 201     self.intrctrl = IntrControl()
 202     self.mem_mode = mem_mode
 203     self.terminal = Terminal()
 204     self.kernel = binary('mips/vmlinux')
 205     self.console = binary('mips/console')
 206     self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
 207
 208     return self
 209
 210 def x86IOAddress(port):
 211     IO_address_space_base = 0x8000000000000000
 212     return IO_address_space_base + port;
 213
 214 def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
 215     if self == None:
 216         self = X86System()
 217
 218     if not mdesc:
 219         # generic system
 220         mdesc = SysConfig()
 221     mdesc.diskname = 'x86root.img'
 222     self.readfile = mdesc.script()
 223
 224     self.mem_mode = mem_mode
 225
 226     # Physical memory
 227     self.membus = MemBus(bus_id=1)
 228     self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
 229     self.physmem.port = self.membus.port
 230
 231     # North Bridge
 232     self.iobus = Bus(bus_id=0)
 233     self.bridge = Bridge(delay='50ns', nack_delay='4ns')
 234     self.bridge.side_a = self.iobus.port
 235     self.bridge.side_b = self.membus.port
 236
 237     # Platform
 238     self.pc = Pc()
 239     self.pc.attachIO(self.iobus)
 240
 241     self.intrctrl = IntrControl()
 242
 243     # Disks
 244     disk0 = CowIdeDisk(driveID='master')
 245     disk2 = CowIdeDisk(driveID='master')
 246     disk0.childImage(mdesc.disk())
 247     disk2.childImage(disk('linux-bigswap2.img'))
 248     self.pc.south_bridge.ide.disks = [disk0, disk2]
 249
 250     # Add in a Bios information structure.
 251     structures = [X86SMBiosBiosInformation()]
 252     self.smbios_table.structures = structures
 253
 254     # Set up the Intel MP table
 255     for i in xrange(numCPUs):
 256         bp = X86IntelMPProcessor(
 257                 local_apic_id = i,
 258                 local_apic_version = 0x14,
 259                 enable = True,
 260                 bootstrap = (i == 0))
 261         self.intel_mp_table.add_entry(bp)
 262     io_apic = X86IntelMPIOAPIC(
 263             id = numCPUs,
 264             version = 0x11,
 265             enable = True,
 266             address = 0xfec00000)
 267     self.pc.south_bridge.io_apic.apic_id = io_apic.id
 268     self.intel_mp_table.add_entry(io_apic)
 269     isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
 270     self.intel_mp_table.add_entry(isa_bus)
 271     pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
 272     self.intel_mp_table.add_entry(pci_bus)
 273     connect_busses = X86IntelMPBusHierarchy(bus_id=0,
 274             subtractive_decode=True, parent_bus=1)
 275     self.intel_mp_table.add_entry(connect_busses)
 276     pci_dev4_inta = X86IntelMPIOIntAssignment(
 277             interrupt_type = 'INT',
 278             polarity = 'ConformPolarity',
 279             trigger = 'ConformTrigger',
 280             source_bus_id = 1,
 281             source_bus_irq = 0 + (4 << 2),
 282             dest_io_apic_id = io_apic.id,
 283             dest_io_apic_intin = 16)
 284     self.intel_mp_table.add_entry(pci_dev4_inta);
 285     def assignISAInt(irq, apicPin):
 286         assign_8259_to_apic = X86IntelMPIOIntAssignment(
 287                 interrupt_type = 'ExtInt',
 288                 polarity = 'ConformPolarity',
 289                 trigger = 'ConformTrigger',
 290                 source_bus_id = 0,
 291                 source_bus_irq = irq,
 292                 dest_io_apic_id = io_apic.id,
 293                 dest_io_apic_intin = 0)
 294         self.intel_mp_table.add_entry(assign_8259_to_apic)
 295         assign_to_apic = X86IntelMPIOIntAssignment(
 296                 interrupt_type = 'INT',
 297                 polarity = 'ConformPolarity',
 298                 trigger = 'ConformTrigger',
 299                 source_bus_id = 0,
 300                 source_bus_irq = irq,
 301                 dest_io_apic_id = io_apic.id,
 302                 dest_io_apic_intin = apicPin)
 303         self.intel_mp_table.add_entry(assign_to_apic)
 304     assignISAInt(0, 2)
 305     assignISAInt(1, 1)
 306     for i in range(3, 15):
 307         assignISAInt(i, i)
 308
 309
 310 def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None):
 311     self = LinuxX86System()
 312
 313     # Build up a generic x86 system and then specialize it for Linux
 314     makeX86System(mem_mode, numCPUs, mdesc, self)
 315
 316     # We assume below that there's at least 1MB of memory. We'll require 2
 317     # just to avoid corner cases.
 318     assert(self.physmem.range.second >= 0x200000)
 319
 320     # Mark the first megabyte of memory as reserved
 321     self.e820_table.entries.append(X86E820Entry(
 322                 addr = 0,
 323                 size = '1MB',
 324                 range_type = 2))
 325
 326     # Mark the rest as available
 327     self.e820_table.entries.append(X86E820Entry(
 328                 addr = 0x100000,
 329                 size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
 330                 range_type = 1))
 331
 332     # Command line
 333     self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
 334                         'root=/dev/hda1'
 335     return self
 336
 337
 338 def makeDualRoot(testSystem, driveSystem, dumpfile):
 339     self = Root()
 340     self.testsys = testSystem
 341     self.drivesys = driveSystem
 342     self.etherlink = EtherLink()
 343     self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
 344     self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
 345
 346     if dumpfile:
 347         self.etherdump = EtherDump(file=dumpfile)
 348         self.etherlink.dump = Parent.etherdump
 349
 350     return self
 351
 352 def setMipsOptions(TestCPUClass):
 353         #CP0 Configuration
 354         TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
 355         TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
 356         TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
 357         TestCPUClass.CoreParams.CP0_PRId_Revision = 0
 358
 359         #CP0 Interrupt Control
 360         TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
 361         TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
 362
 363         # Config Register
 364         #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
 365         #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
 366         TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
 367         TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
 368         TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
 369         TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
 370         #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
 371
 372         #Config 1 Register
 373         TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
 374         TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
 375         # ***VERY IMPORTANT***
 376         # Remember to modify CP0_Config1 according to cache specs
 377         # Examine file ../common/Cache.py
 378         TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
 379         TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
 380         TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
 381         TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
 382         TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
 383         TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
 384         TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
 385         TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
 386         TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
 387         TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
 388         TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
 389         TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
 390         TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
 391
 392         #Config 2 Register
 393         TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
 394         TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
 395         TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
 396         TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
 397         TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
 398         TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
 399         TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
 400         TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
 401         TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
 402
 403
 404         #Config 3 Register
 405         TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
 406         TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
 407         TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
 408         TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
 409         TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
 410         TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
 411         TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
 412         TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
 413         TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
 414
 415         #SRS Ctl - HSS
 416         TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
 417
 418
 419         #TestCPUClass.CoreParams.tlb = TLB()
 420         #TestCPUClass.CoreParams.UnifiedTLB = 1