1 # Copyright (c) 2010-2012, 2015-2019 ARM Limited
4 # The license below extends only to copyright in the software and shall
5 # not be construed as granting a license to any other intellectual
6 # property including but not limited to intellectual property relating
7 # to a hardware implementation of the functionality of the software
8 # licensed hereunder. You may use the software subject to the license
9 # terms below provided that you ensure that this notice is replicated
10 # unmodified and in its entirety in all distributions of the software,
11 # modified or unmodified, in source code or in binary form.
13 # Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14 # Copyright (c) 2006-2008 The Regents of The University of Michigan
15 # All rights reserved.
17 # Redistribution and use in source and binary forms, with or without
18 # modification, are permitted provided that the following conditions are
19 # met: redistributions of source code must retain the above copyright
20 # notice, this list of conditions and the following disclaimer;
21 # redistributions in binary form must reproduce the above copyright
22 # notice, this list of conditions and the following disclaimer in the
23 # documentation and/or other materials provided with the distribution;
24 # neither the name of the copyright holders nor the names of its
25 # contributors may be used to endorse or promote products derived from
26 # this software without specific prior written permission.
28 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 from __future__
import print_function
41 from __future__
import absolute_import
44 from m5
.objects
import *
46 from common
.Benchmarks
import *
47 from common
import ObjectList
49 # Populate to reflect supported os types per target ISA
50 os_types
= { 'mips' : [ 'linux' ],
51 'sparc' : [ 'linux' ],
54 'android-gingerbread',
61 class CowIdeDisk(IdeDisk
):
62 image
= CowDiskImage(child
=RawDiskImage(read_only
=True),
65 def childImage(self
, ci
):
66 self
.image
.child
.image_file
= ci
68 class MemBus(SystemXBar
):
69 badaddr_responder
= BadAddr()
70 default
= Self
.badaddr_responder
.pio
72 def attach_9p(parent
, bus
):
74 viopci
.vio
= VirtIO9PDiod()
75 viodir
= os
.path
.join(m5
.options
.outdir
, '9p')
76 viopci
.vio
.root
= os
.path
.join(viodir
, 'share')
77 viopci
.vio
.socketPath
= os
.path
.join(viodir
, 'socket')
78 if not os
.path
.exists(viopci
.vio
.root
):
79 os
.makedirs(viopci
.vio
.root
)
80 if os
.path
.exists(viopci
.vio
.socketPath
):
81 os
.remove(viopci
.vio
.socketPath
)
82 parent
.viopci
= viopci
83 parent
.attachPciDevice(viopci
, bus
)
85 def fillInCmdline(mdesc
, template
, **kwargs
):
86 kwargs
.setdefault('rootdev', mdesc
.rootdev())
87 kwargs
.setdefault('mem', mdesc
.mem())
88 kwargs
.setdefault('script', mdesc
.script())
89 return template
% kwargs
91 def makeCowDisks(disk_paths
):
93 for disk_path
in disk_paths
:
94 disk
= CowIdeDisk(driveID
='master')
95 disk
.childImage(disk_path
);
99 def makeSparcSystem(mem_mode
, mdesc
=None, cmdline
=None):
100 # Constants from iob.cc and uart8250.cc
101 iob_man_addr
= 0x9800000000
104 class CowMmDisk(MmDisk
):
105 image
= CowDiskImage(child
=RawDiskImage(read_only
=True),
108 def childImage(self
, ci
):
109 self
.image
.child
.image_file
= ci
115 self
.readfile
= mdesc
.script()
116 self
.iobus
= IOXBar()
117 self
.membus
= MemBus()
118 self
.bridge
= Bridge(delay
='50ns')
120 self
.t1000
.attachOnChipIO(self
.membus
)
121 self
.t1000
.attachIO(self
.iobus
)
122 self
.mem_ranges
= [AddrRange(Addr('1MB'), size
= '64MB'),
123 AddrRange(Addr('2GB'), size
='256MB')]
124 self
.bridge
.master
= self
.iobus
.slave
125 self
.bridge
.slave
= self
.membus
.master
126 self
.intrctrl
= IntrControl()
127 self
.disk0
= CowMmDisk()
128 self
.disk0
.childImage(mdesc
.disks()[0])
129 self
.disk0
.pio
= self
.iobus
.master
131 # The puart0 and hvuart are placed on the IO bus, so create ranges
132 # for them. The remaining IO range is rather fragmented, so poke
133 # holes for the iob and partition descriptors etc.
134 self
.bridge
.ranges
= \
136 AddrRange(self
.t1000
.puart0
.pio_addr
,
137 self
.t1000
.puart0
.pio_addr
+ uart_pio_size
- 1),
138 AddrRange(self
.disk0
.pio_addr
,
139 self
.t1000
.fake_jbi
.pio_addr
+
140 self
.t1000
.fake_jbi
.pio_size
- 1),
141 AddrRange(self
.t1000
.fake_clk
.pio_addr
,
143 AddrRange(self
.t1000
.fake_l2_1
.pio_addr
,
144 self
.t1000
.fake_ssi
.pio_addr
+
145 self
.t1000
.fake_ssi
.pio_size
- 1),
146 AddrRange(self
.t1000
.hvuart
.pio_addr
,
147 self
.t1000
.hvuart
.pio_addr
+ uart_pio_size
- 1)
150 workload
= SparcFsWorkload()
152 # ROM for OBP/Reset/Hypervisor
153 self
.rom
= SimpleMemory(image_file
=binary('t1000_rom.bin'),
154 range=AddrRange(0xfff0000000, size
='8MB'))
156 self
.nvram
= SimpleMemory(image_file
=binary('nvram1'),
157 range=AddrRange(0x1f11000000, size
='8kB'))
158 # hypervisor description
159 self
.hypervisor_desc
= SimpleMemory(image_file
=binary('1up-hv.bin'),
160 range=AddrRange(0x1f12080000, size
='8kB'))
161 # partition description
162 self
.partition_desc
= SimpleMemory(image_file
=binary('1up-md.bin'),
163 range=AddrRange(0x1f12000000, size
='8kB'))
165 self
.rom
.port
= self
.membus
.master
166 self
.nvram
.port
= self
.membus
.master
167 self
.hypervisor_desc
.port
= self
.membus
.master
168 self
.partition_desc
.port
= self
.membus
.master
170 self
.system_port
= self
.membus
.slave
172 self
.workload
= workload
176 def makeArmSystem(mem_mode
, machine_type
, num_cpus
=1, mdesc
=None,
177 dtb_filename
=None, bare_metal
=False, cmdline
=None,
178 external_memory
="", ruby
=False, security
=False,
179 vio_9p
=None, bootloader
=None):
190 self
.readfile
= mdesc
.script()
191 self
.iobus
= IOXBar()
193 self
.bridge
= Bridge(delay
='50ns')
194 self
.bridge
.master
= self
.iobus
.slave
195 self
.membus
= MemBus()
196 self
.membus
.badaddr_responder
.warn_access
= "warn"
197 self
.bridge
.slave
= self
.membus
.master
199 self
.mem_mode
= mem_mode
201 platform_class
= ObjectList
.platform_list
.get(machine_type
)
202 # Resolve the real platform name, the original machine_type
203 # variable might have been an alias.
204 machine_type
= platform_class
.__name
__
205 self
.realview
= platform_class()
206 self
._bootmem
= self
.realview
.bootmem
208 # Attach any PCI devices this platform supports
209 self
.realview
.attachPciDevices()
211 disks
= makeCowDisks(mdesc
.disks())
212 # Old platforms have a built-in IDE or CF controller. Default to
213 # the IDE controller if both exist. New platforms expect the
214 # storage controller to be added from the config script.
215 if hasattr(self
.realview
, "ide"):
216 self
.realview
.ide
.disks
= disks
217 elif hasattr(self
.realview
, "cf_ctrl"):
218 self
.realview
.cf_ctrl
.disks
= disks
220 self
.pci_ide
= IdeController(disks
=disks
)
221 pci_devices
.append(self
.pci_ide
)
224 size_remain
= long(Addr(mdesc
.mem()))
225 for region
in self
.realview
._mem
_regions
:
226 if size_remain
> long(region
.size()):
227 self
.mem_ranges
.append(region
)
228 size_remain
= size_remain
- long(region
.size())
230 self
.mem_ranges
.append(AddrRange(region
.start
, size
=size_remain
))
233 warn("Memory size specified spans more than one region. Creating" \
234 " another memory controller for that range.")
237 fatal("The currently selected ARM platforms doesn't support" \
238 " the amount of DRAM you've selected. Please try" \
241 self
.have_security
= security
244 # EOT character on UART will end the simulation
245 self
.realview
.uart
[0].end_on_eot
= True
246 self
.workload
= ArmFsWorkload(atags_addr
=0)
248 workload
= ArmFsLinux()
251 workload
.dtb_filename
= binary(dtb_filename
)
253 workload
.machine_type
= \
254 machine_type
if machine_type
in ArmMachineType
.map else "DTOnly"
256 # Ensure that writes to the UART actually go out early in the boot
258 cmdline
= 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
259 'lpj=19988480 norandmaps rw loglevel=8 ' + \
260 'mem=%(mem)s root=%(rootdev)s'
262 if hasattr(self
.realview
.gic
, 'cpu_addr'):
263 self
.gic_cpu_addr
= self
.realview
.gic
.cpu_addr
265 self
.flags_addr
= self
.realview
.realview_io
.pio_addr
+ 0x30
267 # This check is for users who have previously put 'android' in
268 # the disk image filename to tell the config scripts to
269 # prepare the kernel with android-specific boot options. That
270 # behavior has been replaced with a more explicit option per
271 # the error message below. The disk can have any name now and
272 # doesn't need to include 'android' substring.
273 if (mdesc
.disks() and
274 os
.path
.split(mdesc
.disks()[0])[-1].lower().count('android')):
275 if 'android' not in mdesc
.os_type():
276 fatal("It looks like you are trying to boot an Android " \
277 "platform. To boot Android, you must specify " \
278 "--os-type with an appropriate Android release on " \
281 # android-specific tweaks
282 if 'android' in mdesc
.os_type():
284 cmdline
+= " init=/init"
286 # release-specific tweaks
287 if 'kitkat' in mdesc
.os_type():
288 cmdline
+= " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
289 "android.bootanim=0 "
290 elif 'nougat' in mdesc
.os_type():
291 cmdline
+= " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \
292 "android.bootanim=0 " + \
294 "android.early.fstab=/fstab.gem5 " + \
295 "androidboot.selinux=permissive " + \
296 "video=Virtual-1:1920x1080-16"
298 workload
.command_line
= fillInCmdline(mdesc
, cmdline
)
300 self
.workload
= workload
302 self
.realview
.setupBootLoader(self
, binary
, bootloader
)
305 # I/O traffic enters iobus
306 self
.external_io
= ExternalMaster(port_data
="external_io",
307 port_type
=external_memory
)
308 self
.external_io
.port
= self
.iobus
.slave
310 # Ensure iocache only receives traffic destined for (actual) memory.
311 self
.iocache
= ExternalSlave(port_data
="iocache",
312 port_type
=external_memory
,
313 addr_ranges
=self
.mem_ranges
)
314 self
.iocache
.port
= self
.iobus
.master
316 # Let system_port get to nvmem and nothing else.
317 self
.bridge
.ranges
= [self
.realview
.nvmem
.range]
319 self
.realview
.attachOnChipIO(self
.iobus
)
320 # Attach off-chip devices
321 self
.realview
.attachIO(self
.iobus
)
323 self
._dma
_ports
= [ ]
324 self
._mem
_ports
= [ ]
325 self
.realview
.attachOnChipIO(self
.iobus
,
326 dma_ports
=self
._dma
_ports
, mem_ports
=self
._mem
_ports
)
327 self
.realview
.attachIO(self
.iobus
, dma_ports
=self
._dma
_ports
)
329 self
.realview
.attachOnChipIO(self
.membus
, self
.bridge
)
330 # Attach off-chip devices
331 self
.realview
.attachIO(self
.iobus
)
333 for dev
in pci_devices
:
334 self
.realview
.attachPciDevice(
336 dma_ports
=self
._dma
_ports
if ruby
else None)
338 self
.intrctrl
= IntrControl()
339 self
.terminal
= Terminal()
340 self
.vncserver
= VncServer()
343 attach_9p(self
.realview
, self
.iobus
)
346 self
.system_port
= self
.membus
.slave
349 if buildEnv
['PROTOCOL'] == 'MI_example' and num_cpus
> 1:
350 fatal("The MI_example protocol cannot implement Load/Store "
351 "Exclusive operations. Multicore ARM systems configured "
352 "with the MI_example protocol will not work properly.")
353 warn("You are trying to use Ruby on ARM, which is not working "
359 def makeLinuxMipsSystem(mem_mode
, mdesc
=None, cmdline
=None):
360 class BaseMalta(Malta
):
361 ethernet
= NSGigE(pci_bus
=0, pci_dev
=1, pci_func
=0)
362 ide
= IdeController(disks
=Parent
.disks
,
363 pci_func
=0, pci_dev
=0, pci_bus
=0)
369 self
.readfile
= mdesc
.script()
370 self
.iobus
= IOXBar()
371 self
.membus
= MemBus()
372 self
.bridge
= Bridge(delay
='50ns')
373 self
.mem_ranges
= [AddrRange('1GB')]
374 self
.bridge
.master
= self
.iobus
.slave
375 self
.bridge
.slave
= self
.membus
.master
376 self
.disks
= makeCowDisks(mdesc
.disks())
377 self
.malta
= BaseMalta()
378 self
.malta
.attachIO(self
.iobus
)
379 self
.malta
.ide
.pio
= self
.iobus
.master
380 self
.malta
.ide
.dma
= self
.iobus
.slave
381 self
.malta
.ethernet
.pio
= self
.iobus
.master
382 self
.malta
.ethernet
.dma
= self
.iobus
.slave
383 self
.simple_disk
= SimpleDisk(disk
=RawDiskImage(
384 image_file
= mdesc
.disks()[0], read_only
= True))
385 self
.intrctrl
= IntrControl()
386 self
.mem_mode
= mem_mode
387 self
.terminal
= Terminal()
388 self
.console
= binary('mips/console')
390 cmdline
= 'root=/dev/hda1 console=ttyS0'
391 self
.workload
= KernelWorkload(command_line
=fillInCmdline(mdesc
, cmdline
))
393 self
.system_port
= self
.membus
.slave
397 def x86IOAddress(port
):
398 IO_address_space_base
= 0x8000000000000000
399 return IO_address_space_base
+ port
401 def connectX86ClassicSystem(x86_sys
, numCPUs
):
402 # Constants similar to x86_traits.hh
403 IO_address_space_base
= 0x8000000000000000
404 pci_config_address_space_base
= 0xc000000000000000
405 interrupts_address_space_base
= 0xa000000000000000
406 APIC_range_size
= 1 << 12;
408 x86_sys
.membus
= MemBus()
411 x86_sys
.iobus
= IOXBar()
412 x86_sys
.bridge
= Bridge(delay
='50ns')
413 x86_sys
.bridge
.master
= x86_sys
.iobus
.slave
414 x86_sys
.bridge
.slave
= x86_sys
.membus
.master
415 # Allow the bridge to pass through:
416 # 1) kernel configured PCI device memory map address: address range
417 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
418 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1),
419 # 3) everything in the IO address range up to the local APIC, and
420 # 4) then the entire PCI address space and beyond.
421 x86_sys
.bridge
.ranges
= \
423 AddrRange(0xC0000000, 0xFFFF0000),
424 AddrRange(IO_address_space_base
,
425 interrupts_address_space_base
- 1),
426 AddrRange(pci_config_address_space_base
,
430 # Create a bridge from the IO bus to the memory bus to allow access to
431 # the local APIC (two pages)
432 x86_sys
.apicbridge
= Bridge(delay
='50ns')
433 x86_sys
.apicbridge
.slave
= x86_sys
.iobus
.master
434 x86_sys
.apicbridge
.master
= x86_sys
.membus
.slave
435 x86_sys
.apicbridge
.ranges
= [AddrRange(interrupts_address_space_base
,
436 interrupts_address_space_base
+
437 numCPUs
* APIC_range_size
441 x86_sys
.pc
.attachIO(x86_sys
.iobus
)
443 x86_sys
.system_port
= x86_sys
.membus
.slave
445 def connectX86RubySystem(x86_sys
):
447 x86_sys
.iobus
= IOXBar()
449 # add the ide to the list of dma devices that later need to attach to
451 x86_sys
._dma
_ports
= [x86_sys
.pc
.south_bridge
.ide
.dma
]
452 x86_sys
.pc
.attachIO(x86_sys
.iobus
, x86_sys
._dma
_ports
)
455 def makeX86System(mem_mode
, numCPUs
=1, mdesc
=None, workload
=None, Ruby
=False):
459 workload
= X86FsWorkload()
460 self
.workload
= workload
465 self
.readfile
= mdesc
.script()
467 self
.mem_mode
= mem_mode
470 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
471 # for various devices. Hence, if the physical memory size is greater than
472 # 3GB, we need to split it into two parts.
474 convert
.toMemorySize(mdesc
.mem()) - convert
.toMemorySize('3GB')
475 if excess_mem_size
<= 0:
476 self
.mem_ranges
= [AddrRange(mdesc
.mem())]
478 warn("Physical memory size specified is %s which is greater than " \
479 "3GB. Twice the number of memory controllers would be " \
480 "created." % (mdesc
.mem()))
482 self
.mem_ranges
= [AddrRange('3GB'),
483 AddrRange(Addr('4GB'), size
= excess_mem_size
)]
488 # Create and connect the busses required by each memory system
490 connectX86RubySystem(self
)
492 connectX86ClassicSystem(self
, numCPUs
)
494 self
.intrctrl
= IntrControl()
497 disks
= makeCowDisks(mdesc
.disks())
498 self
.pc
.south_bridge
.ide
.disks
= disks
500 # Add in a Bios information structure.
501 structures
= [X86SMBiosBiosInformation()]
502 workload
.smbios_table
.structures
= structures
504 # Set up the Intel MP table
507 for i
in range(numCPUs
):
508 bp
= X86IntelMPProcessor(
510 local_apic_version
= 0x14,
512 bootstrap
= (i
== 0))
513 base_entries
.append(bp
)
514 io_apic
= X86IntelMPIOAPIC(
518 address
= 0xfec00000)
519 self
.pc
.south_bridge
.io_apic
.apic_id
= io_apic
.id
520 base_entries
.append(io_apic
)
521 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
522 # but linux kernel cannot config PCI device if it was not connected to
523 # PCI bus, so we fix PCI bus id to 0, and ISA bus id to 1.
524 pci_bus
= X86IntelMPBus(bus_id
= 0, bus_type
='PCI ')
525 base_entries
.append(pci_bus
)
526 isa_bus
= X86IntelMPBus(bus_id
= 1, bus_type
='ISA ')
527 base_entries
.append(isa_bus
)
528 connect_busses
= X86IntelMPBusHierarchy(bus_id
=1,
529 subtractive_decode
=True, parent_bus
=0)
530 ext_entries
.append(connect_busses
)
531 pci_dev4_inta
= X86IntelMPIOIntAssignment(
532 interrupt_type
= 'INT',
533 polarity
= 'ConformPolarity',
534 trigger
= 'ConformTrigger',
536 source_bus_irq
= 0 + (4 << 2),
537 dest_io_apic_id
= io_apic
.id,
538 dest_io_apic_intin
= 16)
539 base_entries
.append(pci_dev4_inta
)
540 def assignISAInt(irq
, apicPin
):
541 assign_8259_to_apic
= X86IntelMPIOIntAssignment(
542 interrupt_type
= 'ExtInt',
543 polarity
= 'ConformPolarity',
544 trigger
= 'ConformTrigger',
546 source_bus_irq
= irq
,
547 dest_io_apic_id
= io_apic
.id,
548 dest_io_apic_intin
= 0)
549 base_entries
.append(assign_8259_to_apic
)
550 assign_to_apic
= X86IntelMPIOIntAssignment(
551 interrupt_type
= 'INT',
552 polarity
= 'ConformPolarity',
553 trigger
= 'ConformTrigger',
555 source_bus_irq
= irq
,
556 dest_io_apic_id
= io_apic
.id,
557 dest_io_apic_intin
= apicPin
)
558 base_entries
.append(assign_to_apic
)
561 for i
in range(3, 15):
563 workload
.intel_mp_table
.base_entries
= base_entries
564 workload
.intel_mp_table
.ext_entries
= ext_entries
568 def makeLinuxX86System(mem_mode
, numCPUs
=1, mdesc
=None, Ruby
=False,
570 # Build up the x86 system and then specialize it for Linux
571 self
= makeX86System(mem_mode
, numCPUs
, mdesc
, X86FsLinux(), Ruby
)
573 # We assume below that there's at least 1MB of memory. We'll require 2
574 # just to avoid corner cases.
575 phys_mem_size
= sum(map(lambda r
: r
.size(), self
.mem_ranges
))
576 assert(phys_mem_size
>= 0x200000)
577 assert(len(self
.mem_ranges
) <= 2)
581 # Mark the first megabyte of memory as reserved
582 X86E820Entry(addr
= 0, size
= '639kB', range_type
= 1),
583 X86E820Entry(addr
= 0x9fc00, size
= '385kB', range_type
= 2),
584 # Mark the rest of physical memory as available
585 X86E820Entry(addr
= 0x100000,
586 size
= '%dB' % (self
.mem_ranges
[0].size() - 0x100000),
590 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
591 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
592 # specific range can pass though bridge to iobus.
593 if len(self
.mem_ranges
) == 1:
594 entries
.append(X86E820Entry(addr
= self
.mem_ranges
[0].size(),
595 size
='%dB' % (0xC0000000 - self
.mem_ranges
[0].size()),
598 # Reserve the last 16kB of the 32-bit address space for the m5op interface
599 entries
.append(X86E820Entry(addr
=0xFFFF0000, size
='64kB', range_type
=2))
601 # In case the physical memory is greater than 3GB, we split it into two
602 # parts and add a separate e820 entry for the second part. This entry
603 # starts at 0x100000000, which is the first address after the space
604 # reserved for devices.
605 if len(self
.mem_ranges
) == 2:
606 entries
.append(X86E820Entry(addr
= 0x100000000,
607 size
= '%dB' % (self
.mem_ranges
[1].size()), range_type
= 1))
609 self
.workload
.e820_table
.entries
= entries
613 cmdline
= 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
614 self
.workload
.command_line
= fillInCmdline(mdesc
, cmdline
)
618 def makeDualRoot(full_system
, testSystem
, driveSystem
, dumpfile
):
619 self
= Root(full_system
= full_system
)
620 self
.testsys
= testSystem
621 self
.drivesys
= driveSystem
622 self
.etherlink
= EtherLink()
624 if hasattr(testSystem
, 'realview'):
625 self
.etherlink
.int0
= Parent
.testsys
.realview
.ethernet
.interface
626 self
.etherlink
.int1
= Parent
.drivesys
.realview
.ethernet
.interface
627 elif hasattr(testSystem
, 'tsunami'):
628 self
.etherlink
.int0
= Parent
.testsys
.tsunami
.ethernet
.interface
629 self
.etherlink
.int1
= Parent
.drivesys
.tsunami
.ethernet
.interface
631 fatal("Don't know how to connect these system together")
634 self
.etherdump
= EtherDump(file=dumpfile
)
635 self
.etherlink
.dump
= Parent
.etherdump
640 def makeDistRoot(testSystem
,
650 self
= Root(full_system
= True)
651 self
.testsys
= testSystem
653 self
.etherlink
= DistEtherLink(speed
= linkspeed
,
657 server_name
= server_name
,
658 server_port
= server_port
,
659 sync_start
= sync_start
,
660 sync_repeat
= sync_repeat
)
662 if hasattr(testSystem
, 'realview'):
663 self
.etherlink
.int0
= Parent
.testsys
.realview
.ethernet
.interface
664 elif hasattr(testSystem
, 'tsunami'):
665 self
.etherlink
.int0
= Parent
.testsys
.tsunami
.ethernet
.interface
667 fatal("Don't know how to connect DistEtherLink to this system")
670 self
.etherdump
= EtherDump(file=dumpfile
)
671 self
.etherlink
.dump
= Parent
.etherdump